MLK-19183-2 iMX8QXP SPL: board: imx8qxp_mek: Add spl specific implementation
This adds the spl specific code for imx8qxp. Signed-off-by: Abel Vesa <abel.vesa@nxp.com>zero-sugar
parent
7586aa50fd
commit
30ac9734f6
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@ -5,3 +5,7 @@
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#
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obj-y += imx8qxp_mek.o
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ifdef CONFIG_SPL_BUILD
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obj-y += spl.o
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endif
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@ -100,6 +100,7 @@ int board_early_init_f(void)
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#define USDHC1_CD_GPIO IMX_GPIO_NR(4, 22)
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#ifndef CONFIG_SPL_BUILD
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static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
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{USDHC1_BASE_ADDR, 0, 8},
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{USDHC2_BASE_ADDR, 0, 4},
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@ -193,6 +194,7 @@ int board_mmc_getcd(struct mmc *mmc)
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return ret;
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}
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#endif /* CONFIG_SPL_BUILD */
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#endif /* CONFIG_FSL_ESDHC */
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@ -0,0 +1,203 @@
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/*
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* Copyright 2018 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <spl.h>
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#include <malloc.h>
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#include <errno.h>
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#include <netdev.h>
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#include <fsl_ifc.h>
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#include <fdt_support.h>
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#include <linux/libfdt.h>
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#include <environment.h>
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#include <fsl_esdhc.h>
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#include <i2c.h>
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#include "pca953x.h"
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/arch/clock.h>
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#include <asm/mach-imx/sci/sci.h>
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#include <asm/arch/imx8-pins.h>
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#include <dm.h>
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#include <imx8_hsio.h>
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#include <usb.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/video.h>
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#include <asm/arch/video_common.h>
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#include <power-domain.h>
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#include "../common/tcpc.h"
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#include <cdns3-uboot.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define ESDHC_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
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| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
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#define ESDHC_CLK_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
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| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PD << PADRING_PULL_SHIFT))
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#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
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| (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
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#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
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| (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
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#define FSPI_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
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| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
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#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
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| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
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#define I2C_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
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| (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
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#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
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| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
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#ifdef CONFIG_FSL_ESDHC
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#define USDHC1_CD_GPIO IMX_GPIO_NR(4, 22)
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static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
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{USDHC1_BASE_ADDR, 0, 8},
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{USDHC2_BASE_ADDR, 0, 4},
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};
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static iomux_cfg_t emmc0[] = {
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SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
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SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
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SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
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SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
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SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
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SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
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SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
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SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
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SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
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SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
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SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
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};
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static iomux_cfg_t usdhc1_sd[] = {
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SC_P_USDHC1_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
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SC_P_USDHC1_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
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SC_P_USDHC1_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
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SC_P_USDHC1_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
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SC_P_USDHC1_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
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SC_P_USDHC1_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
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SC_P_USDHC1_WP | MUX_PAD_CTRL(ESDHC_PAD_CTRL), /* Mux for WP */
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SC_P_USDHC1_CD_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), /* Mux for CD, GPIO4 IO22 */
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SC_P_USDHC1_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
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SC_P_USDHC1_VSELECT | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
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};
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void spl_dram_init(void)
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{
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/* do nothing for now */
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}
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int board_mmc_init(bd_t *bis)
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{
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int i, ret;
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sc_ipc_t ipcHndl = 0;
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ipcHndl = gd->arch.ipc_channel_handle;
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/*
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* According to the board_mmc_init() the following map is done:
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* (U-boot device node) (Physical Port)
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* mmc0 USDHC1
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* mmc1 USDHC2
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*/
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for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
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switch (i) {
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case 0:
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ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_SDHC_0, SC_PM_PW_MODE_ON);
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if (ret != SC_ERR_NONE)
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return ret;
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imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0));
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init_clk_usdhc(0);
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usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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break;
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case 1:
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ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_SDHC_1, SC_PM_PW_MODE_ON);
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if (ret != SC_ERR_NONE)
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return ret;
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ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_GPIO_3, SC_PM_PW_MODE_ON);
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if (ret != SC_ERR_NONE)
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return ret;
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imx8_iomux_setup_multiple_pads(usdhc1_sd, ARRAY_SIZE(usdhc1_sd));
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init_clk_usdhc(1);
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usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
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gpio_request(USDHC1_CD_GPIO, "sd1_cd");
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gpio_direction_input(USDHC1_CD_GPIO);
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break;
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default:
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printf("Warning: you configured more USDHC controllers"
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"(%d) than supported by the board\n", i + 1);
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return 0;
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}
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ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
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if (ret) {
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printf("Warning: failed to initialize mmc dev %d\n", i);
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return ret;
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}
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}
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return 0;
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}
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret = 0;
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switch (cfg->esdhc_base) {
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case USDHC1_BASE_ADDR:
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ret = 1; /* eMMC */
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break;
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case USDHC2_BASE_ADDR:
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ret = !gpio_get_value(USDHC1_CD_GPIO);
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break;
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}
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return ret;
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}
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#endif
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void spl_board_init(void)
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{
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/* DDR initialization */
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spl_dram_init();
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puts("Normal Boot\n");
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}
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void board_init_f(ulong dummy)
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{
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/* Clear global data */
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memset((void *)gd, 0, sizeof(gd_t));
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arch_cpu_init();
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board_early_init_f();
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timer_init();
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preloader_console_init();
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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board_init_r(NULL, 0);
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}
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