ARM: uniphier: allow to enable multiple SoCs
Before this commit, the Kconfig menu in mach-uniphier only allowed us
to choose one SoC to be compiled. Each SoC has its own defconfig file
for the build-test coverage. Consequently, some defconfig files are
duplicated with only the difference in CONFIG_DEFAULT_DEVICE_TREE and
CONFIG_{SOC_NAME}=y.
Now, most of board-specific parameters have been moved to device trees,
so it makes sense to include init code of multiple SoCs into a single
image as long as the SoCs have similar architecture. In fact, some
SoCs of UniPhier family are very similar:
- PH1-LD4 and PH1-sLD8
- PH1-LD6b and ProXstream2 (will be added in the upcoming commit)
This commit will be helpful to merge some defconfig files for better
maintainability.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
utp
Masahiro Yamada
parent
5451b777de
commit
323d1f9d5b
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@ -6,25 +6,32 @@ config SYS_CONFIG_NAME
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config UNIPHIER_SMP
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bool
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choice
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prompt "UniPhier SoC select"
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default ARCH_UNIPHIER_PH1_PRO4
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config ARCH_UNIPHIER_PH1_SLD3
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bool "PH1-sLD3"
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bool "UniPhier PH1-sLD3 SoC"
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select UNIPHIER_SMP
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help
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This enables support for UniPhier PH1-sLD3 SoC.
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config ARCH_UNIPHIER_PH1_LD4
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bool "PH1-LD4"
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bool "UniPhier PH1-LD4 SoC"
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depends on !ARCH_UNIPHIER_PH1_SLD3
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help
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This enables support for UniPhier PH1-LD4 SoC.
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config ARCH_UNIPHIER_PH1_PRO4
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bool "PH1-Pro4"
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bool "UniPhier PH1-Pro4 SoC"
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select UNIPHIER_SMP
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depends on !ARCH_UNIPHIER_PH1_SLD3 && \
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!ARCH_UNIPHIER_PH1_LD4 && \
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!ARCH_UNIPHIER_PH1_SLD8
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help
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This enables support for UniPhier PH1-Pro4 SoC.
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config ARCH_UNIPHIER_PH1_SLD8
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bool "PH1-sLD8"
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endchoice
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bool "UniPhier PH1-sLD8 SoC"
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depends on !ARCH_UNIPHIER_PH1_SLD3
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help
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This enables support for UniPhier PH1-sLD8 SoC.
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config MICRO_SUPPORT_CARD
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bool "Use Micro Support Card"
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@ -48,22 +55,4 @@ config CMD_DDRPHY_DUMP
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The command "ddrphy" shows the resulting parameters of DDR PHY
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training; it is useful for the evaluation of DDR PHY training.
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choice
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prompt "DDR3 Frequency select"
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config DDR_FREQ_1600
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bool "DDR3 1600"
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depends on ARCH_UNIPHIER_PH1_SLD3 || ARCH_UNIPHIER_PH1_LD4 || ARCH_UNIPHIER_PH1_PRO4
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config DDR_FREQ_1333
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bool "DDR3 1333"
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depends on ARCH_UNIPHIER_PH1_SLD3 || ARCH_UNIPHIER_PH1_LD4 || ARCH_UNIPHIER_PH1_SLD8
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endchoice
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config DDR_FREQ
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int
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default 1333 if DDR_FREQ_1333
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default 1600 if DDR_FREQ_1600
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endif
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@ -6,9 +6,10 @@ ifdef CONFIG_SPL_BUILD
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obj-y += lowlevel_init.o
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obj-y += init_page_table.o
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obj-y += spl.o
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obj-y += memconf.o
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obj-y += ddrphy_training.o
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obj-y += boards.o
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obj-y += init/ bcu/ memconf/ pll/ early-clk/ early-pinctrl/ umc/ ddrphy/
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obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/
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obj-$(CONFIG_DEBUG_LL) += debug_ll.o
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@ -27,13 +28,12 @@ obj-y += cache_uniphier.o
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obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
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obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o
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obj-y += pinctrl/ clk/
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endif
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obj-y += timer.o
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obj-y += soc_info.o
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obj-y += boot-mode/
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obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o
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obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += ph1-sld3/
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obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += ph1-ld4/
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obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += ph1-pro4/
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obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += ph1-sld8/
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@ -0,0 +1,3 @@
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obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += bcu-ph1-sld3.o
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obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += bcu-ph1-ld4.o
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obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += bcu-ph1-ld4.o
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@ -4,13 +4,13 @@
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/io.h>
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#include <mach/bcu-regs.h>
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#include <mach/init.h>
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#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
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void bcu_init(void)
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int ph1_ld4_bcu_init(const struct uniphier_board_data *bd)
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{
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int shift;
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@ -21,7 +21,7 @@ void bcu_init(void)
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writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */
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/* Specify DDR channel */
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shift = (CONFIG_SDRAM1_BASE - CONFIG_SDRAM0_BASE) / 0x04000000 * 4;
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shift = (bd->dram_ch1_base - bd->dram_ch0_base) / 0x04000000 * 4;
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writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
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shift -= 32;
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@ -29,4 +29,6 @@ void bcu_init(void)
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shift -= 32;
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writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
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return 0;
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}
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@ -4,13 +4,13 @@
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/io.h>
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#include <mach/bcu-regs.h>
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#include <mach/init.h>
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#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
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void bcu_init(void)
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int ph1_sld3_bcu_init(const struct uniphier_board_data *bd)
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{
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int shift;
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@ -25,7 +25,7 @@ void bcu_init(void)
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writel(0x24440000, BCSCR5);
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/* Specify DDR channel */
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shift = (CONFIG_SDRAM1_BASE - CONFIG_SDRAM0_BASE) / 0x04000000 * 4;
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shift = (bd->dram_ch1_base - bd->dram_ch0_base) / 0x04000000 * 4;
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writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
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shift -= 32;
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@ -33,4 +33,6 @@ void bcu_init(void)
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shift -= 32;
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writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
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return 0;
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}
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@ -4,20 +4,46 @@
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <mach/init.h>
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#include <mach/micro-support-card.h>
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void pin_init(void);
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void clkrst_init(void);
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#include <mach/soc_info.h>
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int board_early_init_f(void)
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{
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led_puts("U0");
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pin_init();
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led_puts("U1");
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clkrst_init();
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switch (uniphier_get_soc_type()) {
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#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
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case SOC_UNIPHIER_PH1_SLD3:
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ph1_sld3_pin_init();
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led_puts("U1");
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ph1_ld4_clk_init();
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break;
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
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case SOC_UNIPHIER_PH1_LD4:
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ph1_ld4_pin_init();
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led_puts("U1");
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ph1_ld4_clk_init();
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break;
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
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case SOC_UNIPHIER_PH1_PRO4:
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ph1_pro4_pin_init();
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led_puts("U1");
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ph1_pro4_clk_init();
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break;
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
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case SOC_UNIPHIER_PH1_SLD8:
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ph1_sld8_pin_init();
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led_puts("U1");
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ph1_ld4_clk_init();
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break;
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#endif
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default:
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break;
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}
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led_puts("U2");
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@ -0,0 +1,93 @@
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/*
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* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <libfdt.h>
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#include <linux/kernel.h>
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#include <mach/init.h>
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#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
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static const struct uniphier_board_data ph1_sld3_data = {
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.dram_ch0_base = 0x80000000,
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.dram_ch0_size = 0x20000000,
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.dram_ch0_width = 32,
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.dram_ch1_base = 0xc0000000,
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.dram_ch1_size = 0x20000000,
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.dram_ch1_width = 16,
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.dram_ch2_base = 0xc0000000,
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.dram_ch2_size = 0x10000000,
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.dram_ch2_width = 16,
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.dram_freq = 1600,
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};
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
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static const struct uniphier_board_data ph1_ld4_data = {
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.dram_ch0_base = 0x80000000,
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.dram_ch0_size = 0x10000000,
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.dram_ch0_width = 16,
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.dram_ch1_base = 0x90000000,
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.dram_ch1_size = 0x10000000,
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.dram_ch1_width = 16,
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.dram_freq = 1600,
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};
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
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static const struct uniphier_board_data ph1_pro4_data = {
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.dram_ch0_base = 0x80000000,
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.dram_ch0_size = 0x20000000,
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.dram_ch0_width = 32,
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.dram_ch1_base = 0xa0000000,
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.dram_ch1_size = 0x20000000,
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.dram_ch1_width = 32,
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.dram_freq = 1600,
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};
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
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static const struct uniphier_board_data ph1_sld8_data = {
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.dram_ch0_base = 0x80000000,
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.dram_ch0_size = 0x10000000,
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.dram_ch0_width = 16,
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.dram_ch1_base = 0x90000000,
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.dram_ch1_size = 0x10000000,
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.dram_ch1_width = 16,
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.dram_freq = 1333,
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};
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#endif
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struct uniphier_board_id {
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const char *compatible;
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const struct uniphier_board_data *param;
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};
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static const struct uniphier_board_id uniphier_boards[] = {
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#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
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{ "socionext,ph1-sld3", &ph1_sld3_data, },
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
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{ "socionext,ph1-ld4", &ph1_ld4_data, },
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
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{ "socionext,ph1-pro4", &ph1_pro4_data, },
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
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{ "socionext,ph1-sld8", &ph1_sld8_data, },
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#endif
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};
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const struct uniphier_board_data *uniphier_get_board_param(const void *fdt)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(uniphier_boards); i++) {
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if (!fdt_node_check_compatible(fdt, 0,
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uniphier_boards[i].compatible))
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return uniphier_boards[i].param;
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}
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return NULL;
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}
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@ -0,0 +1,6 @@
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obj-y += boot-mode.o
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obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += boot-mode-ph1-sld3.o
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obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += boot-mode-ph1-ld4.o
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obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += boot-mode-ph1-ld4.o
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obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += boot-mode-ph1-ld4.o
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@ -44,22 +44,31 @@ struct boot_device_info boot_device_table[] = {
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{ /* sentinel */ }
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};
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int get_boot_mode_sel(void)
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static int get_boot_mode_sel(void)
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{
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return (readl(SG_PINMON0) >> 1) & 0x1f;
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}
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u32 spl_boot_device(void)
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u32 ph1_ld4_boot_device(void)
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{
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int boot_mode;
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if (boot_is_swapped())
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return BOOT_DEVICE_NOR;
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boot_mode = get_boot_mode_sel();
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return boot_device_table[boot_mode].type;
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}
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void ph1_ld4_boot_mode_show(void)
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{
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int mode_sel, i;
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mode_sel = get_boot_mode_sel();
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puts("Boot Mode Pin:\n");
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for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
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printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
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boot_device_table[i].info);
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}
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@ -11,7 +11,7 @@
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#include <mach/sg-regs.h>
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#include <mach/sbc-regs.h>
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struct boot_device_info boot_device_table[] = {
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static struct boot_device_info boot_device_table[] = {
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NONE, "External Master"},
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{BOOT_DEVICE_NONE, "Reserved"},
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@ -76,22 +76,31 @@ struct boot_device_info boot_device_table[] = {
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{ /* sentinel */ }
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};
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int get_boot_mode_sel(void)
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static int get_boot_mode_sel(void)
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{
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return readl(SG_PINMON0) & 0x3f;
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}
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u32 spl_boot_device(void)
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u32 ph1_sld3_boot_device(void)
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{
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int boot_mode;
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if (boot_is_swapped())
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return BOOT_DEVICE_NOR;
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boot_mode = get_boot_mode_sel();
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return boot_device_table[boot_mode].type;
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}
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void ph1_sld3_boot_mode_show(void)
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{
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int mode_sel, i;
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mode_sel = get_boot_mode_sel();
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puts("Boot Mode Pin:\n");
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for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
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printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
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boot_device_table[i].info);
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}
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@ -0,0 +1,35 @@
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/*
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* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <spl.h>
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#include <linux/io.h>
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#include <mach/boot-device.h>
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#include <mach/sbc-regs.h>
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#include <mach/soc_info.h>
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u32 spl_boot_device(void)
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{
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if (boot_is_swapped())
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return BOOT_DEVICE_NOR;
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switch (uniphier_get_soc_type()) {
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#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
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case SOC_UNIPHIER_PH1_SLD3:
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return ph1_sld3_boot_device();
|
||||
#endif
|
||||
#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \
|
||||
defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) || \
|
||||
defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
|
||||
case SOC_UNIPHIER_PH1_LD4:
|
||||
case SOC_UNIPHIER_PH1_PRO4:
|
||||
case SOC_UNIPHIER_PH1_SLD8:
|
||||
return ph1_ld4_boot_device();
|
||||
#endif
|
||||
default:
|
||||
return BOOT_DEVICE_NONE;
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += clk-ph1-ld4.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += clk-ph1-ld4.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += clk-ph1-pro4.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += clk-ph1-ld4.o
|
||||
|
|
@ -5,9 +5,10 @@
|
|||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <mach/init.h>
|
||||
#include <mach/sc-regs.h>
|
||||
|
||||
void clkrst_init(void)
|
||||
void ph1_ld4_clk_init(void)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
|
|
@ -5,9 +5,10 @@
|
|||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <mach/init.h>
|
||||
#include <mach/sc-regs.h>
|
||||
|
||||
void clkrst_init(void)
|
||||
void ph1_pro4_clk_init(void)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
|
|
@ -1,6 +1,5 @@
|
|||
/*
|
||||
* Copyright (C) 2014 Panasonic Corporation
|
||||
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
|
||||
* Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
|
@ -8,20 +7,30 @@
|
|||
#include <common.h>
|
||||
#include <mach/boot-device.h>
|
||||
#include <mach/sbc-regs.h>
|
||||
#include <mach/soc_info.h>
|
||||
|
||||
static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
int mode_sel, i;
|
||||
|
||||
printf("Boot Swap: %s\n\n", boot_is_swapped() ? "ON" : "OFF");
|
||||
|
||||
mode_sel = get_boot_mode_sel();
|
||||
|
||||
puts("Boot Mode Pin:\n");
|
||||
|
||||
for (i = 0; boot_device_table[i].info; i++)
|
||||
printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
|
||||
boot_device_table[i].info);
|
||||
switch (uniphier_get_soc_type()) {
|
||||
#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
|
||||
case SOC_UNIPHIER_PH1_SLD3:
|
||||
ph1_sld3_boot_mode_show();
|
||||
break;
|
||||
#endif
|
||||
#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \
|
||||
defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) || \
|
||||
defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
|
||||
case SOC_UNIPHIER_PH1_LD4:
|
||||
case SOC_UNIPHIER_PH1_PRO4:
|
||||
case SOC_UNIPHIER_PH1_SLD8:
|
||||
ph1_ld4_boot_mode_show();
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,3 @@
|
|||
obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += ddrphy-training.o ddrphy-ph1-ld4.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += ddrphy-training.o ddrphy-ph1-pro4.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += ddrphy-training.o ddrphy-ph1-sld8.o
|
||||
|
|
@ -8,7 +8,7 @@
|
|||
#include <linux/io.h>
|
||||
#include <mach/ddrphy-regs.h>
|
||||
|
||||
void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
|
||||
int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
|
|
@ -67,4 +67,6 @@ void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
|
|||
|
||||
writel(0x0300C473, &phy->pgcr[1]);
|
||||
writel(0x0000005D, &phy->zq[0].cr[1]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -8,7 +8,7 @@
|
|||
#include <linux/io.h>
|
||||
#include <mach/ddrphy-regs.h>
|
||||
|
||||
void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
|
||||
int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
|
|
@ -67,4 +67,6 @@ void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
|
|||
|
||||
writel(0x0300C473, &phy->pgcr[1]);
|
||||
writel(0x0000005D, &phy->zq[0].cr[1]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -9,7 +9,7 @@
|
|||
#include <linux/io.h>
|
||||
#include <mach/ddrphy-regs.h>
|
||||
|
||||
void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
|
||||
int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
|
|
@ -72,4 +72,6 @@ void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
|
|||
|
||||
writel(0x0300C473, &phy->pgcr[1]);
|
||||
writel(0x0000005D, &phy->zq[0].cr[1]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += early-clk-ph1-ld4.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += early-clk-ph1-ld4.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += early-clk-ph1-ld4.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += early-clk-ph1-ld4.o
|
||||
|
|
@ -7,9 +7,10 @@
|
|||
#include <common.h>
|
||||
#include <spl.h>
|
||||
#include <linux/io.h>
|
||||
#include <mach/init.h>
|
||||
#include <mach/sc-regs.h>
|
||||
|
||||
void early_clkrst_init(void)
|
||||
int ph1_ld4_early_clk_init(const struct uniphier_board_data *bd)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
|
|
@ -27,4 +28,6 @@ void early_clkrst_init(void)
|
|||
tmp |= SC_CLKCTRL_CEN_UMC | SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
|
||||
writel(tmp, SC_CLKCTRL);
|
||||
readl(SC_CLKCTRL); /* dummy read */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1 @@
|
|||
obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += early-pinctrl-ph1-sld3.o
|
||||
|
|
@ -4,9 +4,10 @@
|
|||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <mach/init.h>
|
||||
#include <mach/sg-regs.h>
|
||||
|
||||
void early_pin_init(void)
|
||||
int ph1_sld3_early_pin_init(const struct uniphier_board_data *bd)
|
||||
{
|
||||
/* Comment format: PAD Name -> Function Name */
|
||||
|
||||
|
|
@ -20,4 +21,6 @@ void early_pin_init(void)
|
|||
sg_set_pinsel(96, 2, 4, 4); /* RXD2 */
|
||||
sg_set_pinsel(102, 2, 4, 4); /* TXD2 */
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1,6 +1,5 @@
|
|||
/*
|
||||
* Copyright (C) 2011-2014 Panasonic Corporation
|
||||
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
|
||||
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
|
@ -8,13 +7,15 @@
|
|||
#ifndef _ASM_BOOT_DEVICE_H_
|
||||
#define _ASM_BOOT_DEVICE_H_
|
||||
|
||||
int get_boot_mode_sel(void);
|
||||
|
||||
struct boot_device_info {
|
||||
u32 type;
|
||||
char *info;
|
||||
};
|
||||
|
||||
extern struct boot_device_info boot_device_table[];
|
||||
u32 ph1_sld3_boot_device(void);
|
||||
u32 ph1_ld4_boot_device(void);
|
||||
|
||||
void ph1_sld3_boot_mode_show(void);
|
||||
void ph1_ld4_boot_mode_show(void);
|
||||
|
||||
#endif /* _ASM_BOOT_DEVICE_H_ */
|
||||
|
|
|
|||
|
|
@ -168,7 +168,9 @@ struct ddrphy {
|
|||
#define DDRPHY_BASE(ch, phy) (0x5bc01000 + 0x200000 * (ch) + 0x1000 * (phy))
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
|
||||
int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
|
||||
int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
|
||||
int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
|
||||
void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank);
|
||||
int ddrphy_training(struct ddrphy __iomem *phy);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,83 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __MACH_INIT_H
|
||||
#define __MACH_INIT_H
|
||||
|
||||
struct uniphier_board_data {
|
||||
unsigned long dram_ch0_base;
|
||||
unsigned long dram_ch0_size;
|
||||
unsigned long dram_ch0_width;
|
||||
unsigned long dram_ch1_base;
|
||||
unsigned long dram_ch1_size;
|
||||
unsigned long dram_ch1_width;
|
||||
unsigned long dram_ch2_base;
|
||||
unsigned long dram_ch2_size;
|
||||
unsigned long dram_ch2_width;
|
||||
unsigned int dram_freq;
|
||||
};
|
||||
|
||||
const struct uniphier_board_data *uniphier_get_board_param(const void *fdt);
|
||||
|
||||
int ph1_sld3_init(const struct uniphier_board_data *bd);
|
||||
int ph1_ld4_init(const struct uniphier_board_data *bd);
|
||||
int ph1_pro4_init(const struct uniphier_board_data *bd);
|
||||
int ph1_sld8_init(const struct uniphier_board_data *bd);
|
||||
|
||||
#if defined(CONFIG_MICRO_SUPPORT_CARD)
|
||||
int ph1_sld3_sbc_init(const struct uniphier_board_data *bd);
|
||||
int ph1_ld4_sbc_init(const struct uniphier_board_data *bd);
|
||||
int ph1_pro4_sbc_init(const struct uniphier_board_data *bd);
|
||||
#else
|
||||
static inline int ph1_sld3_sbc_init(const struct uniphier_board_data *bd)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int ph1_ld4_sbc_init(const struct uniphier_board_data *bd)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int ph1_pro4_sbc_init(const struct uniphier_board_data *bd)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int ph1_sld3_bcu_init(const struct uniphier_board_data *bd);
|
||||
int ph1_ld4_bcu_init(const struct uniphier_board_data *bd);
|
||||
|
||||
int memconf_init(const struct uniphier_board_data *bd);
|
||||
int ph1_sld3_memconf_init(const struct uniphier_board_data *bd);
|
||||
|
||||
int ph1_sld3_pll_init(const struct uniphier_board_data *bd);
|
||||
int ph1_ld4_pll_init(const struct uniphier_board_data *bd);
|
||||
int ph1_pro4_pll_init(const struct uniphier_board_data *bd);
|
||||
int ph1_sld8_pll_init(const struct uniphier_board_data *bd);
|
||||
|
||||
int ph1_sld3_enable_dpll_ssc(const struct uniphier_board_data *bd);
|
||||
int ph1_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd);
|
||||
|
||||
int ph1_ld4_early_clk_init(const struct uniphier_board_data *bd);
|
||||
|
||||
int ph1_sld3_early_pin_init(const struct uniphier_board_data *bd);
|
||||
|
||||
int ph1_ld4_umc_init(const struct uniphier_board_data *bd);
|
||||
int ph1_pro4_umc_init(const struct uniphier_board_data *bd);
|
||||
int ph1_sld8_umc_init(const struct uniphier_board_data *bd);
|
||||
|
||||
void ph1_sld3_pin_init(void);
|
||||
void ph1_ld4_pin_init(void);
|
||||
void ph1_pro4_pin_init(void);
|
||||
void ph1_sld8_pin_init(void);
|
||||
|
||||
void ph1_ld4_clk_init(void);
|
||||
void ph1_pro4_clk_init(void);
|
||||
|
||||
#define pr_err(fmt, args...) printf(fmt, ##args)
|
||||
|
||||
#endif /* __MACH_INIT_H */
|
||||
|
|
@ -25,26 +25,32 @@
|
|||
/* Memory Configuration */
|
||||
#define SG_MEMCONF (SG_CTRL_BASE | 0x0400)
|
||||
|
||||
#define SG_MEMCONF_CH0_SZ_MASK ((0x1 << 10) | (0x03 << 0))
|
||||
#define SG_MEMCONF_CH0_SZ_64M ((0x0 << 10) | (0x01 << 0))
|
||||
#define SG_MEMCONF_CH0_SZ_128M ((0x0 << 10) | (0x02 << 0))
|
||||
#define SG_MEMCONF_CH0_SZ_256M ((0x0 << 10) | (0x03 << 0))
|
||||
#define SG_MEMCONF_CH0_SZ_512M ((0x1 << 10) | (0x00 << 0))
|
||||
#define SG_MEMCONF_CH0_SZ_1G ((0x1 << 10) | (0x01 << 0))
|
||||
#define SG_MEMCONF_CH0_NUM_MASK (0x1 << 8)
|
||||
#define SG_MEMCONF_CH0_NUM_1 (0x1 << 8)
|
||||
#define SG_MEMCONF_CH0_NUM_2 (0x0 << 8)
|
||||
|
||||
#define SG_MEMCONF_CH1_SZ_MASK ((0x1 << 11) | (0x03 << 2))
|
||||
#define SG_MEMCONF_CH1_SZ_64M ((0x0 << 11) | (0x01 << 2))
|
||||
#define SG_MEMCONF_CH1_SZ_128M ((0x0 << 11) | (0x02 << 2))
|
||||
#define SG_MEMCONF_CH1_SZ_256M ((0x0 << 11) | (0x03 << 2))
|
||||
#define SG_MEMCONF_CH1_SZ_512M ((0x1 << 11) | (0x00 << 2))
|
||||
#define SG_MEMCONF_CH1_SZ_1G ((0x1 << 11) | (0x01 << 2))
|
||||
#define SG_MEMCONF_CH1_NUM_MASK (0x1 << 9)
|
||||
#define SG_MEMCONF_CH1_NUM_1 (0x1 << 9)
|
||||
#define SG_MEMCONF_CH1_NUM_2 (0x0 << 9)
|
||||
|
||||
#define SG_MEMCONF_CH2_SZ_MASK ((0x1 << 26) | (0x03 << 16))
|
||||
#define SG_MEMCONF_CH2_SZ_64M ((0x0 << 26) | (0x01 << 16))
|
||||
#define SG_MEMCONF_CH2_SZ_128M ((0x0 << 26) | (0x02 << 16))
|
||||
#define SG_MEMCONF_CH2_SZ_256M ((0x0 << 26) | (0x03 << 16))
|
||||
#define SG_MEMCONF_CH2_SZ_512M ((0x1 << 26) | (0x00 << 16))
|
||||
#define SG_MEMCONF_CH2_NUM_MASK (0x1 << 24)
|
||||
#define SG_MEMCONF_CH2_NUM_1 (0x1 << 24)
|
||||
#define SG_MEMCONF_CH2_NUM_2 (0x0 << 24)
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __MACH_SOC_INFO_H__
|
||||
#define __MACH_SOC_INFO_H__
|
||||
|
||||
enum uniphier_soc_id {
|
||||
SOC_UNIPHIER_PH1_SLD3,
|
||||
SOC_UNIPHIER_PH1_LD4,
|
||||
SOC_UNIPHIER_PH1_PRO4,
|
||||
SOC_UNIPHIER_PH1_SLD8,
|
||||
SOC_UNIPHIER_PH1_PRO5,
|
||||
SOC_UNIPHIER_PROXSTREAM2,
|
||||
SOC_UNIPHIER_PH1_LD6B,
|
||||
SOC_UNIPHIER_UNKNOWN,
|
||||
};
|
||||
|
||||
#define UNIPHIER_NR_ENABLED_SOCS \
|
||||
IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD3) + \
|
||||
IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD4) + \
|
||||
IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_PRO4) + \
|
||||
IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD8) + \
|
||||
IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_PRO5) + \
|
||||
IS_ENABLED(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) + \
|
||||
IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
|
||||
|
||||
#define UNIPHIER_MULTI_SOC ((UNIPHIER_NR_ENABLED_SOCS) > 1)
|
||||
|
||||
#if UNIPHIER_MULTI_SOC
|
||||
enum uniphier_soc_id uniphier_get_soc_type(void);
|
||||
#else
|
||||
static inline enum uniphier_soc_id uniphier_get_soc_type(void)
|
||||
{
|
||||
#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
|
||||
return SOC_UNIPHIER_PH1_SLD3;
|
||||
#endif
|
||||
#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
|
||||
return SOC_UNIPHIER_PH1_LD4;
|
||||
#endif
|
||||
#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
|
||||
return SOC_UNIPHIER_PH1_PRO4;
|
||||
#endif
|
||||
#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
|
||||
return SOC_UNIPHIER_PH1_SLD8;
|
||||
#endif
|
||||
#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
|
||||
return SOC_UNIPHIER_PH1_PRO5;
|
||||
#endif
|
||||
#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
|
||||
return SOC_UNIPHIER_PROXSTREAM2;
|
||||
#endif
|
||||
#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
|
||||
return SOC_UNIPHIER_PH1_LD6B;
|
||||
#endif
|
||||
|
||||
return SOC_UNIPHIER_UNKNOWN;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __MACH_SOC_INFO_H__ */
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
obj-y += init.o
|
||||
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += init-ph1-sld3.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += init-ph1-ld4.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += init-ph1-pro4.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += init-ph1-sld8.o
|
||||
|
|
@ -7,60 +7,31 @@
|
|||
#include <common.h>
|
||||
#include <spl.h>
|
||||
#include <linux/compiler.h>
|
||||
#include <mach/init.h>
|
||||
#include <mach/micro-support-card.h>
|
||||
|
||||
void __weak bcu_init(void)
|
||||
int ph1_ld4_init(const struct uniphier_board_data *bd)
|
||||
{
|
||||
};
|
||||
ph1_ld4_bcu_init(bd);
|
||||
|
||||
void __weak sbc_init(void)
|
||||
{
|
||||
};
|
||||
|
||||
void __weak sg_init(void)
|
||||
{
|
||||
};
|
||||
|
||||
void __weak early_pin_init(void)
|
||||
{
|
||||
};
|
||||
|
||||
void sbc_init(void);
|
||||
void sg_init(void);
|
||||
void pll_init(void);
|
||||
void pin_init(void);
|
||||
void memconf_init(void);
|
||||
void early_clkrst_init(void);
|
||||
void early_pin_init(void);
|
||||
int umc_init(void);
|
||||
void enable_dpll_ssc(void);
|
||||
|
||||
void spl_board_init(void)
|
||||
{
|
||||
bcu_init();
|
||||
|
||||
sbc_init();
|
||||
|
||||
sg_init();
|
||||
ph1_ld4_sbc_init(bd);
|
||||
|
||||
support_card_reset();
|
||||
|
||||
pll_init();
|
||||
ph1_ld4_pll_init(bd);
|
||||
|
||||
support_card_init();
|
||||
|
||||
led_puts("L0");
|
||||
|
||||
memconf_init();
|
||||
memconf_init(bd);
|
||||
|
||||
led_puts("L1");
|
||||
|
||||
early_clkrst_init();
|
||||
ph1_ld4_early_clk_init(bd);
|
||||
|
||||
led_puts("L2");
|
||||
|
||||
early_pin_init();
|
||||
|
||||
led_puts("L3");
|
||||
|
||||
#ifdef CONFIG_SPL_SERIAL_SUPPORT
|
||||
|
|
@ -72,7 +43,7 @@ void spl_board_init(void)
|
|||
{
|
||||
int res;
|
||||
|
||||
res = umc_init();
|
||||
res = ph1_ld4_umc_init(bd);
|
||||
if (res < 0) {
|
||||
while (1)
|
||||
;
|
||||
|
|
@ -81,7 +52,9 @@ void spl_board_init(void)
|
|||
|
||||
led_puts("L5");
|
||||
|
||||
enable_dpll_ssc();
|
||||
ph1_ld4_enable_dpll_ssc(bd);
|
||||
|
||||
led_puts("L6");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
/*
|
||||
* Copyright (C) 2013-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <spl.h>
|
||||
#include <linux/compiler.h>
|
||||
#include <mach/init.h>
|
||||
#include <mach/micro-support-card.h>
|
||||
|
||||
int ph1_pro4_init(const struct uniphier_board_data *bd)
|
||||
{
|
||||
ph1_pro4_sbc_init(bd);
|
||||
|
||||
support_card_reset();
|
||||
|
||||
ph1_pro4_pll_init(bd);
|
||||
|
||||
support_card_init();
|
||||
|
||||
led_puts("L0");
|
||||
|
||||
memconf_init(bd);
|
||||
|
||||
led_puts("L1");
|
||||
|
||||
ph1_ld4_early_clk_init(bd);
|
||||
|
||||
led_puts("L2");
|
||||
|
||||
led_puts("L3");
|
||||
|
||||
#ifdef CONFIG_SPL_SERIAL_SUPPORT
|
||||
preloader_console_init();
|
||||
#endif
|
||||
|
||||
led_puts("L4");
|
||||
|
||||
{
|
||||
int res;
|
||||
|
||||
res = ph1_pro4_umc_init(bd);
|
||||
if (res < 0) {
|
||||
while (1)
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
led_puts("L5");
|
||||
|
||||
ph1_ld4_enable_dpll_ssc(bd);
|
||||
|
||||
led_puts("L6");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* Copyright (C) 2013-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <spl.h>
|
||||
#include <linux/compiler.h>
|
||||
#include <mach/init.h>
|
||||
#include <mach/micro-support-card.h>
|
||||
|
||||
int ph1_sld3_init(const struct uniphier_board_data *bd)
|
||||
{
|
||||
ph1_sld3_bcu_init(bd);
|
||||
|
||||
ph1_sld3_sbc_init(bd);
|
||||
|
||||
support_card_reset();
|
||||
|
||||
ph1_sld3_pll_init(bd);
|
||||
|
||||
support_card_init();
|
||||
|
||||
led_puts("L0");
|
||||
|
||||
memconf_init(bd);
|
||||
ph1_sld3_memconf_init(bd);
|
||||
|
||||
led_puts("L1");
|
||||
|
||||
ph1_ld4_early_clk_init(bd);
|
||||
|
||||
led_puts("L2");
|
||||
|
||||
ph1_sld3_early_pin_init(bd);
|
||||
|
||||
led_puts("L3");
|
||||
|
||||
#ifdef CONFIG_SPL_SERIAL_SUPPORT
|
||||
preloader_console_init();
|
||||
#endif
|
||||
|
||||
led_puts("L4");
|
||||
|
||||
led_puts("L5");
|
||||
|
||||
ph1_sld3_enable_dpll_ssc(bd);
|
||||
|
||||
led_puts("L6");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
/*
|
||||
* Copyright (C) 2013-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <spl.h>
|
||||
#include <linux/compiler.h>
|
||||
#include <mach/init.h>
|
||||
#include <mach/micro-support-card.h>
|
||||
|
||||
int ph1_sld8_init(const struct uniphier_board_data *bd)
|
||||
{
|
||||
ph1_ld4_bcu_init(bd);
|
||||
|
||||
ph1_ld4_sbc_init(bd);
|
||||
|
||||
support_card_reset();
|
||||
|
||||
ph1_sld8_pll_init(bd);
|
||||
|
||||
support_card_init();
|
||||
|
||||
led_puts("L0");
|
||||
|
||||
memconf_init(bd);
|
||||
|
||||
led_puts("L1");
|
||||
|
||||
ph1_ld4_early_clk_init(bd);
|
||||
|
||||
led_puts("L2");
|
||||
|
||||
led_puts("L3");
|
||||
|
||||
#ifdef CONFIG_SPL_SERIAL_SUPPORT
|
||||
preloader_console_init();
|
||||
#endif
|
||||
|
||||
led_puts("L4");
|
||||
|
||||
{
|
||||
int res;
|
||||
|
||||
res = ph1_sld8_umc_init(bd);
|
||||
if (res < 0) {
|
||||
while (1)
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
led_puts("L5");
|
||||
|
||||
ph1_ld4_enable_dpll_ssc(bd);
|
||||
|
||||
led_puts("L6");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <spl.h>
|
||||
#include <mach/init.h>
|
||||
#include <mach/soc_info.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
void spl_board_init(void)
|
||||
{
|
||||
const struct uniphier_board_data *param;
|
||||
|
||||
param = uniphier_get_board_param(gd->fdt_blob);
|
||||
if (!param)
|
||||
hang();
|
||||
|
||||
switch (uniphier_get_soc_type()) {
|
||||
#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
|
||||
case SOC_UNIPHIER_PH1_SLD3:
|
||||
ph1_sld3_init(param);
|
||||
break;
|
||||
#endif
|
||||
#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
|
||||
case SOC_UNIPHIER_PH1_LD4:
|
||||
ph1_ld4_init(param);
|
||||
break;
|
||||
#endif
|
||||
#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
|
||||
case SOC_UNIPHIER_PH1_PRO4:
|
||||
ph1_pro4_init(param);
|
||||
break;
|
||||
#endif
|
||||
#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
|
||||
case SOC_UNIPHIER_PH1_SLD8:
|
||||
ph1_sld8_init(param);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
@ -1,103 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <linux/io.h>
|
||||
#include <mach/sg-regs.h>
|
||||
|
||||
static inline u32 sg_memconf_val_ch0(unsigned long size, int num)
|
||||
{
|
||||
int size_mb = size / num;
|
||||
u32 ret;
|
||||
|
||||
switch (size_mb) {
|
||||
case SZ_64M:
|
||||
ret = SG_MEMCONF_CH0_SZ_64M;
|
||||
break;
|
||||
case SZ_128M:
|
||||
ret = SG_MEMCONF_CH0_SZ_128M;
|
||||
break;
|
||||
case SZ_256M:
|
||||
ret = SG_MEMCONF_CH0_SZ_256M;
|
||||
break;
|
||||
case SZ_512M:
|
||||
ret = SG_MEMCONF_CH0_SZ_512M;
|
||||
break;
|
||||
case SZ_1G:
|
||||
ret = SG_MEMCONF_CH0_SZ_1G;
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
break;
|
||||
}
|
||||
|
||||
switch (num) {
|
||||
case 1:
|
||||
ret |= SG_MEMCONF_CH0_NUM_1;
|
||||
break;
|
||||
case 2:
|
||||
ret |= SG_MEMCONF_CH0_NUM_2;
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
break;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline u32 sg_memconf_val_ch1(unsigned long size, int num)
|
||||
{
|
||||
int size_mb = size / num;
|
||||
u32 ret;
|
||||
|
||||
switch (size_mb) {
|
||||
case SZ_64M:
|
||||
ret = SG_MEMCONF_CH1_SZ_64M;
|
||||
break;
|
||||
case SZ_128M:
|
||||
ret = SG_MEMCONF_CH1_SZ_128M;
|
||||
break;
|
||||
case SZ_256M:
|
||||
ret = SG_MEMCONF_CH1_SZ_256M;
|
||||
break;
|
||||
case SZ_512M:
|
||||
ret = SG_MEMCONF_CH1_SZ_512M;
|
||||
break;
|
||||
case SZ_1G:
|
||||
ret = SG_MEMCONF_CH1_SZ_1G;
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
break;
|
||||
}
|
||||
|
||||
switch (num) {
|
||||
case 1:
|
||||
ret |= SG_MEMCONF_CH1_NUM_1;
|
||||
break;
|
||||
case 2:
|
||||
ret |= SG_MEMCONF_CH1_NUM_2;
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
break;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
void memconf_init(void)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
/* Set DDR size */
|
||||
tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0);
|
||||
tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1);
|
||||
#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE
|
||||
tmp |= SG_MEMCONF_SPARSEMEM;
|
||||
#endif
|
||||
writel(tmp, SG_MEMCONF);
|
||||
}
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
obj-y += memconf.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += memconf-ph1-sld3.o
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <mach/init.h>
|
||||
#include <mach/sg-regs.h>
|
||||
|
||||
int ph1_sld3_memconf_init(const struct uniphier_board_data *bd)
|
||||
{
|
||||
u32 tmp;
|
||||
unsigned long size_per_word;
|
||||
|
||||
tmp = readl(SG_MEMCONF);
|
||||
|
||||
tmp &= ~(SG_MEMCONF_CH2_SZ_MASK | SG_MEMCONF_CH2_NUM_MASK);
|
||||
|
||||
switch (bd->dram_ch2_width) {
|
||||
case 16:
|
||||
tmp |= SG_MEMCONF_CH2_NUM_1;
|
||||
size_per_word = bd->dram_ch2_size;
|
||||
break;
|
||||
case 32:
|
||||
tmp |= SG_MEMCONF_CH2_NUM_2;
|
||||
size_per_word = bd->dram_ch2_size >> 1;
|
||||
break;
|
||||
default:
|
||||
pr_err("error: unsupported DRAM Ch2 width\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Set DDR size */
|
||||
switch (size_per_word) {
|
||||
case SZ_64M:
|
||||
tmp |= SG_MEMCONF_CH2_SZ_64M;
|
||||
break;
|
||||
case SZ_128M:
|
||||
tmp |= SG_MEMCONF_CH2_SZ_128M;
|
||||
break;
|
||||
case SZ_256M:
|
||||
tmp |= SG_MEMCONF_CH2_SZ_256M;
|
||||
break;
|
||||
case SZ_512M:
|
||||
tmp |= SG_MEMCONF_CH2_SZ_512M;
|
||||
break;
|
||||
default:
|
||||
pr_err("error: unsupported DRAM Ch2 size\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
writel(tmp, SG_MEMCONF);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
/*
|
||||
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <mach/init.h>
|
||||
#include <mach/sg-regs.h>
|
||||
|
||||
int memconf_init(const struct uniphier_board_data *bd)
|
||||
{
|
||||
u32 tmp = 0;
|
||||
unsigned long size_per_word;
|
||||
|
||||
tmp = readl(SG_MEMCONF);
|
||||
|
||||
tmp &= ~(SG_MEMCONF_CH0_SZ_MASK | SG_MEMCONF_CH0_NUM_MASK);
|
||||
|
||||
switch (bd->dram_ch0_width) {
|
||||
case 16:
|
||||
tmp |= SG_MEMCONF_CH0_NUM_1;
|
||||
size_per_word = bd->dram_ch0_size;
|
||||
break;
|
||||
case 32:
|
||||
tmp |= SG_MEMCONF_CH0_NUM_2;
|
||||
size_per_word = bd->dram_ch0_size >> 1;
|
||||
break;
|
||||
default:
|
||||
pr_err("error: unsupported DRAM Ch0 width\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Set DDR size */
|
||||
switch (size_per_word) {
|
||||
case SZ_64M:
|
||||
tmp |= SG_MEMCONF_CH0_SZ_64M;
|
||||
break;
|
||||
case SZ_128M:
|
||||
tmp |= SG_MEMCONF_CH0_SZ_128M;
|
||||
break;
|
||||
case SZ_256M:
|
||||
tmp |= SG_MEMCONF_CH0_SZ_256M;
|
||||
break;
|
||||
case SZ_512M:
|
||||
tmp |= SG_MEMCONF_CH0_SZ_512M;
|
||||
break;
|
||||
case SZ_1G:
|
||||
tmp |= SG_MEMCONF_CH0_SZ_1G;
|
||||
break;
|
||||
default:
|
||||
pr_err("error: unsupported DRAM Ch0 size\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
tmp &= ~(SG_MEMCONF_CH1_SZ_MASK | SG_MEMCONF_CH1_NUM_MASK);
|
||||
|
||||
switch (bd->dram_ch1_width) {
|
||||
case 16:
|
||||
tmp |= SG_MEMCONF_CH1_NUM_1;
|
||||
size_per_word = bd->dram_ch1_size;
|
||||
break;
|
||||
case 32:
|
||||
tmp |= SG_MEMCONF_CH1_NUM_2;
|
||||
size_per_word = bd->dram_ch1_size >> 1;
|
||||
break;
|
||||
default:
|
||||
pr_err("error: unsupported DRAM Ch1 width\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
switch (size_per_word) {
|
||||
case SZ_64M:
|
||||
tmp |= SG_MEMCONF_CH1_SZ_64M;
|
||||
break;
|
||||
case SZ_128M:
|
||||
tmp |= SG_MEMCONF_CH1_SZ_128M;
|
||||
break;
|
||||
case SZ_256M:
|
||||
tmp |= SG_MEMCONF_CH1_SZ_256M;
|
||||
break;
|
||||
case SZ_512M:
|
||||
tmp |= SG_MEMCONF_CH1_SZ_512M;
|
||||
break;
|
||||
case SZ_1G:
|
||||
tmp |= SG_MEMCONF_CH1_SZ_1G;
|
||||
break;
|
||||
default:
|
||||
pr_err("error: unsupported DRAM Ch1 size\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (bd->dram_ch0_base + bd->dram_ch0_size < bd->dram_ch1_base)
|
||||
tmp |= SG_MEMCONF_SPARSEMEM;
|
||||
else
|
||||
tmp &= ~SG_MEMCONF_SPARSEMEM;
|
||||
|
||||
writel(tmp, SG_MEMCONF);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
obj-y += bcu_init.o pll_init.o early_clkrst_init.o \
|
||||
pll_spectrum.o umc_init.o ddrphy_init.o
|
||||
obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc_init.o
|
||||
else
|
||||
obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
|
||||
endif
|
||||
|
||||
obj-y += boot-mode.o
|
||||
|
|
@ -1 +0,0 @@
|
|||
#include "../ph1-pro4/boot-mode.c"
|
||||
|
|
@ -1 +0,0 @@
|
|||
#include "../ph1-pro4/early_clkrst_init.c"
|
||||
|
|
@ -1 +0,0 @@
|
|||
#include "../ph1-pro4/pll_spectrum.c"
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
obj-y += pll_init.o early_clkrst_init.o \
|
||||
pll_spectrum.o umc_init.o ddrphy_init.o
|
||||
obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc_init.o
|
||||
else
|
||||
obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
|
||||
endif
|
||||
|
||||
obj-y += boot-mode.o
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
obj-y += bcu_init.o memconf.o sg_init.o pll_init.o early_clkrst_init.o \
|
||||
early_pinctrl.o pll_spectrum.o umc_init.o
|
||||
obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc_init.o
|
||||
else
|
||||
obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
|
||||
endif
|
||||
|
||||
obj-y += boot-mode.o
|
||||
|
|
@ -1 +0,0 @@
|
|||
#include "../ph1-pro4/clkrst_init.c"
|
||||
|
|
@ -1 +0,0 @@
|
|||
#include "../ph1-pro4/early_clkrst_init.c"
|
||||
|
|
@ -1,52 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <mach/sg-regs.h>
|
||||
|
||||
static inline u32 sg_memconf_val_ch2(unsigned long size, int num)
|
||||
{
|
||||
int size_mb = size / num;
|
||||
u32 ret;
|
||||
|
||||
switch (size_mb) {
|
||||
case SZ_64M:
|
||||
ret = SG_MEMCONF_CH2_SZ_64M;
|
||||
break;
|
||||
case SZ_128M:
|
||||
ret = SG_MEMCONF_CH2_SZ_128M;
|
||||
break;
|
||||
case SZ_256M:
|
||||
ret = SG_MEMCONF_CH2_SZ_256M;
|
||||
break;
|
||||
case SZ_512M:
|
||||
ret = SG_MEMCONF_CH2_SZ_512M;
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
break;
|
||||
}
|
||||
|
||||
switch (num) {
|
||||
case 1:
|
||||
ret |= SG_MEMCONF_CH2_NUM_1;
|
||||
break;
|
||||
case 2:
|
||||
ret |= SG_MEMCONF_CH2_NUM_2;
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
break;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
u32 memconf_additional_val(void)
|
||||
{
|
||||
return sg_memconf_val_ch2(CONFIG_SDRAM2_SIZE, CONFIG_DDR_NUM_CH2);
|
||||
}
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
void sg_init(void)
|
||||
{
|
||||
}
|
||||
|
|
@ -1,15 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
int umc_init(void)
|
||||
{
|
||||
/* add UMC init code here */
|
||||
printf("Implement memory init code\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1 +0,0 @@
|
|||
include $(src)/../ph1-ld4/Makefile
|
||||
|
|
@ -1 +0,0 @@
|
|||
#include "../ph1-ld4/bcu_init.c"
|
||||
|
|
@ -1 +0,0 @@
|
|||
#include "../ph1-pro4/boot-mode.c"
|
||||
|
|
@ -1 +0,0 @@
|
|||
#include "../ph1-ld4/clkrst_init.c"
|
||||
|
|
@ -1 +0,0 @@
|
|||
#include "../ph1-ld4/early_clkrst_init.c"
|
||||
|
|
@ -1 +0,0 @@
|
|||
#include "../ph1-ld4/pll_spectrum.c"
|
||||
|
|
@ -1 +0,0 @@
|
|||
#include "../ph1-ld4/sbc_init.c"
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += pinctrl-ph1-sld3.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += pinctrl-ph1-pro4.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += pinctrl-ph1-sld8.o
|
||||
|
|
@ -5,9 +5,10 @@
|
|||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <mach/init.h>
|
||||
#include <mach/sg-regs.h>
|
||||
|
||||
void pin_init(void)
|
||||
void ph1_ld4_pin_init(void)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
|
|
@ -5,9 +5,10 @@
|
|||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <mach/init.h>
|
||||
#include <mach/sg-regs.h>
|
||||
|
||||
void pin_init(void)
|
||||
void ph1_pro4_pin_init(void)
|
||||
{
|
||||
/* Comment format: PAD Name -> Function Name */
|
||||
|
||||
|
|
@ -4,9 +4,10 @@
|
|||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <mach/init.h>
|
||||
#include <mach/sg-regs.h>
|
||||
|
||||
void pin_init(void)
|
||||
void ph1_sld3_pin_init(void)
|
||||
{
|
||||
#ifdef CONFIG_USB_EHCI_UNIPHIER
|
||||
sg_set_pinsel(13, 0, 4, 4); /* USB0OC */
|
||||
|
|
@ -5,9 +5,10 @@
|
|||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <mach/init.h>
|
||||
#include <mach/sg-regs.h>
|
||||
|
||||
void pin_init(void)
|
||||
void ph1_sld8_pin_init(void)
|
||||
{
|
||||
/* Comment format: PAD Name -> Function Name */
|
||||
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += pll-init-ph1-sld3.o \
|
||||
pll-spectrum-ph1-sld3.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += pll-init-ph1-ld4.o \
|
||||
pll-spectrum-ph1-ld4.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += pll-init-ph1-pro4.o \
|
||||
pll-spectrum-ph1-ld4.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += pll-init-ph1-sld8.o \
|
||||
pll-spectrum-ph1-ld4.o
|
||||
|
|
@ -5,13 +5,15 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <mach/init.h>
|
||||
#include <mach/sc-regs.h>
|
||||
#include <mach/sg-regs.h>
|
||||
|
||||
#undef DPLL_SSC_RATE_1PER
|
||||
|
||||
static void dpll_init(void)
|
||||
static int dpll_init(unsigned int dram_freq)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
|
|
@ -22,13 +24,17 @@ static void dpll_init(void)
|
|||
*/
|
||||
tmp = readl(SC_DPLLCTRL);
|
||||
tmp &= ~0x000f0000;
|
||||
#if CONFIG_DDR_FREQ == 1600
|
||||
tmp |= 0x000c0000;
|
||||
#elif CONFIG_DDR_FREQ == 1333
|
||||
tmp |= 0x000d0000;
|
||||
#else
|
||||
# error "Unknown frequency"
|
||||
#endif
|
||||
switch (dram_freq) {
|
||||
case 1333:
|
||||
tmp |= 0x000d0000;
|
||||
break;
|
||||
case 1600:
|
||||
tmp |= 0x000c0000;
|
||||
break;
|
||||
default:
|
||||
pr_err("Unsupported frequency");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
#if defined(DPLL_SSC_RATE_1PER)
|
||||
tmp &= ~SC_DPLLCTRL_SSC_RATE;
|
||||
|
|
@ -40,6 +46,8 @@ static void dpll_init(void)
|
|||
tmp = readl(SC_DPLLCTRL2);
|
||||
tmp |= SC_DPLLCTRL2_NRSTDS;
|
||||
writel(tmp, SC_DPLLCTRL2);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void upll_init(void)
|
||||
|
|
@ -174,9 +182,13 @@ static void vpll_init(void)
|
|||
writel(tmp, SC_VPLL27BCTRL);
|
||||
}
|
||||
|
||||
void pll_init(void)
|
||||
int ph1_ld4_pll_init(const struct uniphier_board_data *bd)
|
||||
{
|
||||
dpll_init();
|
||||
int ret;
|
||||
|
||||
ret = dpll_init(bd->dram_freq);
|
||||
if (ret)
|
||||
return ret;
|
||||
upll_init();
|
||||
vpll_init();
|
||||
|
||||
|
|
@ -186,4 +198,6 @@ void pll_init(void)
|
|||
* so 20 usec can be saved here.
|
||||
*/
|
||||
udelay(480);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -5,13 +5,15 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <mach/init.h>
|
||||
#include <mach/sc-regs.h>
|
||||
#include <mach/sg-regs.h>
|
||||
|
||||
#undef DPLL_SSC_RATE_1PER
|
||||
|
||||
static void dpll_init(void)
|
||||
static int dpll_init(unsigned int dram_freq)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
|
|
@ -22,13 +24,17 @@ static void dpll_init(void)
|
|||
*/
|
||||
tmp = readl(SC_DPLLCTRL);
|
||||
tmp &= ~(0x000f0000);
|
||||
#if CONFIG_DDR_FREQ == 1600
|
||||
tmp |= 0x000c0000;
|
||||
#elif CONFIG_DDR_FREQ == 1333
|
||||
tmp |= 0x000d0000;
|
||||
#else
|
||||
# error "Unsupported frequency"
|
||||
#endif
|
||||
switch (dram_freq) {
|
||||
case 1333:
|
||||
tmp |= 0x000d0000;
|
||||
break;
|
||||
case 1600:
|
||||
tmp |= 0x000c0000;
|
||||
break;
|
||||
default:
|
||||
pr_err("Unsupported frequency");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set Moduration rate
|
||||
|
|
@ -44,6 +50,8 @@ static void dpll_init(void)
|
|||
tmp = readl(SC_DPLLCTRL2);
|
||||
tmp |= SC_DPLLCTRL2_NRSTDS;
|
||||
writel(tmp, SC_DPLLCTRL2);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void vpll_init(void)
|
||||
|
|
@ -136,9 +144,13 @@ static void vpll_init(void)
|
|||
writel(tmp, SC_VPLL27BCTRL);
|
||||
}
|
||||
|
||||
void pll_init(void)
|
||||
int ph1_pro4_pll_init(const struct uniphier_board_data *bd)
|
||||
{
|
||||
dpll_init();
|
||||
int ret;
|
||||
|
||||
ret = dpll_init(bd->dram_freq);
|
||||
if (ret)
|
||||
return ret;
|
||||
vpll_init();
|
||||
|
||||
/*
|
||||
|
|
@ -146,4 +158,6 @@ void pll_init(void)
|
|||
* We wait 1 usec in vpll_init() so 1 usec can be saved here.
|
||||
*/
|
||||
udelay(499);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -4,7 +4,10 @@
|
|||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
void pll_init(void)
|
||||
#include <mach/init.h>
|
||||
|
||||
int ph1_sld3_pll_init(const struct uniphier_board_data *bd)
|
||||
{
|
||||
/* add pll init code here */
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -6,6 +6,7 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <linux/io.h>
|
||||
#include <mach/init.h>
|
||||
#include <mach/sc-regs.h>
|
||||
#include <mach/sg-regs.h>
|
||||
|
||||
|
|
@ -186,7 +187,7 @@ static void vpll_init(void)
|
|||
writel(tmp, SC_VPLL27BCTRL);
|
||||
}
|
||||
|
||||
void pll_init(void)
|
||||
int ph1_sld8_pll_init(const struct uniphier_board_data *bd)
|
||||
{
|
||||
dpll_init();
|
||||
upll_init();
|
||||
|
|
@ -198,4 +199,6 @@ void pll_init(void)
|
|||
* so 20 usec can be saved here.
|
||||
*/
|
||||
udelay(480);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -4,15 +4,17 @@
|
|||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <linux/io.h>
|
||||
#include <mach/init.h>
|
||||
#include <mach/sc-regs.h>
|
||||
|
||||
void enable_dpll_ssc(void)
|
||||
int ph1_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
tmp = readl(SC_DPLLCTRL);
|
||||
tmp |= SC_DPLLCTRL_SSC_EN;
|
||||
writel(tmp, SC_DPLLCTRL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -6,13 +6,16 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <linux/io.h>
|
||||
#include <mach/init.h>
|
||||
#include <mach/sc-regs.h>
|
||||
|
||||
void enable_dpll_ssc(void)
|
||||
int ph1_sld3_enable_dpll_ssc(const struct uniphier_board_data *bd)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
tmp = readl(SC_DPLLCTRL);
|
||||
tmp |= SC_DPLLCTRL_SSC_EN;
|
||||
writel(tmp, SC_DPLLCTRL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += sbc-ph1-sld3.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += sbc-ph1-ld4.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += sbc-ph1-pro4.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += sbc-ph1-ld4.o
|
||||
|
|
@ -6,10 +6,11 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <linux/io.h>
|
||||
#include <mach/init.h>
|
||||
#include <mach/sbc-regs.h>
|
||||
#include <mach/sg-regs.h>
|
||||
|
||||
void sbc_init(void)
|
||||
int ph1_ld4_sbc_init(const struct uniphier_board_data *bd)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
|
|
@ -46,4 +47,6 @@ void sbc_init(void)
|
|||
writel(0x0000be01, SBBASE0); /* dummy */
|
||||
writel(0x0200be01, SBBASE1);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -6,10 +6,11 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <linux/io.h>
|
||||
#include <mach/init.h>
|
||||
#include <mach/sbc-regs.h>
|
||||
#include <mach/sg-regs.h>
|
||||
|
||||
void sbc_init(void)
|
||||
int ph1_pro4_sbc_init(const struct uniphier_board_data *bd)
|
||||
{
|
||||
/*
|
||||
* Only CS1 is connected to support card.
|
||||
|
|
@ -39,4 +40,6 @@ void sbc_init(void)
|
|||
writel(0x0000be01, SBBASE0); /* dummy */
|
||||
writel(0x0200be01, SBBASE1);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -6,10 +6,11 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <linux/io.h>
|
||||
#include <mach/init.h>
|
||||
#include <mach/sbc-regs.h>
|
||||
#include <mach/sg-regs.h>
|
||||
|
||||
void sbc_init(void)
|
||||
int ph1_sld3_sbc_init(const struct uniphier_board_data *bd)
|
||||
{
|
||||
/* only address/data multiplex mode is supported */
|
||||
|
||||
|
|
@ -42,4 +43,6 @@ void sbc_init(void)
|
|||
}
|
||||
|
||||
sg_set_pinsel(99, 1, 4, 4); /* GPIO26 -> EA24 */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/types.h>
|
||||
#include <mach/sg-regs.h>
|
||||
#include <mach/soc_info.h>
|
||||
|
||||
#if UNIPHIER_MULTI_SOC
|
||||
enum uniphier_soc_id uniphier_get_soc_type(void)
|
||||
{
|
||||
u32 revision = readl(SG_REVISION);
|
||||
enum uniphier_soc_id ret;
|
||||
|
||||
switch ((revision & SG_REVISION_TYPE_MASK) >> SG_REVISION_TYPE_SHIFT) {
|
||||
#ifdef CONFIG_ARCH_UNIPHIER_PH1_SLD3
|
||||
case 0x25:
|
||||
ret = SOC_UNIPHIER_PH1_SLD3;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_UNIPHIER_PH1_LD4
|
||||
case 0x26:
|
||||
ret = SOC_UNIPHIER_PH1_LD4;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_UNIPHIER_PH1_PRO4
|
||||
case 0x28:
|
||||
ret = SOC_UNIPHIER_PH1_PRO4;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_UNIPHIER_PH1_SLD8
|
||||
case 0x29:
|
||||
ret = SOC_UNIPHIER_PH1_SLD8;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_UNIPHIER_PH1_PRO5
|
||||
case 0x2A:
|
||||
ret = SOC_UNIPHIER_PH1_PRO5;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_UNIPHIER_PROXSTREAM2
|
||||
case 0x2E:
|
||||
ret = SOC_UNIPHIER_PROXSTREAM2;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_UNIPHIER_PH1_LD6B
|
||||
case 0x2F:
|
||||
ret = SOC_UNIPHIER_PH1_LD6B;
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
ret = SOC_UNIPHIER_UNKNOWN;
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += umc-ph1-ld4.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += umc-ph1-pro4.o
|
||||
obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += umc-ph1-sld8.o
|
||||
|
|
@ -5,7 +5,10 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <mach/init.h>
|
||||
#include <mach/umc-regs.h>
|
||||
#include <mach/ddrphy-regs.h>
|
||||
|
||||
|
|
@ -136,14 +139,14 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1)
|
|||
|
||||
writel(0x00000101, dramcont0 + UMC_DIOCTLA);
|
||||
|
||||
ddrphy_init(phy0_0, freq, size_ch0);
|
||||
ph1_ld4_ddrphy_init(phy0_0, freq, size_ch0);
|
||||
|
||||
ddrphy_prepare_training(phy0_0, 0);
|
||||
ddrphy_training(phy0_0);
|
||||
|
||||
writel(0x00000101, dramcont1 + UMC_DIOCTLA);
|
||||
|
||||
ddrphy_init(phy1_0, freq, size_ch1);
|
||||
ph1_ld4_ddrphy_init(phy1_0, freq, size_ch1);
|
||||
|
||||
ddrphy_prepare_training(phy1_0, 1);
|
||||
ddrphy_training(phy1_0);
|
||||
|
|
@ -156,16 +159,17 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int umc_init(void)
|
||||
int ph1_ld4_umc_init(const struct uniphier_board_data *bd)
|
||||
{
|
||||
return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000,
|
||||
CONFIG_SDRAM1_SIZE / 0x08000000);
|
||||
if ((bd->dram_ch0_size == SZ_128M || bd->dram_ch0_size == SZ_256M) &&
|
||||
(bd->dram_ch1_size == SZ_128M || bd->dram_ch1_size == SZ_256M) &&
|
||||
(bd->dram_freq == 1333 || bd->dram_freq == 1600) &&
|
||||
bd->dram_ch0_width == 16 && bd->dram_ch1_width == 16) {
|
||||
return umc_init_sub(bd->dram_freq,
|
||||
bd->dram_ch0_size / SZ_128M,
|
||||
bd->dram_ch1_size / SZ_128M);
|
||||
} else {
|
||||
pr_err("Unsupported DDR configuration\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \
|
||||
(CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \
|
||||
CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1
|
||||
/* OK */
|
||||
#else
|
||||
#error Unsupported DDR configuration.
|
||||
#endif
|
||||
|
|
@ -5,7 +5,10 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <mach/init.h>
|
||||
#include <mach/umc-regs.h>
|
||||
#include <mach/ddrphy-regs.h>
|
||||
|
||||
|
|
@ -107,28 +110,28 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1)
|
|||
|
||||
writel(0x00000101, dramcont0 + UMC_DIOCTLA);
|
||||
|
||||
ddrphy_init(phy0_0, freq, size_ch0);
|
||||
ph1_pro4_ddrphy_init(phy0_0, freq, size_ch0);
|
||||
|
||||
ddrphy_prepare_training(phy0_0, 0);
|
||||
ddrphy_training(phy0_0);
|
||||
|
||||
writel(0x00000103, dramcont0 + UMC_DIOCTLA);
|
||||
|
||||
ddrphy_init(phy0_1, freq, size_ch0);
|
||||
ph1_pro4_ddrphy_init(phy0_1, freq, size_ch0);
|
||||
|
||||
ddrphy_prepare_training(phy0_1, 1);
|
||||
ddrphy_training(phy0_1);
|
||||
|
||||
writel(0x00000101, dramcont1 + UMC_DIOCTLA);
|
||||
|
||||
ddrphy_init(phy1_0, freq, size_ch1);
|
||||
ph1_pro4_ddrphy_init(phy1_0, freq, size_ch1);
|
||||
|
||||
ddrphy_prepare_training(phy1_0, 0);
|
||||
ddrphy_training(phy1_0);
|
||||
|
||||
writel(0x00000103, dramcont1 + UMC_DIOCTLA);
|
||||
|
||||
ddrphy_init(phy1_1, freq, size_ch1);
|
||||
ph1_pro4_ddrphy_init(phy1_1, freq, size_ch1);
|
||||
|
||||
ddrphy_prepare_training(phy1_1, 1);
|
||||
ddrphy_training(phy1_1);
|
||||
|
|
@ -141,17 +144,18 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int umc_init(void)
|
||||
int ph1_pro4_umc_init(const struct uniphier_board_data *bd)
|
||||
{
|
||||
return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000,
|
||||
CONFIG_SDRAM1_SIZE / 0x08000000);
|
||||
if (((bd->dram_ch0_size == SZ_512M && bd->dram_ch0_width == 32) ||
|
||||
(bd->dram_ch0_size == SZ_256M && bd->dram_ch0_width == 16)) &&
|
||||
((bd->dram_ch1_size == SZ_512M && bd->dram_ch1_width == 32) ||
|
||||
(bd->dram_ch1_size == SZ_256M && bd->dram_ch1_width == 16)) &&
|
||||
bd->dram_freq == 1600) {
|
||||
return umc_init_sub(bd->dram_freq,
|
||||
bd->dram_ch0_size / SZ_128M,
|
||||
bd->dram_ch1_size / SZ_128M);
|
||||
} else {
|
||||
pr_err("Unsupported DDR configuration\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
#if ((CONFIG_SDRAM0_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH0 == 2) || \
|
||||
(CONFIG_SDRAM0_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH0 == 1)) && \
|
||||
((CONFIG_SDRAM1_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH1 == 2) || \
|
||||
(CONFIG_SDRAM1_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH1 == 1))
|
||||
/* OK */
|
||||
#else
|
||||
#error Unsupported DDR configuration.
|
||||
#endif
|
||||
|
|
@ -5,7 +5,10 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <mach/init.h>
|
||||
#include <mach/umc-regs.h>
|
||||
#include <mach/ddrphy-regs.h>
|
||||
|
||||
|
|
@ -116,14 +119,14 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1)
|
|||
|
||||
writel(0x00000101, dramcont0 + UMC_DIOCTLA);
|
||||
|
||||
ddrphy_init(phy0_0, freq, size_ch0);
|
||||
ph1_sld8_ddrphy_init(phy0_0, freq, size_ch0);
|
||||
|
||||
ddrphy_prepare_training(phy0_0, 0);
|
||||
ddrphy_training(phy0_0);
|
||||
|
||||
writel(0x00000101, dramcont1 + UMC_DIOCTLA);
|
||||
|
||||
ddrphy_init(phy1_0, freq, size_ch1);
|
||||
ph1_sld8_ddrphy_init(phy1_0, freq, size_ch1);
|
||||
|
||||
ddrphy_prepare_training(phy1_0, 1);
|
||||
ddrphy_training(phy1_0);
|
||||
|
|
@ -136,16 +139,17 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int umc_init(void)
|
||||
int ph1_sld8_umc_init(const struct uniphier_board_data *bd)
|
||||
{
|
||||
return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000,
|
||||
CONFIG_SDRAM1_SIZE / 0x08000000);
|
||||
if ((bd->dram_ch0_size == SZ_128M || bd->dram_ch0_size == SZ_256M) &&
|
||||
(bd->dram_ch1_size == SZ_128M || bd->dram_ch1_size == SZ_256M) &&
|
||||
bd->dram_freq == 1333 &&
|
||||
bd->dram_ch0_width == 16 && bd->dram_ch1_width == 16) {
|
||||
return umc_init_sub(bd->dram_freq,
|
||||
bd->dram_ch0_size / SZ_128M,
|
||||
bd->dram_ch1_size / SZ_128M);
|
||||
} else {
|
||||
pr_err("Unsupported DDR configuration\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \
|
||||
(CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \
|
||||
CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1
|
||||
/* OK */
|
||||
#else
|
||||
#error Unsupported DDR configuration.
|
||||
#endif
|
||||
|
|
@ -1,6 +1,7 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_UNIPHIER=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_ARCH_UNIPHIER_PH1_PRO4=y
|
||||
CONFIG_MICRO_SUPPORT_CARD=y
|
||||
CONFIG_SYS_TEXT_BASE=0x84000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref"
|
||||
|
|
|
|||
|
|
@ -9,53 +9,6 @@
|
|||
#ifndef __CONFIG_UNIPHIER_COMMON_H__
|
||||
#define __CONFIG_UNIPHIER_COMMON_H__
|
||||
|
||||
#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
|
||||
#define CONFIG_DDR_NUM_CH0 2
|
||||
#define CONFIG_DDR_NUM_CH1 1
|
||||
#define CONFIG_DDR_NUM_CH2 1
|
||||
|
||||
/* Physical start address of SDRAM */
|
||||
#define CONFIG_SDRAM0_BASE 0x80000000
|
||||
#define CONFIG_SDRAM0_SIZE 0x20000000
|
||||
#define CONFIG_SDRAM1_BASE 0xc0000000
|
||||
#define CONFIG_SDRAM1_SIZE 0x20000000
|
||||
#define CONFIG_SDRAM2_BASE 0xc0000000
|
||||
#define CONFIG_SDRAM2_SIZE 0x10000000
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
|
||||
#define CONFIG_DDR_NUM_CH0 1
|
||||
#define CONFIG_DDR_NUM_CH1 1
|
||||
|
||||
/* Physical start address of SDRAM */
|
||||
#define CONFIG_SDRAM0_BASE 0x80000000
|
||||
#define CONFIG_SDRAM0_SIZE 0x10000000
|
||||
#define CONFIG_SDRAM1_BASE 0x90000000
|
||||
#define CONFIG_SDRAM1_SIZE 0x10000000
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
|
||||
#define CONFIG_DDR_NUM_CH0 2
|
||||
#define CONFIG_DDR_NUM_CH1 2
|
||||
|
||||
/* Physical start address of SDRAM */
|
||||
#define CONFIG_SDRAM0_BASE 0x80000000
|
||||
#define CONFIG_SDRAM0_SIZE 0x20000000
|
||||
#define CONFIG_SDRAM1_BASE 0xa0000000
|
||||
#define CONFIG_SDRAM1_SIZE 0x20000000
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
|
||||
#define CONFIG_DDR_NUM_CH0 1
|
||||
#define CONFIG_DDR_NUM_CH1 1
|
||||
|
||||
/* Physical start address of SDRAM */
|
||||
#define CONFIG_SDRAM0_BASE 0x80000000
|
||||
#define CONFIG_SDRAM0_SIZE 0x10000000
|
||||
#define CONFIG_SDRAM1_BASE 0x90000000
|
||||
#define CONFIG_SDRAM1_SIZE 0x10000000
|
||||
#endif
|
||||
|
||||
#define CONFIG_I2C_EEPROM
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
|
||||
|
||||
|
|
@ -285,8 +238,7 @@
|
|||
defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \
|
||||
defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
|
||||
#define CONFIG_SPL_TEXT_BASE 0x00040000
|
||||
#endif
|
||||
#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
|
||||
#else
|
||||
#define CONFIG_SPL_TEXT_BASE 0x00100000
|
||||
#endif
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue