Adjust for mmc changes
Martin T. H. Sandsmark
Martin T. H. Sandsmark
parent
060ded3a14
commit
3588b75eb3
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@ -44,9 +44,6 @@ DECLARE_GLOBAL_DATA_PTR;
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
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#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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@ -72,17 +69,13 @@ static iomux_v3_cfg_t const uart1_pads[] = {
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};
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static iomux_v3_cfg_t const usdhc1_pads[] = {
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/* 8 bit SD */
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/* 4 bit SD */
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MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DAT4__USDHC1_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DAT5__USDHC1_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DAT6__USDHC1_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DAT7__USDHC1_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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/*CD pin*/
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MX6_PAD_KEY_ROW7__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
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@ -95,6 +88,10 @@ static iomux_v3_cfg_t const usdhc2_pads[] = {
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MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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/*CD pin*/
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MX6_PAD_SD2_DAT7__GPIO_5_0 | MUX_PAD_CTRL(NO_PAD_CTRL),
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@ -126,25 +123,6 @@ static iomux_v3_cfg_t const fec_pads[] = {
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MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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#ifdef CONFIG_MXC_SPI
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static iomux_v3_cfg_t ecspi1_pads[] = {
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MX6_PAD_ECSPI1_MISO__ECSPI_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
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MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
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MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
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MX6_PAD_ECSPI1_SS0__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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int board_spi_cs_gpio(unsigned bus, unsigned cs)
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{
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return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 11)) : -1;
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}
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static void setup_spi(void)
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{
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imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
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}
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#endif
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static void setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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@ -160,12 +138,12 @@ static void setup_iomux_fec(void)
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}
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#define USDHC1_CD_GPIO IMX_GPIO_NR(4, 7)
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#define USDHC2_CD_GPIO IMX_GPIO_NR(5, 0)
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#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 22)
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/*#define USDHC2_CD_GPIO IMX_GPIO_NR(5, 0)*/
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/*#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 22)*/
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static struct fsl_esdhc_cfg usdhc_cfg[3] = {
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{USDHC1_BASE_ADDR},
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{USDHC2_BASE_ADDR, 0, 4},
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{USDHC1_BASE_ADDR, 0, 4},
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{USDHC2_BASE_ADDR, 0, 8},
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{USDHC3_BASE_ADDR, 0, 4},
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};
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@ -184,10 +162,12 @@ int board_mmc_getcd(struct mmc *mmc)
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ret = !gpio_get_value(USDHC1_CD_GPIO);
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break;
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case USDHC2_BASE_ADDR:
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ret = !gpio_get_value(USDHC2_CD_GPIO);
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ret = 1;
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/*ret = !gpio_get_value(USDHC2_CD_GPIO);*/
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break;
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case USDHC3_BASE_ADDR:
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ret = !gpio_get_value(USDHC3_CD_GPIO);
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ret = 0;
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/*ret = !gpio_get_value(USDHC3_CD_GPIO);*/
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break;
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}
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@ -217,13 +197,13 @@ int board_mmc_init(bd_t *bis)
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case 1:
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imx_iomux_v3_setup_multiple_pads(
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usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
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gpio_direction_input(USDHC2_CD_GPIO);
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/*gpio_direction_input(USDHC2_CD_GPIO);*/
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usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
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break;
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case 2:
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imx_iomux_v3_setup_multiple_pads(
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usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
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gpio_direction_input(USDHC3_CD_GPIO);
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/*gpio_direction_input(USDHC3_CD_GPIO);*/
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usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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break;
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default:
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@ -261,7 +241,7 @@ int board_mmc_init(bd_t *bis)
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case 1:
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imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
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ARRAY_SIZE(usdhc2_pads));
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gpio_direction_input(USDHC2_CD_GPIO);
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/*gpio_direction_input(USDHC2_CD_GPIO);*/
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usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
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usdhc_cfg[0].max_bus_width = 4;
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
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@ -269,7 +249,7 @@ int board_mmc_init(bd_t *bis)
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case 2:
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imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
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ARRAY_SIZE(usdhc3_pads));
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gpio_direction_input(USDHC3_CD_GPIO);
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/*gpio_direction_input(USDHC3_CD_GPIO);*/
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usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
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usdhc_cfg[0].max_bus_width = 4;
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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@ -1,5 +1,4 @@
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CONFIG_ARM=y
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CONFIG_SYS_L2CACHE_OFF=y
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CONFIG_ARCH_MX6=y
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CONFIG_TARGET_ZERO_GRAVITAS=y
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CONFIG_LOCALVERSION="-zero-gravitas"
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@ -11,11 +10,10 @@ CONFIG_CMD_BOOTZ=y
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CONFIG_CMD_GREPENV=y
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CONFIG_CMD_MEMTEST=y
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CONFIG_CMD_MEMINFO=y
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# CONFIG_CMD_FLASH is not set
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CONFIG_CMD_MMC=y
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CONFIG_CMD_SF=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_USB=y
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# CONFIG_CMD_FPGA is not set
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CONFIG_CMD_GPIO=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_DHCP=y
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@ -24,7 +22,6 @@ CONFIG_CMD_PING=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_EXT2=y
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CONFIG_CMD_EXT4=y
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CONFIG_CMD_EXT4_WRITE=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FS_GENERIC=y
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CONFIG_DM=y
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@ -32,3 +29,4 @@ CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_DM_THERMAL=y
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CONFIG_OF_LIBFDT=y
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# CONFIG_EFI_LOADER is not set
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@ -61,9 +61,9 @@
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"fdt_addr=0x88000000\0" \
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"boot_fdt=try\0" \
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"ip_dyn=yes\0" \
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"mmcdev=1\0" \
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"mmcdev=0\0" \
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"mmcpart=1\0" \
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"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
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"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
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"mmcargs=setenv bootargs console=${console},${baudrate} " \
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"root=${mmcroot}\0" \
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"loadbootscript=" \
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@ -103,7 +103,8 @@
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"bootz ${loadaddr} - ${fdt_addr}; " \
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"else " \
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"if test ${boot_fdt} = try; then " \
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"bootz ${loadaddr} - ${fdt_addr}; " \
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"setenv bootargs console=${console},${baudrate} rdinit=/linuxrc; " \
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"bootz ${loadaddr} 0x89000000 ${fdt_addr}; " \
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"else " \
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"echo WARN: Cannot load the DT; " \
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"fi; " \
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