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[PATCH] Update Yosemite (440EP) to display board rev and PCI bus speed 

Now the board revision and the current PCI bus speed are printed after
the board message.

Also the EBC initialising is now done via defines in the board config
file.

Signed-off-by: Stefan Roese <sr@denx.de>
utp
Stefan Roese 2007-01-13 07:59:19 +01:00
parent e0b9ea8c8a
commit 36adff362c
2 changed files with 21 additions and 18 deletions
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25
board/amcc/yosemite/yosemite.c
View File

@ -39,24 +39,6 @@ int board_early_init_f(void)
reg = mfdcr(ebccfgd);
mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */
mtebc(pb0cr, 0xfc0da000); /* BAS=0xfc0 64MB r/w 16-bit */
mtebc(pb1ap, 0x00000000);
mtebc(pb1cr, 0x00000000);
mtebc(pb2ap, 0x04814500);
/*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */
mtebc(pb3ap, 0x00000000);
mtebc(pb3cr, 0x00000000);
mtebc(pb4ap, 0x00000000);
mtebc(pb4cr, 0x00000000);
mtebc(pb5ap, 0x00000000);
mtebc(pb5cr, 0x00000000);
/*--------------------------------------------------------------------
* Setup the GPIO pins
*-------------------------------------------------------------------*/
@ -186,8 +168,15 @@ int misc_init_r (void)
int checkboard(void)
{
char *s = getenv("serial#");
u8 rev;
u8 val;
printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
rev = *(u8 *)(CFG_CPLD + 0);
val = *(u8 *)(CFG_CPLD + 5) & 0x01;
printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
if (s != NULL) {
puts(", serial# ");
puts(s);

14
include/configs/yosemite.h
View File

@ -306,6 +306,20 @@
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
#define CFG_FLASH CFG_FLASH_BASE
#define CFG_CPLD 0x80000000
/* Memory Bank 0 (NOR-FLASH) initialization */
#define CFG_EBC_PB0AP 0x03017300
#define CFG_EBC_PB0CR (CFG_FLASH | 0xda000)
/* Memory Bank 2 (CPLD) initialization */
#define CFG_EBC_PB2AP 0x04814500
#define CFG_EBC_PB2CR (CFG_CPLD | 0x18000)
/*-----------------------------------------------------------------------
* Cache Configuration
*/