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sun6i: Make dram clk and zq value Kconfig options 

It turns out that there is a too large spread between boards to handle this
with a default value, turn this into Kconfig options, and set the values
the factory images are using for the Colombus and Mele_M9 boards.

Note this changes the ZQ default when not overriden through defconfig from
120 to 123, as that is what most boards seem to actually use.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
utp
Hans de Goede 2014-11-15 19:46:39 +01:00
parent 5f88ed5cde
commit 37781a1a7e
4 changed files with 26 additions and 7 deletions
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12
arch/arm/cpu/armv7/sunxi/dram_sun6i.c
View File

@ -17,9 +17,7 @@
#include <asm/arch/dram.h>
#include <asm/arch/prcm.h>
/* DRAM clk & zq defaults, maybe turn these into Kconfig options ? */
#define DRAM_CLK_DEFAULT 312000000
#define DRAM_ZQ_DEFAULT 0x78
#define DRAM_CLK (CONFIG_DRAM_CLK * 1000000)
struct dram_sun6i_para {
u8 bus_width;
@ -48,7 +46,7 @@ static void mctl_sys_init(void)
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
const int dram_clk_div = 2;
clock_set_pll5(DRAM_CLK_DEFAULT * dram_clk_div);
clock_set_pll5(DRAM_CLK * dram_clk_div);
clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV0_MASK,
CCM_DRAMCLK_CFG_DIV0(dram_clk_div) | CCM_DRAMCLK_CFG_RST |
@ -170,7 +168,7 @@ static void mctl_channel_init(int ch_index, struct dram_sun6i_para *para)
await_completion(&mctl_phy->pgsr, 0x03, 0x03);
writel(DRAM_ZQ_DEFAULT, &mctl_phy->zq0cr1);
writel(CONFIG_DRAM_ZQ, &mctl_phy->zq0cr1);
setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS);
writel(MCTL_PIR_STEP1, &mctl_phy->pir);
@ -216,9 +214,9 @@ static void mctl_channel_init(int ch_index, struct dram_sun6i_para *para)
await_completion(&mctl_ctl->sstat, 0x07, 0x01);
/* Set number of clks per micro-second */
writel(DRAM_CLK_DEFAULT / 1000000, &mctl_ctl->togcnt1u);
writel(DRAM_CLK / 1000000, &mctl_ctl->togcnt1u);
/* Set number of clks per 100 nano-seconds */
writel(DRAM_CLK_DEFAULT / 10000000, &mctl_ctl->togcnt100n);
writel(DRAM_CLK / 10000000, &mctl_ctl->togcnt100n);
/* Set memory timing registers */
writel(MCTL_TREFI, &mctl_ctl->trefi);
writel(MCTL_TMRD, &mctl_ctl->tmrd);

17
board/sunxi/Kconfig
View File

@ -32,6 +32,23 @@ config MACH_SUN8I
endchoice
if MACH_SUN6I
config DRAM_CLK
int "sun6i dram clock speed"
default 312
---help---
Set the dram clock speed, valid range 240 - 480, must be a multiple
of 24.
config DRAM_ZQ
int "sun6i dram zq value"
default 123
---help---
Set the dram zq value.
endif
config SYS_CONFIG_NAME
default "sun4i" if MACH_SUN4I
default "sun5i" if MACH_SUN5I

2
configs/Colombus_defconfig
View File

@ -5,3 +5,5 @@ CONFIG_USB_KEYBOARD=n
+S:CONFIG_ARCH_SUNXI=y
+S:CONFIG_MACH_SUN6I=y
+S:CONFIG_TARGET_COLOMBUS=y
+S:CONFIG_DRAM_CLK=288
+S:CONFIG_DRAM_ZQ=379

2
configs/Mele_M9_defconfig
View File

@ -5,6 +5,8 @@ CONFIG_FDTFILE="sun6i-a31-m9.dtb"
+S:CONFIG_ARCH_SUNXI=y
+S:CONFIG_MACH_SUN6I=y
+S:CONFIG_TARGET_MELE_M9=y
+S:CONFIG_DRAM_CLK=312
+S:CONFIG_DRAM_ZQ=120
# Ethernet phy power
+S:CONFIG_AXP221_DLDO1_VOLT=3300
# USB hub power