ppc4xx: Improve DDR autodetect
Added support for a second memory bank to DDR autodetection for 440 platforms. Made hardcoded values configurable. Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
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@ -259,6 +259,7 @@ phys_size_t initdram(int board_type)
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#ifndef CONFIG_SYS_SDRAM_TABLE
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#ifndef CONFIG_SYS_SDRAM_TABLE
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sdram_conf_t mb0cf[] = {
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sdram_conf_t mb0cf[] = {
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{(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4) */
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{(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4) */
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{(128 << 20), 13, 0x000A4001}, /* 128MB mode 3, 13x10(4) */
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{(64 << 20), 12, 0x00082001} /* 64MB mode 2, 12x9(4) */
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{(64 << 20), 12, 0x00082001} /* 64MB mode 2, 12x9(4) */
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};
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};
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#else
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#else
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@ -269,6 +270,18 @@ sdram_conf_t mb0cf[] = CONFIG_SYS_SDRAM_TABLE;
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#define CONFIG_SYS_SDRAM0_TR0 0x41094012
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#define CONFIG_SYS_SDRAM0_TR0 0x41094012
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#endif
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#endif
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#ifndef CONFIG_SYS_SDRAM0_WDDCTR
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#define CONFIG_SYS_SDRAM0_WDDCTR 0x00000000 /* wrcp=0 dcd=0 */
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#endif
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#ifndef CONFIG_SYS_SDRAM0_RTR
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#define CONFIG_SYS_SDRAM0_RTR 0x04100000 /* 7.8us @ 133MHz PLB */
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#endif
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#ifndef CONFIG_SYS_SDRAM0_CFG0
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#define CONFIG_SYS_SDRAM0_CFG0 0x82000000 /* DCEN=1, PMUD=0, 64-bit */
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#endif
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#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
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#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
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#define NUM_TRIES 64
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#define NUM_TRIES 64
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@ -378,7 +391,7 @@ phys_size_t initdram(int board_type)
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mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
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mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
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mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
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mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
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mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
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mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
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mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
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mtsdram(mem_wddctr, CONFIG_SYS_SDRAM0_WDDCTR);
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mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
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mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
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/*
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/*
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@ -387,31 +400,63 @@ phys_size_t initdram(int board_type)
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mtsdram(mem_b0cr, mb0cf[i].reg);
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mtsdram(mem_b0cr, mb0cf[i].reg);
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mtsdram(mem_tr0, CONFIG_SYS_SDRAM0_TR0);
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mtsdram(mem_tr0, CONFIG_SYS_SDRAM0_TR0);
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mtsdram(mem_tr1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
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mtsdram(mem_tr1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
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mtsdram(mem_rtr, 0x04100000); /* Interval 7.8µs @ 133MHz PLB */
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mtsdram(mem_rtr, CONFIG_SYS_SDRAM0_RTR);
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mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM*/
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mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM*/
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udelay(400); /* Delay 200 usecs (min) */
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udelay(400); /* Delay 200 usecs (min) */
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/*
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/*
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* Enable the controller, then wait for DCEN to complete
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* Enable the controller, then wait for DCEN to complete
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*/
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*/
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mtsdram(mem_cfg0, 0x82000000); /* DCEN=1, PMUD=0, 64-bit */
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mtsdram(mem_cfg0, CONFIG_SYS_SDRAM0_CFG0);
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udelay(10000);
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udelay(10000);
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if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
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if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
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phys_size_t size = mb0cf[i].size;
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/*
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/*
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* Optimize TR1 to current hardware environment
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* Optimize TR1 to current hardware environment
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*/
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*/
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sdram_tr1_set(0x00000000, &tr1_bank1);
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sdram_tr1_set(0x00000000, &tr1_bank1);
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mtsdram(mem_tr1, (tr1_bank1 | 0x80800800));
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mtsdram(mem_tr1, (tr1_bank1 | 0x80800800));
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/*
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* OK, size detected. Enable second bank if
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* defined (assumes same type as bank 0)
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*/
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#ifdef CONFIG_SDRAM_BANK1
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mtsdram(mem_cfg0, 0);
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mtsdram(mem_b1cr, mb0cf[i].size | mb0cf[i].reg);
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mtsdram(mem_cfg0, CONFIG_SYS_SDRAM0_CFG0);
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udelay(10000);
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/*
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* Check if 2nd bank is really available.
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* If the size not equal to the size of the first
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* bank, then disable the 2nd bank completely.
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*/
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if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size)
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!= mb0cf[i].size) {
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mtsdram(mem_cfg0, 0);
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mtsdram(mem_b1cr, 0);
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mtsdram(mem_cfg0, CONFIG_SYS_SDRAM0_CFG0);
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udelay(10000);
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} else {
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/*
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* We have two identical banks, so the size
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* is twice the bank size
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*/
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size = 2 * size;
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}
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#endif
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#ifdef CONFIG_SDRAM_ECC
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#ifdef CONFIG_SDRAM_ECC
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ecc_init(0, mb0cf[i].size);
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ecc_init(0, size);
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#endif
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#endif
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/*
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/*
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* OK, size detected -> all done
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* OK, size detected -> all done
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*/
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*/
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return mb0cf[i].size;
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return size;
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}
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}
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}
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}
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