arm, da850evm: Add an SPL for SPI boot
Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Heiko Schocher <hs@denx.de> Cc: Sandeep Paulraj <s-paulraj@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com>utp
Christian Riesch
Albert ARIBAUD
parent
620fd27cfa
commit
3d2c8e6c7f
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@ -108,7 +108,7 @@ static const struct pinmux_config gpio_pins[] = {
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#endif
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};
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static const struct pinmux_resource pinmuxes[] = {
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const struct pinmux_resource pinmuxes[] = {
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#ifdef CONFIG_DRIVER_TI_EMAC
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PINMUX_ITEM(emac_pins_mdio),
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#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
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@ -135,6 +135,8 @@ static const struct pinmux_resource pinmuxes[] = {
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PINMUX_ITEM(gpio_pins),
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};
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const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
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static const struct lpsc_resource lpsc[] = {
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{ DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
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{ DAVINCI_LPSC_SPI1 }, /* Serial Flash */
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@ -0,0 +1,73 @@
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/*
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* (C) Copyright 2002
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* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
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*
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* (C) Copyright 2008
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* Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
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LENGTH = CONFIG_SPL_MAX_SIZE }
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
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OUTPUT_ARCH(arm)
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ENTRY(_start)
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SECTIONS
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{
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. = 0x00000000;
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. = ALIGN(4);
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.text :
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{
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__start = .;
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arch/arm/cpu/arm926ejs/start.o (.text)
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*(.text*)
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} >.sram
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. = ALIGN(4);
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.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
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. = ALIGN(4);
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.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
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. = ALIGN(4);
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.rel.dyn : {
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__rel_dyn_start = .;
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*(.rel*)
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__rel_dyn_end = .;
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} >.sram
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.dynsym : {
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__dynsym_start = .;
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*(.dynsym)
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} >.sram
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.bss :
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{
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. = ALIGN(4);
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__bss_start = .;
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*(.bss*)
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. = ALIGN(4);
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__bss_end__ = .;
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} >.sram
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__image_copy_end = .;
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_end = .;
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}
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@ -95,6 +95,15 @@ into the RAM.
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The programmers and UBL are always released as part of any standard TI
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software release associated with an SOC.
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Alternative boot method (DA850 EVM only):
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For the DA850 EVM an SPL (secondary program loader, see doc/README.SPL)
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is provided to load U-Boot directly from SPI flash. In this case, the
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SPL does the low level initialization that is otherwise done by the SPL.
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To build U-Boot with this SPL, do
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make da850evm_config
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make u-boot.ais
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and program the resulting u-boot.ais file to the SPI flash of the DA850 EVM.
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Environment Variables
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=====================
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@ -65,6 +65,75 @@
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
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#define CONFIG_STACKSIZE (256*1024) /* regular stack */
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#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
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DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
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DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
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DAVINCI_SYSCFG_SUSPSRC_UART2 | \
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DAVINCI_SYSCFG_SUSPSRC_EMAC | \
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DAVINCI_SYSCFG_SUSPSRC_I2C)
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/*
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* PLL configuration
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*/
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#define CONFIG_SYS_DV_CLKMODE 0
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#define CONFIG_SYS_DA850_PLL0_POSTDIV 1
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#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
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#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
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#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
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#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
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#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
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#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
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#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
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#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
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#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
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#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
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#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
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#define CONFIG_SYS_DA850_PLL0_PLLM 24
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#define CONFIG_SYS_DA850_PLL1_PLLM 21
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/*
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* DDR2 memory configuration
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*/
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#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
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DV_DDR_PHY_EXT_STRBEN | \
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(0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
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#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
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(1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
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(1 << DV_DDR_SDCR_DDREN_SHIFT) | \
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(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
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(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
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(0x3 << DV_DDR_SDCR_CL_SHIFT) | \
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(0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \
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(0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
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/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
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#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
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#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
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(14 << DV_DDR_SDTMR1_RFC_SHIFT) | \
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(2 << DV_DDR_SDTMR1_RP_SHIFT) | \
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(2 << DV_DDR_SDTMR1_RCD_SHIFT) | \
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(1 << DV_DDR_SDTMR1_WR_SHIFT) | \
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(5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
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(8 << DV_DDR_SDTMR1_RC_SHIFT) | \
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(1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
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(0 << DV_DDR_SDTMR1_WTR_SHIFT))
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#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
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(7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
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(0 << DV_DDR_SDTMR2_XP_SHIFT) | \
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(0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
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(17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
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(199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
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(0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
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(0 << DV_DDR_SDTMR2_CKE_SHIFT))
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#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494
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#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
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/*
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* Serial Driver info
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*/
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@ -76,6 +145,7 @@
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#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
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#define CONFIG_BAUDRATE 115200 /* Default baud rate */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#define CONFIG_SYS_DA850_LPSC_UART DAVINCI_LPSC_UART2
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#define CONFIG_SPI
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#define CONFIG_SPI_FLASH
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@ -242,6 +312,23 @@
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#undef CONFIG_CMD_ENV
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#endif
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/* defines for SPL */
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#define CONFIG_SPL
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#define CONFIG_SPL_SPI_SUPPORT
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#define CONFIG_SPL_SPI_FLASH_SUPPORT
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#define CONFIG_SPL_SPI_LOAD
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#define CONFIG_SPL_SPI_BUS 0
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#define CONFIG_SPL_SPI_CS 0
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_LDSCRIPT "$(BOARDDIR)/u-boot-spl.lds"
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#define CONFIG_SPL_STACK 0x8001ff00
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#define CONFIG_SPL_TEXT_BASE 0x80000000
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#define CONFIG_SPL_MAX_SIZE 32768
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
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#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000
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/* additions for new relocation code, must added to all boards */
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#define CONFIG_SYS_SDRAM_BASE 0xc0000000
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
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