Merge branch 'master' of git://git.denx.de/u-boot-arm
Tom Rini
commit
3e1b36bd58
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@ -17,6 +17,9 @@ obj-$(CONFIG_SUN7I) += clock_sun4i.o
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ifndef CONFIG_SPL_BUILD
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obj-y += cpu_info.o
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ifdef CONFIG_ARMV7_PSCI
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obj-y += psci.o
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endif
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endif
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ifdef CONFIG_SPL_BUILD
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@ -129,6 +129,11 @@ int cpu_eth_init(bd_t *bis)
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{
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__maybe_unused int rc;
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#ifdef CONFIG_MACPWR
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gpio_direction_output(CONFIG_MACPWR, 1);
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mdelay(200);
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#endif
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#ifdef CONFIG_SUNXI_EMAC
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rc = sunxi_emac_initialize(bis);
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if (rc < 0) {
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@ -39,6 +39,10 @@ void clock_init_safe(void)
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setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA);
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#endif
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writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
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#ifdef CONFIG_SUNXI_AHCI
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setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA);
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setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT);
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#endif
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}
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#endif
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@ -0,0 +1,162 @@
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/*
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* Copyright (C) 2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* Based on code by Carl van Schaik <carl@ok-labs.com>.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <config.h>
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#include <asm/psci.h>
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#include <asm/arch/cpu.h>
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/*
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* Memory layout:
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*
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* SECURE_RAM to text_end :
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* ._secure_text section
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* text_end to ALIGN_PAGE(text_end):
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* nothing
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* ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x1000)
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* 1kB of stack per CPU (4 CPUs max).
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*/
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.pushsection ._secure.text, "ax"
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.arch_extension sec
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#define ONE_MS (CONFIG_SYS_CLK_FREQ / 1000)
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#define TEN_MS (10 * ONE_MS)
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.macro timer_wait reg, ticks
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@ Program CNTP_TVAL
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movw \reg, #(\ticks & 0xffff)
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movt \reg, #(\ticks >> 16)
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mcr p15, 0, \reg, c14, c2, 0
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isb
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@ Enable physical timer, mask interrupt
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mov \reg, #3
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mcr p15, 0, \reg, c14, c2, 1
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@ Poll physical timer until ISTATUS is on
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1: isb
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mrc p15, 0, \reg, c14, c2, 1
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ands \reg, \reg, #4
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bne 1b
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@ Disable timer
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mov \reg, #0
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mcr p15, 0, \reg, c14, c2, 1
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isb
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.endm
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.globl psci_arch_init
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psci_arch_init:
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mrc p15, 0, r5, c1, c1, 0 @ Read SCR
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bic r5, r5, #1 @ Secure mode
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mcr p15, 0, r5, c1, c1, 0 @ Write SCR
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isb
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mrc p15, 0, r4, c0, c0, 5 @ MPIDR
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and r4, r4, #3 @ cpu number in cluster
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mov r5, #400 @ 1kB of stack per CPU
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mul r4, r4, r5
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adr r5, text_end @ end of text
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add r5, r5, #0x2000 @ Skip two pages
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lsr r5, r5, #12 @ Align to start of page
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lsl r5, r5, #12
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sub sp, r5, r4 @ here's our stack!
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bx lr
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@ r1 = target CPU
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@ r2 = target PC
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.globl psci_cpu_on
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psci_cpu_on:
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adr r0, _target_pc
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str r2, [r0]
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dsb
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movw r0, #(SUNXI_CPUCFG_BASE & 0xffff)
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movt r0, #(SUNXI_CPUCFG_BASE >> 16)
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@ CPU mask
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and r1, r1, #3 @ only care about first cluster
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mov r4, #1
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lsl r4, r4, r1
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adr r6, _sunxi_cpu_entry
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str r6, [r0, #0x1a4] @ PRIVATE_REG (boot vector)
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@ Assert reset on target CPU
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mov r6, #0
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lsl r5, r1, #6 @ 64 bytes per CPU
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add r5, r5, #0x40 @ Offset from base
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add r5, r5, r0 @ CPU control block
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str r6, [r5] @ Reset CPU
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@ l1 invalidate
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ldr r6, [r0, #0x184]
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bic r6, r6, r4
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str r6, [r0, #0x184]
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@ Lock CPU
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ldr r6, [r0, #0x1e4]
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bic r6, r6, r4
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str r6, [r0, #0x1e4]
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@ Release power clamp
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movw r6, #0x1ff
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movt r6, #0
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1: lsrs r6, r6, #1
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str r6, [r0, #0x1b0]
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bne 1b
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timer_wait r1, TEN_MS
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@ Clear power gating
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ldr r6, [r0, #0x1b4]
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bic r6, r6, #1
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str r6, [r0, #0x1b4]
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@ Deassert reset on target CPU
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mov r6, #3
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str r6, [r5]
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@ Unlock CPU
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ldr r6, [r0, #0x1e4]
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orr r6, r6, r4
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str r6, [r0, #0x1e4]
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mov r0, #ARM_PSCI_RET_SUCCESS @ Return PSCI_RET_SUCCESS
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mov pc, lr
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_target_pc:
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.word 0
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_sunxi_cpu_entry:
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@ Set SMP bit
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mrc p15, 0, r0, c1, c0, 1
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orr r0, r0, #0x40
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mcr p15, 0, r0, c1, c0, 1
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isb
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bl _nonsec_init
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bl psci_arch_init
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adr r0, _target_pc
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ldr r0, [r0]
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b _do_nonsec_entry
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text_end:
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.popsection
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@ -218,10 +218,13 @@ struct sunxi_ccm_reg {
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#define CCM_PLL5_CTRL_BYPASS (0x1 << 30)
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#define CCM_PLL5_CTRL_EN (0x1 << 31)
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#define CCM_PLL6_CTRL_N_SHIFT 8
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#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT)
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#define CCM_PLL6_CTRL_K_SHIFT 4
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#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT)
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#define CCM_PLL6_CTRL_EN 31
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#define CCM_PLL6_CTRL_BYPASS_EN 30
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#define CCM_PLL6_CTRL_SATA_EN_SHIFT 14
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#define CCM_PLL6_CTRL_N_SHIFT 8
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#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT)
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#define CCM_PLL6_CTRL_K_SHIFT 4
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#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT)
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#define CCM_GPS_CTRL_RESET (0x1 << 0)
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#define CCM_GPS_CTRL_GATE (0x1 << 1)
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@ -253,4 +256,8 @@ struct sunxi_ccm_reg {
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#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2)
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#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2)
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#define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
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#define CCM_USB_CTRL_PHY2_RST (0x1 << 2)
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#define CCM_USB_CTRL_PHYGATE (0x1 << 8)
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#endif /* _SUNXI_CLOCK_SUN4I_H */
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@ -2,11 +2,26 @@ SUNXI BOARD
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M: Hans de Goede <hdegoede@redhat.com>
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S: Maintained
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F: board/sunxi/
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F: include/configs/sun5i.h
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F: configs/A13-OLinuXinoM_defconfig
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F: include/configs/sun4i.h
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F: configs/A10-OLinuXino-Lime_defconfig
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F: configs/ba10_tv_box_defconfig
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F: configs/Cubieboard_defconfig
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F: configs/Mele_A1000_defconfig
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F: configs/Mele_A1000G_defconfig
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F: configs/Mini-X_defconfig
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F: configs/Mini-X-1Gb_defconfig
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F: include/configs/sun5i.h
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F: configs/A10s-OLinuXino-M_defconfig
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F: configs/A13-OLinuXino_defconfig
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F: configs/A13-OLinuXinoM_defconfig
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F: configs/Auxtek-T004_defconfig
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F: configs/r7-tv-dongle_defconfig
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F: include/configs/sun7i.h
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F: configs/A20-OLinuXino_MICRO_defconfig
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F: configs/Bananapi_defconfig
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F: configs/i12-tvbox_defconfig
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F: configs/Linksprite_pcDuino3_defconfig
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F: configs/qt840a_defconfig
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CUBIEBOARD2 BOARD
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M: Ian Campbell <ijc@hellion.org.uk>
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@ -10,8 +10,24 @@
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#
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obj-y += board.o
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obj-$(CONFIG_SUNXI_GMAC) += gmac.o
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obj-$(CONFIG_SUNXI_AHCI) += ahci.o
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obj-$(CONFIG_A10_OLINUXINO_L) += dram_a10_olinuxino_l.o
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obj-$(CONFIG_A10S_OLINUXINO_M) += dram_a10s_olinuxino_m.o
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obj-$(CONFIG_A13_OLINUXINO) += dram_a13_olinuxino.o
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obj-$(CONFIG_A13_OLINUXINOM) += dram_a13_oli_micro.o
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obj-$(CONFIG_A20_OLINUXINO_M) += dram_sun7i_384_1024_iow16.o
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# This is not a typo, uses the same mem settings as the a10s-olinuxino-m
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obj-$(CONFIG_AUXTEK_T004) += dram_a10s_olinuxino_m.o
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obj-$(CONFIG_BA10_TV_BOX) += dram_sun4i_384_1024_iow8.o
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obj-$(CONFIG_BANANAPI) += dram_bananapi.o
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obj-$(CONFIG_CUBIEBOARD) += dram_cubieboard.o
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obj-$(CONFIG_CUBIEBOARD2) += dram_cubieboard2.o
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obj-$(CONFIG_CUBIETRUCK) += dram_cubietruck.o
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obj-$(CONFIG_I12_TVBOX) += dram_sun7i_384_1024_iow16.o
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obj-$(CONFIG_MELE_A1000) += dram_sun4i_360_512.o
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obj-$(CONFIG_MELE_A1000G) += dram_sun4i_360_1024_iow8.o
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obj-$(CONFIG_MINI_X) += dram_sun4i_360_512.o
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obj-$(CONFIG_MINI_X_1GB) += dram_sun4i_360_1024_iow16.o
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obj-$(CONFIG_PCDUINO3) += dram_linksprite_pcduino3.o
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obj-$(CONFIG_QT840A) += dram_sun7i_384_512_busw16_iow16.o
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obj-$(CONFIG_R7DONGLE) += dram_r7dongle.o
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@ -0,0 +1,84 @@
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#include <common.h>
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#include <ahci.h>
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#include <scsi.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#define AHCI_PHYCS0R 0x00c0
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#define AHCI_PHYCS1R 0x00c4
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#define AHCI_PHYCS2R 0x00c8
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#define AHCI_RWCR 0x00fc
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/* This magic PHY initialisation was taken from the Allwinner releases
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* and Linux driver, but is completely undocumented.
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*/
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static int sunxi_ahci_phy_init(u32 base)
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{
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u8 *reg_base = (u8 *)base;
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u32 reg_val;
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int timeout;
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writel(0, reg_base + AHCI_RWCR);
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mdelay(5);
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setbits_le32(reg_base + AHCI_PHYCS1R, 0x1 << 19);
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clrsetbits_le32(reg_base + AHCI_PHYCS0R,
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(0x7 << 24),
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(0x5 << 24) | (0x1 << 23) | (0x1 << 18));
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clrsetbits_le32(reg_base + AHCI_PHYCS1R,
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(0x3 << 16) | (0x1f << 8) | (0x3 << 6),
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(0x2 << 16) | (0x6 << 8) | (0x2 << 6));
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setbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 28) | (0x1 << 15));
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clrbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 19));
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clrsetbits_le32(reg_base + AHCI_PHYCS0R, (0x7 << 20), (0x3 << 20));
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clrsetbits_le32(reg_base + AHCI_PHYCS2R, (0x1f << 5), (0x19 << 5));
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mdelay(5);
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setbits_le32(reg_base + AHCI_PHYCS0R, (0x1 << 19));
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timeout = 250; /* Power up takes approx 50 us */
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for (;;) {
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reg_val = readl(reg_base + AHCI_PHYCS0R) & (0x7 << 28);
|
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if (reg_val == (0x2 << 28))
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break;
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if (--timeout == 0) {
|
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printf("AHCI PHY power up failed.\n");
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return -EIO;
|
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}
|
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udelay(1);
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};
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setbits_le32(reg_base + AHCI_PHYCS2R, (0x1 << 24));
|
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timeout = 100; /* Calibration takes approx 10 us */
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for (;;) {
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reg_val = readl(reg_base + AHCI_PHYCS2R) & (0x1 << 24);
|
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if (reg_val == 0x0)
|
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break;
|
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if (--timeout == 0) {
|
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printf("AHCI PHY calibration failed.\n");
|
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return -EIO;
|
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}
|
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udelay(1);
|
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}
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||||
|
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mdelay(15);
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|
||||
writel(0x7, reg_base + AHCI_RWCR);
|
||||
|
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return 0;
|
||||
}
|
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|
||||
void scsi_init(void)
|
||||
{
|
||||
printf("SUNXI SCSI INIT\n");
|
||||
#ifdef CONFIG_SATAPWR
|
||||
gpio_direction_output(CONFIG_SATAPWR, 1);
|
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#endif
|
||||
|
||||
if (sunxi_ahci_phy_init(SUNXI_SATA_BASE) < 0)
|
||||
return;
|
||||
|
||||
ahci_init(SUNXI_SATA_BASE);
|
||||
}
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/* this file is generated, don't edit it yourself */
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/dram.h>
|
||||
|
||||
static struct dram_para dram_para = {
|
||||
.clock = 480,
|
||||
.type = 3,
|
||||
.rank_num = 1,
|
||||
.density = 4096,
|
||||
.io_width = 16,
|
||||
.bus_width = 16,
|
||||
.cas = 6,
|
||||
.zq = 123,
|
||||
.odt_en = 0,
|
||||
.size = 512,
|
||||
.tpr0 = 0x30926692,
|
||||
.tpr1 = 0x1090,
|
||||
.tpr2 = 0x1a0c8,
|
||||
.tpr3 = 0,
|
||||
.tpr4 = 0,
|
||||
.tpr5 = 0,
|
||||
.emr1 = 0x4,
|
||||
.emr2 = 0,
|
||||
.emr3 = 0,
|
||||
};
|
||||
|
||||
unsigned long sunxi_dram_init(void)
|
||||
{
|
||||
return dramc_init(&dram_para);
|
||||
}
|
||||
|
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@ -0,0 +1,31 @@
|
|||
/* this file is generated, don't edit it yourself */
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/dram.h>
|
||||
|
||||
static struct dram_para dram_para = {
|
||||
.clock = 432,
|
||||
.type = 3,
|
||||
.rank_num = 1,
|
||||
.density = 4096,
|
||||
.io_width = 16,
|
||||
.bus_width = 16,
|
||||
.cas = 9,
|
||||
.zq = 123,
|
||||
.odt_en = 0,
|
||||
.size = 512,
|
||||
.tpr0 = 0x42d899b7,
|
||||
.tpr1 = 0xa090,
|
||||
.tpr2 = 0x22a00,
|
||||
.tpr3 = 0,
|
||||
.tpr4 = 0,
|
||||
.tpr5 = 0,
|
||||
.emr1 = 0x4,
|
||||
.emr2 = 0x10,
|
||||
.emr3 = 0,
|
||||
};
|
||||
|
||||
unsigned long sunxi_dram_init(void)
|
||||
{
|
||||
return dramc_init(&dram_para);
|
||||
}
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/* this file is generated, don't edit it yourself */
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/dram.h>
|
||||
|
||||
static struct dram_para dram_para = {
|
||||
.clock = 408,
|
||||
.type = 3,
|
||||
.rank_num = 1,
|
||||
.density = 2048,
|
||||
.io_width = 8,
|
||||
.bus_width = 16,
|
||||
.cas = 9,
|
||||
.zq = 123,
|
||||
.odt_en = 0,
|
||||
.size = 512,
|
||||
.tpr0 = 0x42d899b7,
|
||||
.tpr1 = 0xa090,
|
||||
.tpr2 = 0x22a00,
|
||||
.tpr3 = 0,
|
||||
.tpr4 = 0,
|
||||
.tpr5 = 0,
|
||||
.emr1 = 0,
|
||||
.emr2 = 0x10,
|
||||
.emr3 = 0,
|
||||
};
|
||||
|
||||
unsigned long sunxi_dram_init(void)
|
||||
{
|
||||
return dramc_init(&dram_para);
|
||||
}
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/* this file is generated, don't edit it yourself */
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/dram.h>
|
||||
|
||||
static struct dram_para dram_para = {
|
||||
.clock = 432,
|
||||
.type = 3,
|
||||
.rank_num = 1,
|
||||
.density = 4096,
|
||||
.io_width = 16,
|
||||
.bus_width = 32,
|
||||
.cas = 9,
|
||||
.zq = 0x7f,
|
||||
.odt_en = 0,
|
||||
.size = 1024,
|
||||
.tpr0 = 0x42d899b7,
|
||||
.tpr1 = 0xa090,
|
||||
.tpr2 = 0x22a00,
|
||||
.tpr3 = 0x0,
|
||||
.tpr4 = 0x1,
|
||||
.tpr5 = 0x0,
|
||||
.emr1 = 0x4,
|
||||
.emr2 = 0x10,
|
||||
.emr3 = 0x0,
|
||||
};
|
||||
|
||||
unsigned long sunxi_dram_init(void)
|
||||
{
|
||||
return dramc_init(&dram_para);
|
||||
}
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/* this file is generated, don't edit it yourself */
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/dram.h>
|
||||
|
||||
static struct dram_para dram_para = {
|
||||
.clock = 480,
|
||||
.type = 3,
|
||||
.rank_num = 1,
|
||||
.density = 4096,
|
||||
.io_width = 16,
|
||||
.bus_width = 32,
|
||||
.cas = 9,
|
||||
.zq = 0x7a,
|
||||
.odt_en = 0,
|
||||
.size = 1024,
|
||||
.tpr0 = 0x42d899b7,
|
||||
.tpr1 = 0xa090,
|
||||
.tpr2 = 0x22a00,
|
||||
.tpr3 = 0,
|
||||
.tpr4 = 0,
|
||||
.tpr5 = 0,
|
||||
.emr1 = 0x4,
|
||||
.emr2 = 0x10,
|
||||
.emr3 = 0x0,
|
||||
};
|
||||
|
||||
unsigned long sunxi_dram_init(void)
|
||||
{
|
||||
return dramc_init(&dram_para);
|
||||
}
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/* this file is generated, don't edit it yourself */
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/dram.h>
|
||||
|
||||
static struct dram_para dram_para = {
|
||||
.clock = 360,
|
||||
.type = 3,
|
||||
.rank_num = 1,
|
||||
.density = 4096,
|
||||
.io_width = 16,
|
||||
.bus_width = 32,
|
||||
.cas = 6,
|
||||
.zq = 123,
|
||||
.odt_en = 0,
|
||||
.size = 1024,
|
||||
.tpr0 = 0x30926692,
|
||||
.tpr1 = 0x1090,
|
||||
.tpr2 = 0x1a0c8,
|
||||
.tpr3 = 0,
|
||||
.tpr4 = 0,
|
||||
.tpr5 = 0,
|
||||
.emr1 = 0,
|
||||
.emr2 = 0,
|
||||
.emr3 = 0,
|
||||
};
|
||||
|
||||
unsigned long sunxi_dram_init(void)
|
||||
{
|
||||
return dramc_init(&dram_para);
|
||||
}
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/* this file is generated, don't edit it yourself */
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/dram.h>
|
||||
|
||||
static struct dram_para dram_para = {
|
||||
.clock = 360,
|
||||
.type = 3,
|
||||
.rank_num = 1,
|
||||
.density = 2048,
|
||||
.io_width = 8,
|
||||
.bus_width = 32,
|
||||
.cas = 6,
|
||||
.zq = 123,
|
||||
.odt_en = 0,
|
||||
.size = 1024,
|
||||
.tpr0 = 0x30926692,
|
||||
.tpr1 = 0x1090,
|
||||
.tpr2 = 0x1a0c8,
|
||||
.tpr3 = 0,
|
||||
.tpr4 = 0,
|
||||
.tpr5 = 0,
|
||||
.emr1 = 0,
|
||||
.emr2 = 0,
|
||||
.emr3 = 0,
|
||||
};
|
||||
|
||||
unsigned long sunxi_dram_init(void)
|
||||
{
|
||||
return dramc_init(&dram_para);
|
||||
}
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/* this file is generated, don't edit it yourself */
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/dram.h>
|
||||
|
||||
static struct dram_para dram_para = {
|
||||
.clock = 360,
|
||||
.type = 3,
|
||||
.rank_num = 1,
|
||||
.density = 2048,
|
||||
.io_width = 16,
|
||||
.bus_width = 32,
|
||||
.cas = 6,
|
||||
.zq = 123,
|
||||
.odt_en = 0,
|
||||
.size = 512,
|
||||
.tpr0 = 0x30926692,
|
||||
.tpr1 = 0x1090,
|
||||
.tpr2 = 0x1a0c8,
|
||||
.tpr3 = 0,
|
||||
.tpr4 = 0,
|
||||
.tpr5 = 0,
|
||||
.emr1 = 0,
|
||||
.emr2 = 0,
|
||||
.emr3 = 0,
|
||||
};
|
||||
|
||||
unsigned long sunxi_dram_init(void)
|
||||
{
|
||||
return dramc_init(&dram_para);
|
||||
}
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/* this file is generated, don't edit it yourself */
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/dram.h>
|
||||
|
||||
static struct dram_para dram_para = {
|
||||
.clock = 384,
|
||||
.type = 3,
|
||||
.rank_num = 1,
|
||||
.density = 2048,
|
||||
.io_width = 8,
|
||||
.bus_width = 32,
|
||||
.cas = 6,
|
||||
.zq = 123,
|
||||
.odt_en = 0,
|
||||
.size = 1024,
|
||||
.tpr0 = 0x30926692,
|
||||
.tpr1 = 0x1090,
|
||||
.tpr2 = 0x1a0c8,
|
||||
.tpr3 = 0,
|
||||
.tpr4 = 0,
|
||||
.tpr5 = 0,
|
||||
.emr1 = 0x4,
|
||||
.emr2 = 0,
|
||||
.emr3 = 0,
|
||||
};
|
||||
|
||||
unsigned long sunxi_dram_init(void)
|
||||
{
|
||||
return dramc_init(&dram_para);
|
||||
}
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/* this file is generated, don't edit it yourself */
|
||||
|
||||
#include "common.h"
|
||||
#include <asm/arch/dram.h>
|
||||
|
||||
static struct dram_para dram_para = {
|
||||
.clock = 384,
|
||||
.type = 3,
|
||||
.rank_num = 1,
|
||||
.density = 4096,
|
||||
.io_width = 16,
|
||||
.bus_width = 32,
|
||||
.cas = 9,
|
||||
.zq = 0x7f,
|
||||
.odt_en = 0,
|
||||
.size = 1024,
|
||||
.tpr0 = 0x42d899b7,
|
||||
.tpr1 = 0xa090,
|
||||
.tpr2 = 0x22a00,
|
||||
.tpr3 = 0,
|
||||
.tpr4 = 0,
|
||||
.tpr5 = 0,
|
||||
.emr1 = 0x4,
|
||||
.emr2 = 0x10,
|
||||
.emr3 = 0,
|
||||
};
|
||||
|
||||
unsigned long sunxi_dram_init(void)
|
||||
{
|
||||
return dramc_init(&dram_para);
|
||||
}
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/* this file is generated, don't edit it yourself */
|
||||
|
||||
#include "common.h"
|
||||
#include <asm/arch/dram.h>
|
||||
|
||||
static struct dram_para dram_para = {
|
||||
.clock = 384,
|
||||
.type = 3,
|
||||
.rank_num = 1,
|
||||
.density = 4096,
|
||||
.io_width = 16,
|
||||
.bus_width = 16,
|
||||
.cas = 9,
|
||||
.zq = 0x7f,
|
||||
.odt_en = 0,
|
||||
.size = 512,
|
||||
.tpr0 = 0x42d899b7,
|
||||
.tpr1 = 0xa090,
|
||||
.tpr2 = 0x22a00,
|
||||
.tpr3 = 0,
|
||||
.tpr4 = 0,
|
||||
.tpr5 = 0,
|
||||
.emr1 = 0x4,
|
||||
.emr2 = 0x10,
|
||||
.emr3 = 0,
|
||||
};
|
||||
|
||||
unsigned long sunxi_dram_init(void)
|
||||
{
|
||||
return dramc_init(&dram_para);
|
||||
}
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
CONFIG_SPL=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="A10_OLINUXINO_L,SPL,AXP209_POWER,SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI"
|
||||
+S:CONFIG_ARM=y
|
||||
+S:CONFIG_TARGET_SUN4I=y
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
CONFIG_SPL=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="A10S_OLINUXINO_M,SPL,AXP152_POWER,SUNXI_EMAC,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPB(10)"
|
||||
+S:CONFIG_ARM=y
|
||||
+S:CONFIG_TARGET_SUN5I=y
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
CONFIG_SPL=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="A13_OLINUXINOM,SPL,CONS_INDEX=2"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="A13_OLINUXINOM,SPL,CONS_INDEX=2,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPG(11)"
|
||||
+S:CONFIG_ARM=y
|
||||
+S:CONFIG_TARGET_SUN5I=y
|
||||
|
|
|
|||
|
|
@ -0,0 +1,4 @@
|
|||
CONFIG_SPL=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="A13_OLINUXINO,SPL,CONS_INDEX=2,AXP209_POWER,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPG(11)"
|
||||
+S:CONFIG_ARM=y
|
||||
+S:CONFIG_TARGET_SUN5I=y
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
CONFIG_SPL=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="A20_OLINUXINO_M,SPL,AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
|
||||
+S:CONFIG_ARM=y
|
||||
+S:CONFIG_TARGET_SUN7I=y
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
CONFIG_SPL=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="AUXTEK_T004,SPL,AXP152_POWER,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPG(13)"
|
||||
+S:CONFIG_ARM=y
|
||||
+S:CONFIG_TARGET_SUN5I=y
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
CONFIG_SPL=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="BANANAPI,SPL,AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,USB_EHCI"
|
||||
+S:CONFIG_ARM=y
|
||||
+S:CONFIG_TARGET_SUN7I=y
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
CONFIG_SPL=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="CUBIEBOARD2,SPL_FEL,SUNXI_GMAC"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="CUBIEBOARD2,SPL_FEL,AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
|
||||
+S:CONFIG_ARM=y
|
||||
+S:CONFIG_TARGET_SUN7I=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
CONFIG_SPL=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="CUBIEBOARD2,SPL,SUNXI_GMAC"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="CUBIEBOARD2,SPL,AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
|
||||
+S:CONFIG_ARM=y
|
||||
+S:CONFIG_TARGET_SUN7I=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
CONFIG_SPL=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="CUBIEBOARD,SPL,AXP209_POWER,SUNXI_EMAC"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="CUBIEBOARD,SPL,AXP209_POWER,SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
|
||||
+S:CONFIG_ARM=y
|
||||
+S:CONFIG_TARGET_SUN4I=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
CONFIG_SPL=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="CUBIETRUCK,SPL_FEL,AXP209_POWER,SUNXI_GMAC,RGMII"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="CUBIETRUCK,SPL_FEL,AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12),USB_EHCI"
|
||||
+S:CONFIG_ARM=y
|
||||
+S:CONFIG_TARGET_SUN7I=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
CONFIG_SPL=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="CUBIETRUCK,SPL,AXP209_POWER,SUNXI_GMAC,RGMII"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="CUBIETRUCK,SPL,AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12),USB_EHCI"
|
||||
+S:CONFIG_ARM=y
|
||||
+S:CONFIG_TARGET_SUN7I=y
|
||||
|
|
|
|||
|
|
@ -0,0 +1,4 @@
|
|||
CONFIG_SPL=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="PCDUINO3,SPL,AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI"
|
||||
+S:CONFIG_ARM=y
|
||||
+S:CONFIG_TARGET_SUN7I=y
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
CONFIG_SPL=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="MELE_A1000G,SPL,AXP209_POWER,SUNXI_EMAC,MACPWR=SUNXI_GPH(15),AHCI,USB_EHCI"
|
||||
+S:CONFIG_ARM=y
|
||||
+S:CONFIG_TARGET_SUN4I=y
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
CONFIG_SPL=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="MELE_A1000,SPL,AXP209_POWER,SUNXI_EMAC,MACPWR=SUNXI_GPH(15),AHCI,USB_EHCI"
|
||||
+S:CONFIG_ARM=y
|
||||
+S:CONFIG_TARGET_SUN4I=y
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
CONFIG_SPL=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="MINI_X_1GB,SPL,AXP209_POWER,USB_EHCI"
|
||||
+S:CONFIG_ARM=y
|
||||
+S:CONFIG_TARGET_SUN4I=y
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
CONFIG_SPL=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="MINI_X,SPL,AXP209_POWER,USB_EHCI"
|
||||
+S:CONFIG_ARM=y
|
||||
+S:CONFIG_TARGET_SUN4I=y
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
CONFIG_SPL=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="BA10_TV_BOX,SPL,AXP209_POWER,SUNXI_EMAC,USB_EHCI,SUNXI_USB_VBUS1_GPIO=SUNXI_GPH(12)"
|
||||
+S:CONFIG_ARM=y
|
||||
+S:CONFIG_TARGET_SUN4I=y
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
CONFIG_SPL=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="I12_TVBOX,SPL,AXP209_POWER,SUNXI_GMAC,MACPWR=SUNXI_GPH(21),USB_EHCI"
|
||||
+S:CONFIG_ARM=y
|
||||
+S:CONFIG_TARGET_SUN7I=y
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
CONFIG_SPL=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="QT840A,SPL,AXP209_POWER,SUNXI_GMAC,MACPWR=SUNXI_GPH(21),USB_EHCI"
|
||||
+S:CONFIG_ARM=y
|
||||
+S:CONFIG_TARGET_SUN7I=y
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
CONFIG_SPL=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="R7DONGLE,SPL,AXP152_POWER"
|
||||
CONFIG_SYS_EXTRA_OPTIONS="R7DONGLE,SPL,AXP152_POWER,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPG(13)"
|
||||
+S:CONFIG_ARM=y
|
||||
+S:CONFIG_TARGET_SUN5I=y
|
||||
|
|
|
|||
|
|
@ -129,6 +129,14 @@ int __weak ahci_link_up(struct ahci_probe_ent *probe_ent, u8 port)
|
|||
return 1;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SUNXI_AHCI
|
||||
/* The sunxi AHCI controller requires this undocumented setup */
|
||||
static void sunxi_dma_init(volatile u8 *port_mmio)
|
||||
{
|
||||
clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400);
|
||||
}
|
||||
#endif
|
||||
|
||||
static int ahci_host_init(struct ahci_probe_ent *probe_ent)
|
||||
{
|
||||
#ifndef CONFIG_SCSI_AHCI_PLAT
|
||||
|
|
@ -213,6 +221,10 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent)
|
|||
msleep(500);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SUNXI_AHCI
|
||||
sunxi_dma_init(port_mmio);
|
||||
#endif
|
||||
|
||||
/* Add the spinup command to whatever mode bits may
|
||||
* already be on in the command register.
|
||||
*/
|
||||
|
|
@ -545,6 +557,10 @@ static int ahci_port_start(u8 port)
|
|||
|
||||
writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
|
||||
|
||||
#ifdef CONFIG_SUNXI_AHCI
|
||||
sunxi_dma_init(port_mmio);
|
||||
#endif
|
||||
|
||||
writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
|
||||
PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
|
||||
PORT_CMD_START, port_mmio + PORT_CMD);
|
||||
|
|
|
|||
|
|
@ -35,6 +35,7 @@ obj-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
|
|||
obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o
|
||||
obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
|
||||
obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o
|
||||
obj-$(CONFIG_USB_EHCI_SUNXI) += ehci-sunxi.o
|
||||
obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
|
||||
obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
|
||||
obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o
|
||||
|
|
|
|||
|
|
@ -0,0 +1,201 @@
|
|||
/*
|
||||
* Copyright (C) 2014 Roman Byshko
|
||||
*
|
||||
* Roman Byshko <rbyshko@gmail.com>
|
||||
*
|
||||
* Based on code from
|
||||
* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/io.h>
|
||||
#include <common.h>
|
||||
#include "ehci.h"
|
||||
|
||||
#define SUNXI_USB1_IO_BASE 0x01c14000
|
||||
#define SUNXI_USB2_IO_BASE 0x01c1c000
|
||||
|
||||
#define SUNXI_USB_PMU_IRQ_ENABLE 0x800
|
||||
#define SUNXI_USB_CSR 0x01c13404
|
||||
#define SUNXI_USB_PASSBY_EN 1
|
||||
|
||||
#define SUNXI_EHCI_AHB_ICHR8_EN (1 << 10)
|
||||
#define SUNXI_EHCI_AHB_INCR4_BURST_EN (1 << 9)
|
||||
#define SUNXI_EHCI_AHB_INCRX_ALIGN_EN (1 << 8)
|
||||
#define SUNXI_EHCI_ULPI_BYPASS_EN (1 << 0)
|
||||
|
||||
static struct sunxi_ehci_hcd {
|
||||
struct usb_hcd *hcd;
|
||||
int usb_rst_mask;
|
||||
int ahb_clk_mask;
|
||||
int gpio_vbus;
|
||||
void *csr;
|
||||
int irq;
|
||||
int id;
|
||||
} sunxi_echi_hcd[] = {
|
||||
{
|
||||
.usb_rst_mask = CCM_USB_CTRL_PHY1_RST,
|
||||
.ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0,
|
||||
.gpio_vbus = CONFIG_SUNXI_USB_VBUS0_GPIO,
|
||||
.csr = (void *)SUNXI_USB_CSR,
|
||||
.irq = 39,
|
||||
.id = 1,
|
||||
},
|
||||
#if (CONFIG_USB_MAX_CONTROLLER_COUNT > 1)
|
||||
{
|
||||
.usb_rst_mask = CCM_USB_CTRL_PHY2_RST,
|
||||
.ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB_EHCI1,
|
||||
.gpio_vbus = CONFIG_SUNXI_USB_VBUS1_GPIO,
|
||||
.csr = (void *)SUNXI_USB_CSR,
|
||||
.irq = 40,
|
||||
.id = 2,
|
||||
}
|
||||
#endif
|
||||
};
|
||||
|
||||
static int enabled_hcd_count;
|
||||
|
||||
static void *get_io_base(int hcd_id)
|
||||
{
|
||||
if (hcd_id == 1)
|
||||
return (void *)SUNXI_USB1_IO_BASE;
|
||||
else if (hcd_id == 2)
|
||||
return (void *)SUNXI_USB2_IO_BASE;
|
||||
else
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void usb_phy_write(struct sunxi_ehci_hcd *sunxi_ehci, int addr,
|
||||
int data, int len)
|
||||
{
|
||||
int j = 0, usbc_bit = 0;
|
||||
void *dest = sunxi_ehci->csr;
|
||||
|
||||
usbc_bit = 1 << (sunxi_ehci->id * 2);
|
||||
for (j = 0; j < len; j++) {
|
||||
/* set the bit address to be written */
|
||||
clrbits_le32(dest, 0xff << 8);
|
||||
setbits_le32(dest, (addr + j) << 8);
|
||||
|
||||
clrbits_le32(dest, usbc_bit);
|
||||
/* set data bit */
|
||||
if (data & 0x1)
|
||||
setbits_le32(dest, 1 << 7);
|
||||
else
|
||||
clrbits_le32(dest, 1 << 7);
|
||||
|
||||
setbits_le32(dest, usbc_bit);
|
||||
|
||||
clrbits_le32(dest, usbc_bit);
|
||||
|
||||
data >>= 1;
|
||||
}
|
||||
}
|
||||
|
||||
static void sunxi_usb_phy_init(struct sunxi_ehci_hcd *sunxi_ehci)
|
||||
{
|
||||
/* The following comments are machine
|
||||
* translated from Chinese, you have been warned!
|
||||
*/
|
||||
|
||||
/* adjust PHY's magnitude and rate */
|
||||
usb_phy_write(sunxi_ehci, 0x20, 0x14, 5);
|
||||
|
||||
/* threshold adjustment disconnect */
|
||||
#ifdef CONFIG_SUN4I
|
||||
usb_phy_write(sunxi_ehci, 0x2a, 3, 2);
|
||||
#else
|
||||
usb_phy_write(sunxi_ehci, 0x2a, 2, 2);
|
||||
#endif
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static void sunxi_usb_passby(struct sunxi_ehci_hcd *sunxi_ehci, int enable)
|
||||
{
|
||||
unsigned long bits = 0;
|
||||
void *addr = get_io_base(sunxi_ehci->id) + SUNXI_USB_PMU_IRQ_ENABLE;
|
||||
|
||||
bits = SUNXI_EHCI_AHB_ICHR8_EN |
|
||||
SUNXI_EHCI_AHB_INCR4_BURST_EN |
|
||||
SUNXI_EHCI_AHB_INCRX_ALIGN_EN |
|
||||
SUNXI_EHCI_ULPI_BYPASS_EN;
|
||||
|
||||
if (enable)
|
||||
setbits_le32(addr, bits);
|
||||
else
|
||||
clrbits_le32(addr, bits);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static void sunxi_ehci_enable(struct sunxi_ehci_hcd *sunxi_ehci)
|
||||
{
|
||||
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
|
||||
|
||||
setbits_le32(&ccm->usb_clk_cfg, sunxi_ehci->usb_rst_mask);
|
||||
setbits_le32(&ccm->ahb_gate0, sunxi_ehci->ahb_clk_mask);
|
||||
|
||||
sunxi_usb_phy_init(sunxi_ehci);
|
||||
|
||||
sunxi_usb_passby(sunxi_ehci, SUNXI_USB_PASSBY_EN);
|
||||
|
||||
gpio_direction_output(sunxi_ehci->gpio_vbus, 1);
|
||||
}
|
||||
|
||||
static void sunxi_ehci_disable(struct sunxi_ehci_hcd *sunxi_ehci)
|
||||
{
|
||||
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
|
||||
|
||||
gpio_direction_output(sunxi_ehci->gpio_vbus, 0);
|
||||
|
||||
sunxi_usb_passby(sunxi_ehci, !SUNXI_USB_PASSBY_EN);
|
||||
|
||||
clrbits_le32(&ccm->ahb_gate0, sunxi_ehci->ahb_clk_mask);
|
||||
clrbits_le32(&ccm->usb_clk_cfg, sunxi_ehci->usb_rst_mask);
|
||||
}
|
||||
|
||||
int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr,
|
||||
struct ehci_hcor **hcor)
|
||||
{
|
||||
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
|
||||
struct sunxi_ehci_hcd *sunxi_ehci = &sunxi_echi_hcd[index];
|
||||
|
||||
/* enable common PHY only once */
|
||||
if (index == 0)
|
||||
setbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
|
||||
|
||||
sunxi_ehci_enable(sunxi_ehci);
|
||||
|
||||
*hccr = get_io_base(sunxi_ehci->id);
|
||||
|
||||
*hcor = (struct ehci_hcor *)((uint32_t) *hccr
|
||||
+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
|
||||
|
||||
debug("sunxi-ehci: init hccr %x and hcor %x hc_length %d\n",
|
||||
(uint32_t)*hccr, (uint32_t)*hcor,
|
||||
(uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
|
||||
|
||||
enabled_hcd_count++;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ehci_hcd_stop(int index)
|
||||
{
|
||||
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
|
||||
struct sunxi_ehci_hcd *sunxi_ehci = &sunxi_echi_hcd[index];
|
||||
|
||||
sunxi_ehci_disable(sunxi_ehci);
|
||||
|
||||
/* disable common PHY only once, for the last enabled hcd */
|
||||
if (enabled_hcd_count == 1)
|
||||
clrbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
|
||||
|
||||
enabled_hcd_count--;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -58,6 +58,10 @@
|
|||
#define PORT_SCR_ERR 0x30 /* SATA phy register: SError */
|
||||
#define PORT_SCR_ACT 0x34 /* SATA phy register: SActive */
|
||||
|
||||
#ifdef CONFIG_SUNXI_AHCI
|
||||
#define PORT_P0DMACR 0x70 /* SUNXI specific "DMA register" */
|
||||
#endif
|
||||
|
||||
/* PORT_IRQ_{STAT,MASK} bits */
|
||||
#define PORT_IRQ_COLD_PRES (1 << 31) /* cold presence detect */
|
||||
#define PORT_IRQ_TF_ERR (1 << 30) /* task file error */
|
||||
|
|
|
|||
|
|
@ -16,6 +16,18 @@
|
|||
|
||||
#define CONFIG_SYS_PROMPT "sun4i# "
|
||||
|
||||
#ifdef CONFIG_USB_EHCI
|
||||
#define CONFIG_USB_EHCI_SUNXI
|
||||
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
||||
#ifndef CONFIG_SUNXI_USB_VBUS0_GPIO
|
||||
#define CONFIG_SUNXI_USB_VBUS0_GPIO SUNXI_GPH(6)
|
||||
#endif
|
||||
#ifndef CONFIG_SUNXI_USB_VBUS1_GPIO
|
||||
#define CONFIG_SUNXI_USB_VBUS1_GPIO SUNXI_GPH(3)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Include common sunxi configuration where most the settings are
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -16,6 +16,11 @@
|
|||
|
||||
#define CONFIG_SYS_PROMPT "sun5i# "
|
||||
|
||||
#ifdef CONFIG_USB_EHCI
|
||||
#define CONFIG_USB_EHCI_SUNXI
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Include common sunxi configuration where most the settings are
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -17,6 +17,25 @@
|
|||
|
||||
#define CONFIG_SYS_PROMPT "sun7i# "
|
||||
|
||||
#ifdef CONFIG_USB_EHCI
|
||||
#define CONFIG_USB_EHCI_SUNXI
|
||||
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
||||
#ifndef CONFIG_SUNXI_USB_VBUS0_GPIO
|
||||
#define CONFIG_SUNXI_USB_VBUS0_GPIO SUNXI_GPH(6)
|
||||
#endif
|
||||
#ifndef CONFIG_SUNXI_USB_VBUS1_GPIO
|
||||
#define CONFIG_SUNXI_USB_VBUS1_GPIO SUNXI_GPH(3)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define CONFIG_ARMV7_VIRT 1
|
||||
#define CONFIG_ARMV7_NONSEC 1
|
||||
#define CONFIG_ARMV7_PSCI 1
|
||||
#define CONFIG_ARMV7_PSCI_NR_CPUS 2
|
||||
#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE
|
||||
#define CONFIG_SYS_CLK_FREQ 24000000
|
||||
|
||||
/*
|
||||
* Include common sunxi configuration where most the settings are
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -57,6 +57,18 @@
|
|||
#define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE
|
||||
#define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */
|
||||
|
||||
#ifdef CONFIG_AHCI
|
||||
#define CONFIG_LIBATA
|
||||
#define CONFIG_SCSI_AHCI
|
||||
#define CONFIG_SCSI_AHCI_PLAT
|
||||
#define CONFIG_SUNXI_AHCI
|
||||
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
|
||||
#define CONFIG_SYS_SCSI_MAX_LUN 1
|
||||
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
|
||||
CONFIG_SYS_SCSI_MAX_LUN)
|
||||
#define CONFIG_CMD_SCSI
|
||||
#endif
|
||||
|
||||
#define CONFIG_CMD_MEMORY
|
||||
#define CONFIG_CMD_SETEXPR
|
||||
|
||||
|
|
@ -203,6 +215,12 @@
|
|||
#define CONFIG_BOOTP_SEND_HOSTNAME
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_EHCI
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
|
||||
#define CONFIG_USB_STORAGE
|
||||
#endif
|
||||
|
||||
#if !defined CONFIG_ENV_IS_IN_MMC && \
|
||||
!defined CONFIG_ENV_IS_IN_NAND && \
|
||||
!defined CONFIG_ENV_IS_IN_FAT && \
|
||||
|
|
|
|||
Loading…
Reference in New Issue