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remarkable-uboot
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Merge git://git.denx.de/u-boot

utp
Stefano Babic 2012-11-10 08:05:54 +01:00
parent bad05afe08 59852d0386
commit 3e4d27b06d
884 changed files with 23667 additions and 29092 deletions
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1
.gitignore vendored
View File

@ -38,6 +38,7 @@
/u-boot.sha1
/u-boot.dis
/u-boot.lds
/u-boot.lst
/u-boot.ubl
/u-boot.ais
/u-boot.dtb

5
CREDITS
View File

@ -79,11 +79,6 @@ N: Oliver Brown
E: obrown@adventnetworks.com
D: Port to the gw8260 board
N: Curt Brune
E: curt@cucy.com
D: Added support for Samsung S3C4510B CPU (ARM7tdmi based SoC)
W: http://www.cucy.com
N: Jonathan De Bruyne
E: jonathan.debruyne@siemens.atea.be
D: Port to Siemens IAD210 board

24
MAINTAINERS
View File

@ -104,8 +104,6 @@ Wolfgang Denk <wd@denx.de>
ARIA MPC5121e
AMX860 MPC860
ETX094 MPC850
FPS850L MPC850
FPS860L MPC860
ICU862 MPC862
@ -116,7 +114,6 @@ Wolfgang Denk <wd@denx.de>
IVMS8 MPC860
IVMS8_128 MPC860
IVMS8_256 MPC860
LANTEC MPC850
LWMON MPC823
R360MPI MPC823
RRvision MPC823
@ -128,7 +125,6 @@ Wolfgang Denk <wd@denx.de>
TQM855L MPC855
TQM860L MPC860
TQM860L_FEC MPC860
c2mon MPC855
hermes MPC860
lwmon MPC823
@ -214,9 +210,7 @@ Siddarth Gore <gores@marvell.com>
Paul Gortmaker <paul.gortmaker@windriver.com>
sbc8349 MPC8349
sbc8540 MPC8540
sbc8548 MPC8548
sbc8560 MPC8560
sbc8641d MPC8641D
Frank Gottschling <fgottschling@eltec.de>
@ -229,7 +223,6 @@ Wolfgang Grandegger <wg@denx.de>
PN62 MPC8240
IPHASE4539 MPC8260
SCM MPC8260
Anatolij Gustschin <agust@denx.de>
@ -545,7 +538,6 @@ Unknown / orphaned boards:
FADS850SAR MPC8xx
FADS860T MPC8xx
GENIETV MPC8xx
IAD210 MPC8xx
MBX MPC8xx
MBX860T MPC8xx
NX823 MPC8xx
@ -573,6 +565,10 @@ Albert ARIBAUD <albert.u.boot@aribaud.net>
edminiv2 ARM926EJS (Orion5x SoC)
Raphael Assenat <raph@8d.com>
eco5pk ARM ARMV7 (AM35x SoC)
Stefano Babic <sbabic@denx.de>
ea20 davinci
@ -586,6 +582,10 @@ Stefano Babic <sbabic@denx.de>
vision2 i.MX51
woodburn i.MX35
Lukasz Dalek <luk0104@gmail.com>
h2200 xscale/pxa
Jason Liu <r64343@freescale.com>
mx53evk i.MX53
@ -901,6 +901,10 @@ Michal Simek <monstr@monstr.eu>
zynq ARM ARMV7 (Zynq SoC)
Lucas Stach <dev@lynxeye.de>
colibri_t20_iris Tegra20 (ARM7 & A9 Dual Core)
Nick Thompson <nick.thompson@gefanuc.com>
da830evm ARM926EJS (DA830/OMAP-L137)
@ -1010,6 +1014,10 @@ Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
armadillo-800eva R8A7740 (RMOBILE SoC)
Pali Rohár <pali.rohar@gmail.com>
nokia_rx51 ARM ARMV7 (OMAP34xx SoC)
-------------------------------------------------------------------------
Unknown / orphaned boards:

2
MAKEALL
View File

@ -640,7 +640,7 @@ build_target() {
fi
if [ $BUILD_MANY == 1 ] ; then
${MAKE} tidy
${MAKE} -s tidy
if [ -s ${LOG_DIR}/${target}.ERR ] ; then
cp ${LOG_DIR}/${target}.ERR ${OUTPUT_PREFIX}/ERR/${target}

63
Makefile
View File

@ -21,10 +21,10 @@
# MA 02111-1307 USA
#
VERSION = 2012
PATCHLEVEL = 10
VERSION = 2013
PATCHLEVEL = 01
SUBLEVEL =
EXTRAVERSION =
EXTRAVERSION = -rc1
ifneq "$(SUBLEVEL)" ""
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
else
@ -260,7 +260,9 @@ LIBS-y += drivers/net/npe/libnpe.o
endif
LIBS-$(CONFIG_OF_EMBED) += dts/libdts.o
LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o
LIBS-y += fs/cramfs/libcramfs.o \
LIBS-y += fs/libfs.o \
fs/cbfs/libcbfs.o \
fs/cramfs/libcramfs.o \
fs/ext4/libext4fs.o \
fs/fat/libfat.o \
fs/fdos/libfdos.o \
@ -514,16 +516,17 @@ $(obj)u-boot.spr: $(obj)u-boot.img $(obj)spl/u-boot-spl.bin
ifeq ($(SOC),tegra20)
ifeq ($(CONFIG_OF_SEPARATE),y)
$(obj)u-boot-dtb-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin $(obj)u-boot.dtb
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_TEXT_BASE) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin $(obj)u-boot.dtb > $@
rm $(obj)spl/u-boot-spl-pad.bin
nodtb=dtb
dtbfile=$(obj)u-boot.dtb
else
$(obj)u-boot-nodtb-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_TEXT_BASE) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@
rm $(obj)spl/u-boot-spl-pad.bin
nodtb=nodtb
dtbfile=
endif
$(obj)u-boot-$(nodtb)-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin $(dtbfile)
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_TEXT_BASE) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin $(dtbfile) > $@
rm $(obj)spl/u-boot-spl-pad.bin
endif
ifeq ($(CONFIG_SANDBOX),y)
@ -533,9 +536,10 @@ GEN_UBOOT = \
$(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map -o u-boot
else
GEN_UBOOT = \
UNDEF_SYM=`$(OBJDUMP) -x $(LIBBOARD) $(LIBS) | \
sed -n -e 's/.*\($(SYM_PREFIX)__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
cd $(LNDIR) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) $$UNDEF_SYM $(__OBJS) \
UNDEF_LST=`$(OBJDUMP) -x $(LIBBOARD) $(LIBS) | \
sed -n -e 's/.*\($(SYM_PREFIX)_u_boot_list_.*\)/-u\1/p'|sort|uniq`;\
cd $(LNDIR) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) \
$$UNDEF_LST $(__OBJS) \
--start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \
-Map u-boot.map -o u-boot
endif
@ -568,8 +572,12 @@ $(SUBDIR_EXAMPLES): $(obj)u-boot
$(LDSCRIPT): depend
$(MAKE) -C $(dir $@) $(notdir $@)
$(obj)u-boot.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
# The following line expands into whole rule which generates u-boot.lst,
# the file containing u-boots LG-array linker section. This is included into
# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
$(eval $(call make_u_boot_list, $(obj)include/u-boot.lst, $(LIBBOARD) $(LIBS)))
$(obj)u-boot.lds: $(LDSCRIPT) $(obj)include/u-boot.lst
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$< >$@
nand_spl: $(TIMESTAMP_FILE) $(VERSION_FILE) depend
$(MAKE) -C nand_spl/board/$(BOARDDIR) all
@ -748,20 +756,6 @@ $(obj).boards.depend: boards.cfg
lcname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\L\1/')
ucname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\U\1/')
#========================================================================
# ARM
#========================================================================
SX1_stdout_serial_config \
SX1_config: unconfig
@mkdir -p $(obj)include
@if [ "$(findstring _stdout_serial_, $@)" ] ; then \
echo "#undef CONFIG_STDOUT_USBTTY" >> $(obj)include/config.h ; \
else \
echo "#define CONFIG_STDOUT_USBTTY" >> $(obj)include/config.h ; \
fi;
@$(MKCONFIG) -n $@ SX1 arm arm925t sx1
#########################################################################
## ARM1176 Systems
#########################################################################
@ -808,6 +802,7 @@ clean:
$(obj)board/matrix_vision/*/bootscript.img \
$(obj)board/voiceblue/eeprom \
$(obj)u-boot.lds \
$(obj)include/u-boot.lst \
$(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs] \
$(obj)arch/blackfin/cpu/init.{lds,elf}
@rm -f $(obj)include/bmp_logo.h
@ -841,8 +836,10 @@ clobber: tidy
@rm -f $(obj)u-boot.dtb
@rm -f $(obj)u-boot.sb
@rm -f $(obj)u-boot.spr
@rm -f $(obj)nand_spl/{u-boot.lds,u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map,System.map}
@rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.lds,u-boot-spl.map}
@rm -f $(obj)nand_spl/{u-boot.{lds,lst},System.map}
@rm -f $(obj)nand_spl/{u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map}
@rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.map}
@rm -f $(obj)spl/{u-boot-spl.lds,u-boot.lst}
@rm -f $(obj)MLO
@rm -f $(obj)SPL
@rm -f $(obj)tools/xway-swap-bytes

38
README
View File

@ -363,6 +363,12 @@ The following options need to be configured:
ICache only when Code runs from RAM.
- 85xx CPU Options:
CONFIG_SYS_PPC64
Specifies that the core is a 64-bit PowerPC implementation (implements
the "64" category of the Power ISA). This is necessary for ePAPR
compliance, among other possible reasons.
CONFIG_SYS_FSL_TBCLK_DIV
Defines the core time base clock divider ratio compared to the
@ -655,6 +661,10 @@ The following options need to be configured:
additional board info beside
the logo
When CONFIG_CFB_CONSOLE_ANSI is defined, console will support
a limited number of ANSI escape sequences (cursor control,
erase functions and limited graphics rendition control).
When CONFIG_CFB_CONSOLE is defined, video console is
default i/o. Serial console can be forced with
environment 'console=serial'.
@ -801,9 +811,11 @@ The following options need to be configured:
CONFIG_CMD_EEPROM * EEPROM read/write support
CONFIG_CMD_ELF * bootelf, bootvx
CONFIG_CMD_EXPORTENV * export the environment
CONFIG_CMD_EXT2 * ext2 command support
CONFIG_CMD_EXT4 * ext4 command support
CONFIG_CMD_SAVEENV saveenv
CONFIG_CMD_FDC * Floppy Disk Support
CONFIG_CMD_FAT * FAT partition support
CONFIG_CMD_FAT * FAT command support
CONFIG_CMD_FDOS * Dos diskette Support
CONFIG_CMD_FLASH flinfo, erase, protect
CONFIG_CMD_FPGA FPGA device initialization support
@ -1033,6 +1045,9 @@ The following options need to be configured:
devices.
CONFIG_SYS_SCSI_SYM53C8XX_CCF to fix clock timing (80Mhz)
The environment variable 'scsidevs' is set to the number of
SCSI devices found during the last scan.
- NETWORK Support (PCI):
CONFIG_E1000
Support for Intel 8254x/8257x gigabit chips.
@ -1084,7 +1099,7 @@ The following options need to be configured:
CONFIG_CALXEDA_XGMAC
Support for the Calxeda XGMAC device
CONFIG_DRIVER_LAN91C96
CONFIG_LAN91C96
Support for SMSC's LAN91C96 chips.
CONFIG_LAN91C96_BASE
@ -1094,7 +1109,7 @@ The following options need to be configured:
CONFIG_LAN91C96_USE_32_BIT
Define this to enable 32 bit addressing
CONFIG_DRIVER_SMC91111
CONFIG_SMC91111
Support for SMSC's LAN91C111 chip
CONFIG_SMC91111_BASE
@ -1316,6 +1331,13 @@ The following options need to be configured:
This will also enable the command "fatwrite" enabling the
user to write files to FAT.
CBFS (Coreboot Filesystem) support
CONFIG_CMD_CBFS
Define this to enable support for reading from a Coreboot
filesystem. Available commands are cbfsinit, cbfsinfo, cbfsls
and cbfsload.
- Keyboard Support:
CONFIG_ISA_KEYBOARD
@ -2169,8 +2191,8 @@ The following options need to be configured:
following board configurations are known to be
"pRAM-clean":
ETX094, IVMS8, IVML24, SPD8xx, TQM8xxL,
HERMES, IP860, RPXlite, LWMON, LANTEC,
IVMS8, IVML24, SPD8xx, TQM8xxL,
HERMES, IP860, RPXlite, LWMON,
FLAGADM, TQM8260
- Error Recovery:
@ -2296,6 +2318,12 @@ The following options need to be configured:
- CONFIG_SYS_VENDOR
- CONFIG_SYS_SOC
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
Define this in order to add variables describing certain
run-time determined information about the hardware to the
environment. These will be named board_name, board_rev.
- DataFlash Support:
CONFIG_HAS_DATAFLASH

2
arch/arm/cpu/arm1176/tnetv107x/Makefile
View File

@ -21,7 +21,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
COBJS += aemif.o clock.o init.o mux.o timer.o wdt.o
COBJS += aemif.o clock.o init.o mux.o timer.o
SOBJS += lowlevel_init.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)

4
arch/arm/cpu/arm1176/tnetv107x/clock.c
View File

@ -168,10 +168,6 @@ static unsigned long pll_div_mask[] = { 0x01ff, 0x00ff, 0x00ff };
#define tdm_extra_clk {TDM_PLL, 1}
#define tdm1_clk {TDM_PLL, 2}
/* Optimization barrier */
#define barrier() \
__asm__ __volatile__("mov r0, r0\n" : : : "memory");
static const struct lpsc_map lpsc_clk_map[] = {
[TNETV107X_LPSC_ARM] = sys_arm1176_clk,
[TNETV107X_LPSC_GEM] = sys_dsp_clk,

32
arch/arm/cpu/arm720t/cpu.c
View File

@ -27,34 +27,12 @@
*/
/*
* CPU specific code
* cleanup_before_linux() - Prepare the CPU to jump to Linux
*
* This function is called just before we call Linux, it
* prepares the processor for linux
*/
#include <common.h>
#include <command.h>
#include <clps7111.h>
#include <asm/hardware.h>
#include <asm/system.h>
int cleanup_before_linux (void)
int cleanup_before_linux(void)
{
/*
* this function is called just before we call linux
* it prepares the processor for linux
*
* we turn off caches etc ...
* and we set the CPU-speed to 73 MHz - see start.S for details
*/
#if defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) || defined(CONFIG_LPC2292)
disable_interrupts ();
/* Nothing more needed */
#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
/* No cleanup before linux for IntegratorAP/CM720T as yet */
#elif defined(CONFIG_TEGRA)
/* No cleanup before linux for tegra as yet */
#else
#error No cleanup_before_linux() defined for this CPU type
#endif
return 0;
}

251
arch/arm/cpu/arm720t/interrupts.c
View File

@ -27,266 +27,23 @@
*/
#include <common.h>
#include <clps7111.h>
#include <asm/proc-armv/ptrace.h>
#include <asm/hardware.h>
#ifndef CONFIG_NETARM
/* we always count down the max. */
#define TIMER_LOAD_VAL 0xffff
/* macro to read the 16 bit timer */
#define READ_TIMER (IO_TC1D & 0xffff)
#ifdef CONFIG_LPC2292
#undef READ_TIMER
#define READ_TIMER (0xFFFFFFFF - GET32(T0TC))
#endif
#else
#define IRQEN (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_INTR_ENABLE))
#define TM2CTRL (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_CONTROL))
#define TM2STAT (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_STATUS))
#define TIMER_LOAD_VAL NETARM_GEN_TSTAT_CTC_MASK
#define READ_TIMER (TM2STAT & NETARM_GEN_TSTAT_CTC_MASK)
#endif
#ifdef CONFIG_S3C4510B
/* require interrupts for the S3C4510B */
# ifndef CONFIG_USE_IRQ
# error CONFIG_USE_IRQ _must_ be defined when using CONFIG_S3C4510B
# else
static struct _irq_handler IRQ_HANDLER[N_IRQS];
# endif
#endif /* CONFIG_S3C4510B */
#ifdef CONFIG_USE_IRQ
void do_irq (struct pt_regs *pt_regs)
{
#if defined(CONFIG_S3C4510B)
unsigned int pending;
while ( (pending = GET_REG( REG_INTOFFSET)) != 0x54) { /* sentinal value for no pending interrutps */
IRQ_HANDLER[pending>>2].m_func( IRQ_HANDLER[pending>>2].m_data);
/* clear pending interrupt */
PUT_REG( REG_INTPEND, (1<<(pending>>2)));
}
#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
/* No do_irq() for IntegratorAP/CM720T as yet */
#elif defined(CONFIG_LPC2292)
void (*pfnct)(void);
pfnct = (void (*)(void))VICVectAddr;
(*pfnct)();
#else
#error do_irq() not defined for this CPU type
#endif
}
#endif
#ifdef CONFIG_S3C4510B
static void default_isr( void *data) {
printf ("default_isr(): called for IRQ %d\n", (int)data);
}
static void timer_isr( void *data) {
unsigned int *pTime = (unsigned int *)data;
(*pTime)++;
if ( !(*pTime % (CONFIG_SYS_HZ/4))) {
/* toggle LED 0 */
PUT_REG( REG_IOPDATA, GET_REG(REG_IOPDATA) ^ 0x1);
}
}
#endif
#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
/* Use IntegratorAP routines in board/integratorap.c */
#else
#if defined(CONFIG_TEGRA)
static ulong timestamp;
static ulong lastdec;
#if defined(CONFIG_USE_IRQ) && defined(CONFIG_S3C4510B)
int arch_interrupt_init (void)
int timer_init (void)
{
int i;
/* install default interrupt handlers */
for ( i = 0; i < N_IRQS; i++) {
IRQ_HANDLER[i].m_data = (void *)i;
IRQ_HANDLER[i].m_func = default_isr;
}
/* configure interrupts for IRQ mode */
PUT_REG( REG_INTMODE, 0x0);
/* clear any pending interrupts */
PUT_REG( REG_INTPEND, 0x1FFFFF);
/* No timer routines for tegra as yet */
lastdec = 0;
/* install interrupt handler for timer */
IRQ_HANDLER[INT_TIMER0].m_data = (void *)&timestamp;
IRQ_HANDLER[INT_TIMER0].m_func = timer_isr;
timestamp = 0;
return 0;
}
#endif
int timer_init (void)
{
#if defined(CONFIG_NETARM)
/* disable all interrupts */
IRQEN = 0;
/* operate timer 2 in non-prescale mode */
TM2CTRL = ( NETARM_GEN_TIMER_SET_HZ(CONFIG_SYS_HZ) |
NETARM_GEN_TCTL_ENABLE |
NETARM_GEN_TCTL_INIT_COUNT(TIMER_LOAD_VAL));
/* set timer 2 counter */
lastdec = TIMER_LOAD_VAL;
#elif defined(CONFIG_S3C4510B)
/* configure free running timer 0 */
PUT_REG( REG_TMOD, 0x0);
/* Stop timer 0 */
CLR_REG( REG_TMOD, TM0_RUN);
/* Configure for interval mode */
CLR_REG( REG_TMOD, TM1_TOGGLE);
/*
* Load Timer data register with count down value.
* count_down_val = CONFIG_SYS_SYS_CLK_FREQ/CONFIG_SYS_HZ
*/
PUT_REG( REG_TDATA0, (CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ));
/*
* Enable global interrupt
* Enable timer0 interrupt
*/
CLR_REG( REG_INTMASK, ((1<<INT_GLOBAL) | (1<<INT_TIMER0)));
/* Start timer */
SET_REG( REG_TMOD, TM0_RUN);
#elif defined(CONFIG_LPC2292)
PUT32(T0IR, 0); /* disable all timer0 interrupts */
PUT32(T0TCR, 0); /* disable timer0 */
PUT32(T0PR, CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ);
PUT32(T0MCR, 0);
PUT32(T0TC, 0);
PUT32(T0TCR, 1); /* enable timer0 */
#elif defined(CONFIG_TEGRA)
/* No timer routines for tegra as yet */
lastdec = 0;
#else
#error No timer_init() defined for this CPU type
#endif
timestamp = 0;
return (0);
}
#endif /* ! IntegratorAP */
/*
* timer without interrupts
*/
#if defined(CONFIG_NETARM) || defined(CONFIG_LPC2292)
ulong get_timer (ulong base)
{
return get_timer_masked () - base;
}
void __udelay (unsigned long usec)
{
ulong tmo;
tmo = usec / 1000;
tmo *= CONFIG_SYS_HZ;
tmo /= 1000;
tmo += get_timer (0);
while (get_timer_masked () < tmo)
#ifdef CONFIG_LPC2292
/* GJ - not sure whether this is really needed or a misunderstanding */
__asm__ __volatile__(" nop");
#else
/*NOP*/;
#endif
}
ulong get_timer_masked (void)
{
ulong now = READ_TIMER;
if (lastdec >= now) {
/* normal mode */
timestamp += lastdec - now;
} else {
/* we have an overflow ... */
timestamp += lastdec + TIMER_LOAD_VAL - now;
}
lastdec = now;
return timestamp;
}
void udelay_masked (unsigned long usec)
{
ulong tmo;
ulong endtime;
signed long diff;
if (usec >= 1000) {
tmo = usec / 1000;
tmo *= CONFIG_SYS_HZ;
tmo /= 1000;
} else {
tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000*1000);
}
endtime = get_timer_masked () + tmo;
do {
ulong now = get_timer_masked ();
diff = endtime - now;
} while (diff >= 0);
}
#elif defined(CONFIG_S3C4510B)
ulong get_timer (ulong base)
{
return timestamp - base;
}
void __udelay (unsigned long usec)
{
u32 ticks;
ticks = (usec * CONFIG_SYS_HZ) / 1000000;
ticks += get_timer (0);
while (get_timer (0) < ticks)
/*NOP*/;
}
#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
/* No timer routines for IntegratorAP/CM720T as yet */
#elif defined(CONFIG_TEGRA)
/* No timer routines for tegra as yet */
#else
#error Timer routines not defined for this CPU type
#endif

50
arch/arm/cpu/arm720t/lpc2292/Makefile
View File

@ -1,50 +0,0 @@
#
# (C) Copyright 2000-2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
COBJS = flash.o mmc.o mmc_hw.o spi.o
SOBJS = $(obj)iap_entry.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
all: $(obj).depend $(LIB)
$(LIB): $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
# this MUST be compiled as thumb code!
$(SOBJS):
$(CC) $(AFLAGS) -march=armv4t -c -o $(SOBJS) iap_entry.S
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

249
arch/arm/cpu/arm720t/lpc2292/flash.c
View File

@ -1,249 +0,0 @@
/*
* (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com>
*
* Modified to remove all but the IAP-command related code by
* Gary Jennejohn <garyj@denx.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/hardware.h>
/* IAP commands use 32 bytes at the top of CPU internal sram, we
use 512 bytes below that */
#define COPY_BUFFER_LOCATION 0x40003de0
#define IAP_LOCATION 0x7ffffff1
#define IAP_CMD_PREPARE 50
#define IAP_CMD_COPY 51
#define IAP_CMD_ERASE 52
#define IAP_CMD_CHECK 53
#define IAP_CMD_ID 54
#define IAP_CMD_VERSION 55
#define IAP_CMD_COMPARE 56
#define IAP_RET_CMD_SUCCESS 0
static unsigned long command[5];
static unsigned long result[2];
extern void iap_entry(unsigned long * command, unsigned long * result);
/*-----------------------------------------------------------------------
*
*/
static int get_flash_sector(flash_info_t * info, ulong flash_addr)
{
int i;
for(i = 1; i < (info->sector_count); i++) {
if (flash_addr < (info->start[i]))
break;
}
return (i-1);
}
/*-----------------------------------------------------------------------
* This function assumes that flash_addr is aligned on 512 bytes boundary
* in flash. This function also assumes that prepare have been called
* for the sector in question.
*/
int lpc2292_copy_buffer_to_flash(flash_info_t * info, ulong flash_addr)
{
int first_sector;
int last_sector;
first_sector = get_flash_sector(info, flash_addr);
last_sector = get_flash_sector(info, flash_addr + 512 - 1);
/* prepare sectors for write */
command[0] = IAP_CMD_PREPARE;
command[1] = first_sector;
command[2] = last_sector;
iap_entry(command, result);
if (result[0] != IAP_RET_CMD_SUCCESS) {
printf("IAP prepare failed\n");
return ERR_PROG_ERROR;
}
command[0] = IAP_CMD_COPY;
command[1] = flash_addr;
command[2] = COPY_BUFFER_LOCATION;
command[3] = 512;
command[4] = CONFIG_SYS_SYS_CLK_FREQ >> 10;
iap_entry(command, result);
if (result[0] != IAP_RET_CMD_SUCCESS) {
printf("IAP copy failed\n");
return 1;
}
return 0;
}
/*-----------------------------------------------------------------------
*/
int lpc2292_flash_erase (flash_info_t * info, int s_first, int s_last)
{
int flag;
int prot;
int sect;
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot)
return ERR_PROTECTED;
flag = disable_interrupts();
printf ("Erasing %d sectors starting at sector %2d.\n"
"This make take some time ... ",
s_last - s_first + 1, s_first);
command[0] = IAP_CMD_PREPARE;
command[1] = s_first;
command[2] = s_last;
iap_entry(command, result);
if (result[0] != IAP_RET_CMD_SUCCESS) {
printf("IAP prepare failed\n");
return ERR_PROTECTED;
}
command[0] = IAP_CMD_ERASE;
command[1] = s_first;
command[2] = s_last;
command[3] = CONFIG_SYS_SYS_CLK_FREQ >> 10;
iap_entry(command, result);
if (result[0] != IAP_RET_CMD_SUCCESS) {
printf("IAP erase failed\n");
return ERR_PROTECTED;
}
if (flag)
enable_interrupts();
return ERR_OK;
}
int lpc2292_write_buff (flash_info_t * info, uchar * src, ulong addr,
ulong cnt)
{
int first_copy_size;
int last_copy_size;
int first_block;
int last_block;
int nbr_mid_blocks;
uchar memmap_value;
ulong i;
uchar* src_org;
uchar* dst_org;
int ret = ERR_OK;
src_org = src;
dst_org = (uchar*)addr;
first_block = addr / 512;
last_block = (addr + cnt) / 512;
nbr_mid_blocks = last_block - first_block - 1;
first_copy_size = 512 - (addr % 512);
last_copy_size = (addr + cnt) % 512;
debug("\ncopy first block: (1) %lX -> %lX 0x200 bytes, "
"(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX 0x200 bytes\n",
(ulong)(first_block * 512),
(ulong)COPY_BUFFER_LOCATION,
(ulong)src,
(ulong)(COPY_BUFFER_LOCATION + 512 - first_copy_size),
first_copy_size,
(ulong)COPY_BUFFER_LOCATION,
(ulong)(first_block * 512));
/* copy first block */
memcpy((void*)COPY_BUFFER_LOCATION,
(void*)(first_block * 512), 512);
memcpy((void*)(COPY_BUFFER_LOCATION + 512 - first_copy_size),
src, first_copy_size);
lpc2292_copy_buffer_to_flash(info, first_block * 512);
src += first_copy_size;
addr += first_copy_size;
/* copy middle blocks */
for (i = 0; i < nbr_mid_blocks; i++) {
debug("copy middle block: %lX -> %lX 512 bytes, "
"%lX -> %lX 512 bytes\n",
(ulong)src,
(ulong)COPY_BUFFER_LOCATION,
(ulong)COPY_BUFFER_LOCATION,
(ulong)addr);
memcpy((void*)COPY_BUFFER_LOCATION, src, 512);
lpc2292_copy_buffer_to_flash(info, addr);
src += 512;
addr += 512;
}
if (last_copy_size > 0) {
debug("copy last block: (1) %lX -> %lX 0x200 bytes, "
"(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX x200 bytes\n",
(ulong)(last_block * 512),
(ulong)COPY_BUFFER_LOCATION,
(ulong)src,
(ulong)(COPY_BUFFER_LOCATION),
last_copy_size,
(ulong)COPY_BUFFER_LOCATION,
(ulong)addr);
/* copy last block */
memcpy((void*)COPY_BUFFER_LOCATION,
(void*)(last_block * 512), 512);
memcpy((void*)COPY_BUFFER_LOCATION,
src, last_copy_size);
lpc2292_copy_buffer_to_flash(info, addr);
}
/* verify write */
memmap_value = GET8(MEMMAP);
disable_interrupts();
PUT8(MEMMAP, 01); /* we must make sure that initial 64
bytes are taken from flash when we
do the compare */
for (i = 0; i < cnt; i++) {
if (*dst_org != *src_org){
printf("Write failed. Byte %lX differs\n", i);
ret = ERR_PROG_ERROR;
break;
}
dst_org++;
src_org++;
}
PUT8(MEMMAP, memmap_value);
enable_interrupts();
return ret;
}

7
arch/arm/cpu/arm720t/lpc2292/iap_entry.S
View File

@ -1,7 +0,0 @@
IAP_ADDRESS: .word 0x7FFFFFF1
.globl iap_entry
iap_entry:
ldr r2, IAP_ADDRESS
bx r2
mov pc, lr

131
arch/arm/cpu/arm720t/lpc2292/mmc.c
View File

@ -1,131 +0,0 @@
/*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <mmc.h>
#include <asm/errno.h>
#include <asm/arch/hardware.h>
#include <part.h>
#include <fat.h>
#include "mmc_hw.h"
#include <asm/arch/spi.h>
#ifdef CONFIG_MMC
#undef MMC_DEBUG
static block_dev_desc_t mmc_dev;
/* these are filled out by a call to mmc_hw_get_parameters */
static int hw_size; /* in kbytes */
static int hw_nr_sects;
static int hw_sect_size; /* in bytes */
block_dev_desc_t * mmc_get_dev(int dev)
{
return (block_dev_desc_t *)(&mmc_dev);
}
unsigned long mmc_block_read(int dev,
unsigned long start,
lbaint_t blkcnt,
void *buffer)
{
unsigned long rc = 0;
unsigned char *p = (unsigned char *)buffer;
unsigned long i;
unsigned long addr = start;
#ifdef MMC_DEBUG
printf("mmc_block_read: start=%lu, blkcnt=%lu\n", start,
(unsigned long)blkcnt);
#endif
for(i = 0; i < (unsigned long)blkcnt; i++) {
#ifdef MMC_DEBUG
printf("mmc_read_sector: addr=%lu, buffer=%p\n", addr, p);
#endif
(void)mmc_read_sector(addr, p);
rc++;
addr++;
p += hw_sect_size;
}
return rc;
}
/*-----------------------------------------------------------------------------
* Read hardware paramterers (sector size, size, number of sectors)
*/
static int mmc_hw_get_parameters(void)
{
unsigned char csddata[16];
unsigned int sizemult;
unsigned int size;
mmc_read_csd(csddata);
hw_sect_size = 1<<(csddata[5] & 0x0f);
size = ((csddata[6]&0x03)<<10)+(csddata[7]<<2)+(csddata[8]&0xc0);
sizemult = ((csddata[10] & 0x80)>>7)+((csddata[9] & 0x03)<<1);
hw_nr_sects = (size+1)*(1<<(sizemult+2));
hw_size = hw_nr_sects*hw_sect_size/1024;
#ifdef MMC_DEBUG
printf("mmc_hw_get_parameters: hw_sect_size=%d, hw_nr_sects=%d, "
"hw_size=%d\n", hw_sect_size, hw_nr_sects, hw_size);
#endif
return 0;
}
int mmc_legacy_init(int verbose)
{
int ret = -ENODEV;
if (verbose)
printf("mmc_legacy_init\n");
spi_init();
/* this meeds to be done twice */
mmc_hw_init();
udelay(1000);
mmc_hw_init();
mmc_hw_get_parameters();
mmc_dev.if_type = IF_TYPE_MMC;
mmc_dev.part_type = PART_TYPE_DOS;
mmc_dev.dev = 0;
mmc_dev.lun = 0;
mmc_dev.type = 0;
mmc_dev.blksz = hw_sect_size;
mmc_dev.lba = hw_nr_sects;
sprintf((char*)mmc_dev.vendor, "Unknown vendor");
sprintf((char*)mmc_dev.product, "Unknown product");
sprintf((char*)mmc_dev.revision, "N/A");
mmc_dev.removable = 0; /* should be true??? */
mmc_dev.block_read = mmc_block_read;
fat_register_device(&mmc_dev, 1);
ret = 0;
return ret;
}
#endif /* CONFIG_MMC */

233
arch/arm/cpu/arm720t/lpc2292/mmc_hw.c
View File

@ -1,233 +0,0 @@
/*
This code was original written by Ulrich Radig and modified by
Embedded Artists AB (www.embeddedartists.com).
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <asm/arch/hardware.h>
#include <asm/arch/spi.h>
#define MMC_Enable() PUT32(IO1CLR, 1l << 22)
#define MMC_Disable() PUT32(IO1SET, 1l << 22)
#define mmc_spi_cfg() spi_set_clock(8); spi_set_cfg(0, 1, 0);
static unsigned char Write_Command_MMC (unsigned char *CMD);
static void MMC_Read_Block(unsigned char *CMD, unsigned char *Buffer,
unsigned short int Bytes);
/* initialize the hardware */
int mmc_hw_init(void)
{
unsigned long a;
unsigned short int Timeout = 0;
unsigned char b;
unsigned char CMD[] = {0x40, 0x00, 0x00, 0x00, 0x00, 0x95};
/* set-up GPIO and SPI */
(*((volatile unsigned long *)PINSEL2)) &= ~(1l << 3); /* clear bit 3 */
(*((volatile unsigned long *)IO1DIR)) |= (1l << 22); /* set bit 22 (output) */
MMC_Disable();
spi_lock();
spi_set_clock(248);
spi_set_cfg(0, 1, 0);
MMC_Enable();
/* waste some time */
for(a=0; a < 20000; a++)
asm("nop");
/* Put the MMC/SD-card into SPI-mode */
for (b = 0; b < 10; b++) /* Sends min 74+ clocks to the MMC/SD-card */
spi_write(0xff);
/* Sends command CMD0 to MMC/SD-card */
while (Write_Command_MMC(CMD) != 1) {
if (Timeout++ > 200) {
MMC_Disable();
spi_unlock();
return(1); /* Abort with command 1 (return 1) */
}
}
/* Sends Command CMD1 an MMC/SD-card */
Timeout = 0;
CMD[0] = 0x41;/* Command 1 */
CMD[5] = 0xFF;
while (Write_Command_MMC(CMD) != 0) {
if (Timeout++ > 200) {
MMC_Disable();
spi_unlock();
return (2); /* Abort with command 2 (return 2) */
}
}
MMC_Disable();
spi_unlock();
return 0;
}
/* ############################################################################
Sends a command to the MMC/SD-card
######################################################################### */
static unsigned char Write_Command_MMC (unsigned char *CMD)
{
unsigned char a, tmp = 0xff;
unsigned short int Timeout = 0;
MMC_Disable();
spi_write(0xFF);
MMC_Enable();
for (a = 0; a < 0x06; a++)
spi_write(*CMD++);
while (tmp == 0xff) {
tmp = spi_read();
if (Timeout++ > 5000)
break;
}
return (tmp);
}
/* ############################################################################
Routine to read the CID register from the MMC/SD-card (16 bytes)
######################################################################### */
void MMC_Read_Block(unsigned char *CMD, unsigned char *Buffer, unsigned short
int Bytes)
{
unsigned short int a;
spi_lock();
mmc_spi_cfg();
MMC_Enable();
if (Write_Command_MMC(CMD) != 0) {
MMC_Disable();
spi_unlock();
return;
}
while (spi_read() != 0xfe) {};
for (a = 0; a < Bytes; a++)
*Buffer++ = spi_read();
/* Read the CRC-byte */
spi_read(); /* CRC - byte is discarded */
spi_read(); /* CRC - byte is discarded */
/* set MMC_Chip_Select to high (MMC/SD-card Inaktiv) */
MMC_Disable();
spi_unlock();
return;
}
/* ############################################################################
Routine to read a block (512 bytes) from the MMC/SD-card
######################################################################### */
unsigned char mmc_read_sector (unsigned long addr,unsigned char *Buffer)
{
/* Command 16 to read aBlocks from the MMC/SD - caed */
unsigned char CMD[] = {0x51,0x00,0x00,0x00,0x00,0xFF};
/* The address on the MMC/SD-card is in bytes,
addr is transformed from blocks to bytes and the result is
placed into the command */
addr = addr << 9; /* addr = addr * 512 */
CMD[1] = ((addr & 0xFF000000) >> 24);
CMD[2] = ((addr & 0x00FF0000) >> 16);
CMD[3] = ((addr & 0x0000FF00) >> 8 );
MMC_Read_Block(CMD, Buffer, 512);
return (0);
}
/* ############################################################################
Routine to write a block (512 byte) to the MMC/SD-card
######################################################################### */
unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer)
{
unsigned char tmp, a;
unsigned short int b;
/* Command 24 to write a block to the MMC/SD - card */
unsigned char CMD[] = {0x58, 0x00, 0x00, 0x00, 0x00, 0xFF};
/* The address on the MMC/SD-card is in bytes,
addr is transformed from blocks to bytes and the result is
placed into the command */
addr = addr << 9; /* addr = addr * 512 */
CMD[1] = ((addr & 0xFF000000) >> 24);
CMD[2] = ((addr & 0x00FF0000) >> 16);
CMD[3] = ((addr & 0x0000FF00) >> 8 );
spi_lock();
mmc_spi_cfg();
MMC_Enable();
/* Send command CMD24 to the MMC/SD-card (Write 1 Block/512 Bytes) */
tmp = Write_Command_MMC(CMD);
if (tmp != 0) {
MMC_Disable();
spi_unlock();
return(tmp);
}
/* Do a short delay and send a clock-pulse to the MMC/SD-card */
for (a = 0; a < 100; a++)
spi_read();
/* Send a start byte to the MMC/SD-card */
spi_write(0xFE);
/* Write the block (512 bytes) to the MMC/SD-card */
for (b = 0; b < 512; b++)
spi_write(*Buffer++);
/* write the CRC-Byte */
spi_write(0xFF); /* write a dummy CRC */
spi_write(0xFF); /* CRC code is not used */
/* Wait for MMC/SD-card busy */
while (spi_read() != 0xff) {};
/* set MMC_Chip_Select to high (MMC/SD-card inactive) */
MMC_Disable();
spi_unlock();
return (0);
}
/* #########################################################################
Routine to read the CSD register from the MMC/SD-card (16 bytes)
######################################################################### */
unsigned char mmc_read_csd (unsigned char *Buffer)
{
/* Command to read the CSD register */
unsigned char CMD[] = {0x49, 0x00, 0x00, 0x00, 0x00, 0xFF};
MMC_Read_Block(CMD, Buffer, 16);
return (0);
}

29
arch/arm/cpu/arm720t/lpc2292/mmc_hw.h
View File

@ -1,29 +0,0 @@
/*
This module implements a linux character device driver for the 24c256 chip.
Copyright (C) 2006 Embedded Artists AB (www.embeddedartists.com)
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _MMC_HW_
#define _MMC_HW_
unsigned char mmc_read_csd(unsigned char *Buffer);
unsigned char mmc_read_sector (unsigned long addr,
unsigned char *Buffer);
unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer);
int mmc_hw_init(void);
#endif /* _MMC_HW_ */

40
arch/arm/cpu/arm720t/lpc2292/spi.c
View File

@ -1,40 +0,0 @@
/*
This module implements an interface to the SPI on the lpc22xx.
Copyright (C) 2006 Embedded Artists AB (www.embeddedartists.com)
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <asm/errno.h>
#include <asm/arch/hardware.h>
#include <asm/arch/spi.h>
unsigned long spi_flags;
unsigned char spi_idle = 0x00;
int spi_init(void)
{
unsigned long pinsel0_value;
/* activate spi pins */
pinsel0_value = GET32(PINSEL0);
pinsel0_value &= ~(0xFFl << 8);
pinsel0_value |= (0x55l << 8);
PUT32(PINSEL0, pinsel0_value);
return 0;
}

45
arch/arm/cpu/arm720t/s3c4510b/Makefile
View File

@ -1,45 +0,0 @@
#
# (C) Copyright 2000-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
COBJS-y += cache.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

86
arch/arm/cpu/arm720t/s3c4510b/cache.c
View File

@ -1,86 +0,0 @@
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/hardware.h>
void icache_enable (void)
{
s32 i;
/* disable all cache bits */
CLR_REG( REG_SYSCFG, 0x3F);
/* 8KB cache, write enable */
SET_REG( REG_SYSCFG, CACHE_WRITE_BUFF | CACHE_MODE_01);
/* clear TAG RAM bits */
for ( i = 0; i < 256; i++)
PUT_REG( CACHE_TAG_RAM + 4*i, 0x00000000);
/* clear SET0 RAM */
for(i=0; i < 1024; i++)
PUT_REG( CACHE_SET0_RAM + 4*i, 0x00000000);
/* clear SET1 RAM */
for(i=0; i < 1024; i++)
PUT_REG( CACHE_SET1_RAM + 4*i, 0x00000000);
/* enable cache */
SET_REG( REG_SYSCFG, CACHE_ENABLE);
}
void icache_disable (void)
{
/* disable all cache bits */
CLR_REG( REG_SYSCFG, 0x3F);
}
int icache_status (void)
{
return GET_REG( REG_SYSCFG) & CACHE_ENABLE;
}
void dcache_enable (void)
{
/* we don't have seperate instruction/data caches */
icache_enable();
}
void dcache_disable (void)
{
/* we don't have seperate instruction/data caches */
icache_disable();
}
int dcache_status (void)
{
/* we don't have seperate instruction/data caches */
return icache_status();
}

185
arch/arm/cpu/arm720t/start.S
View File

@ -43,11 +43,7 @@ _start: b reset
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
ldr pc, _data_abort
#ifdef CONFIG_LPC2292
.word 0xB4405F76 /* 2's complement of the checksum of the vectors */
#else
ldr pc, _not_used
#endif
ldr pc, _irq
ldr pc, _fiq
@ -151,10 +147,6 @@ reset:
bl cpu_init_crit
#endif
#ifdef CONFIG_LPC2292
bl lowlevel_init
#endif
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
@ -291,148 +283,9 @@ _dynsym_start_ofs:
*************************************************************************
*/
#if defined(CONFIG_LPC2292)
PLLCFG_ADR: .word PLLCFG
PLLFEED_ADR: .word PLLFEED
PLLCON_ADR: .word PLLCON
PLLSTAT_ADR: .word PLLSTAT
VPBDIV_ADR: .word VPBDIV
MEMMAP_ADR: .word MEMMAP
#endif
cpu_init_crit:
#if defined(CONFIG_NETARM)
/*
* prior to software reset : need to set pin PORTC4 to be *HRESET
*/
ldr r0, =NETARM_GEN_MODULE_BASE
ldr r1, =(NETARM_GEN_PORT_MODE(0x10) | \
NETARM_GEN_PORT_DIR(0x10))
str r1, [r0, #+NETARM_GEN_PORTC]
/*
* software reset : see HW Ref. Guide 8.2.4 : Software Service register
* for an explanation of this process
*/
ldr r0, =NETARM_GEN_MODULE_BASE
ldr r1, =NETARM_GEN_SW_SVC_RESETA
str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
ldr r1, =NETARM_GEN_SW_SVC_RESETB
str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
ldr r1, =NETARM_GEN_SW_SVC_RESETA
str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
ldr r1, =NETARM_GEN_SW_SVC_RESETB
str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
/*
* setup PLL and System Config
*/
ldr r0, =NETARM_GEN_MODULE_BASE
ldr r1, =( NETARM_GEN_SYS_CFG_LENDIAN | \
NETARM_GEN_SYS_CFG_BUSFULL | \
NETARM_GEN_SYS_CFG_USER_EN | \
NETARM_GEN_SYS_CFG_ALIGN_ABORT | \
NETARM_GEN_SYS_CFG_BUSARB_INT | \
NETARM_GEN_SYS_CFG_BUSMON_EN )
str r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL]
#ifndef CONFIG_NETARM_PLL_BYPASS
ldr r1, =( NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \
NETARM_GEN_PLL_CTL_POLTST_DEF | \
NETARM_GEN_PLL_CTL_INDIV(1) | \
NETARM_GEN_PLL_CTL_ICP_DEF | \
NETARM_GEN_PLL_CTL_OUTDIV(2) )
str r1, [r0, #+NETARM_GEN_PLL_CONTROL]
#endif
/*
* mask all IRQs by clearing all bits in the INTMRs
*/
mov r1, #0
ldr r0, =NETARM_GEN_MODULE_BASE
str r1, [r0, #+NETARM_GEN_INTR_ENABLE]
#elif defined(CONFIG_S3C4510B)
/*
* Mask off all IRQ sources
*/
ldr r1, =REG_INTMASK
ldr r0, =0x3FFFFF
str r0, [r1]
/*
* Disable Cache
*/
ldr r0, =REG_SYSCFG
ldr r1, =0x83ffffa0 /* cache-disabled */
str r1, [r0]
#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
/* No specific initialisation for IntegratorAP/CM720T as yet */
#elif defined(CONFIG_LPC2292)
/* Set-up PLL */
mov r3, #0xAA
mov r4, #0x55
/* First disconnect and disable the PLL */
ldr r0, PLLCON_ADR
mov r1, #0x00
str r1, [r0]
ldr r0, PLLFEED_ADR /* start feed sequence */
str r3, [r0]
str r4, [r0] /* feed sequence done */
/* Set new M and P values */
ldr r0, PLLCFG_ADR
mov r1, #0x23 /* M=4 and P=2 */
str r1, [r0]
ldr r0, PLLFEED_ADR /* start feed sequence */
str r3, [r0]
str r4, [r0] /* feed sequence done */
/* Then enable the PLL */
ldr r0, PLLCON_ADR
mov r1, #0x01 /* PLL enable bit */
str r1, [r0]
ldr r0, PLLFEED_ADR /* start feed sequence */
str r3, [r0]
str r4, [r0] /* feed sequence done */
/* Wait for the lock */
ldr r0, PLLSTAT_ADR
mov r1, #0x400 /* lock bit */
lock_loop:
ldr r2, [r0]
and r2, r1, r2
cmp r2, #0
beq lock_loop
/* And finally connect the PLL */
ldr r0, PLLCON_ADR
mov r1, #0x03 /* PLL enable bit and connect bit */
str r1, [r0]
ldr r0, PLLFEED_ADR /* start feed sequence */
str r3, [r0]
str r4, [r0] /* feed sequence done */
/* Set-up VPBDIV register */
ldr r0, VPBDIV_ADR
mov r1, #0x01 /* VPB clock is same as process clock */
str r1, [r0]
#elif defined(CONFIG_TEGRA)
/* No cpu_init_crit for tegra as yet */
#else
#error No cpu_init_crit() defined for current CPU type
#endif
#ifdef CONFIG_ARM7_REVD
/* set clock speed */
/* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */
/* !!! not doing DRAM refresh properly! */
ldr r0, SYSCON3
ldr r1, [r0]
bic r1, r1, #CLKCTL
orr r1, r1, #CLKCTL_36
str r1, [r0]
#endif
#if !defined(CONFIG_LPC2292) && !defined(CONFIG_TEGRA)
#if !defined(CONFIG_TEGRA)
mov ip, lr
/*
* before relocating, we have to setup RAM timing
@ -610,39 +463,3 @@ fiq:
#endif
#endif /* CONFIG_SPL_BUILD */
#if defined(CONFIG_NETARM)
.align 5
.globl reset_cpu
reset_cpu:
ldr r1, =NETARM_MEM_MODULE_BASE
ldr r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR]
ldr r1, =0xFFFFF000
and r0, r1, r0
ldr r1, =(relocate-CONFIG_SYS_TEXT_BASE)
add r0, r1, r0
ldr r4, =NETARM_GEN_MODULE_BASE
ldr r1, =NETARM_GEN_SW_SVC_RESETA
str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
ldr r1, =NETARM_GEN_SW_SVC_RESETB
str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
ldr r1, =NETARM_GEN_SW_SVC_RESETA
str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
ldr r1, =NETARM_GEN_SW_SVC_RESETB
str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
mov pc, r0
#elif defined(CONFIG_S3C4510B)
/* Nothing done here as reseting the CPU is board specific, depending
* on external peripherals such as watchdog timers, etc. */
#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
/* No specific reset actions for IntegratorAP/CM720T as yet */
#elif defined(CONFIG_LPC2292)
.align 5
.globl reset_cpu
reset_cpu:
mov pc, r0
#elif defined(CONFIG_TEGRA)
/* No specific reset actions for tegra as yet */
#else
#error No reset_cpu() defined for current CPU type
#endif

95
arch/arm/cpu/arm720t/tegra-common/spl.c
View File

@ -23,105 +23,42 @@
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/u-boot.h>
#include <asm/utils.h>
#include <nand.h>
#include <mmc.h>
#include <fat.h>
#include <version.h>
#include <i2c.h>
#include <image.h>
#include <malloc.h>
#include <linux/compiler.h>
#include "cpu.h"
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/board.h>
#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/pmc.h>
#include <asm/arch-tegra/scu.h>
#include <asm/arch-tegra/sys_proto.h>
#include <asm/arch/spl.h>
DECLARE_GLOBAL_DATA_PTR;
/* Define global data structure pointer to it*/
static gd_t gdata __attribute__ ((section(".data")));
static bd_t bdata __attribute__ ((section(".data")));
inline void hang(void)
{
puts("### ERROR ### Please RESET the board ###\n");
for (;;)
;
}
void board_init_f(ulong dummy)
{
board_init_uart_f();
/* Initialize periph GPIOs */
gpio_early_init_uart();
/*
* We call relocate_code() with relocation target same as the
* CONFIG_SYS_SPL_TEXT_BASE. This will result in relocation getting
* skipped. Instead, only .bss initialization will happen. That's
* all we need
*/
debug(">>board_init_f()\n");
relocate_code(CONFIG_SPL_STACK, &gdata, CONFIG_SPL_TEXT_BASE);
}
/* This requires UART clocks to be enabled */
static void preloader_console_init(void)
{
const char *u_boot_rev = U_BOOT_VERSION;
gd = &gdata;
gd->bd = &bdata;
gd->flags |= GD_FLG_RELOC;
gd->baudrate = CONFIG_BAUDRATE;
serial_init(); /* serial communications setup */
gd->have_console = 1;
/* Avoid a second "U-Boot" coming from this string */
u_boot_rev = &u_boot_rev[7];
printf("\nU-Boot SPL %s (%s - %s)\n", u_boot_rev, U_BOOT_DATE,
U_BOOT_TIME);
}
void board_init_r(gd_t *id, ulong dummy)
void spl_board_init(void)
{
struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
/* enable JTAG */
writel(0xC0, &pmt->pmt_cfg_ctl);
debug(">>spl:board_init_r()\n");
board_init_uart_f();
mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START,
CONFIG_SYS_SPL_MALLOC_SIZE);
#ifdef CONFIG_SPL_BOARD_INIT
spl_board_init();
#endif
/* Initialize periph GPIOs */
gpio_early_init_uart();
clock_early_init();
serial_init();
preloader_console_init();
start_cpu((u32)CONFIG_SYS_TEXT_BASE);
halt_avp();
/* not reached */
}
int board_usb_init(const void *blob)
u32 spl_boot_device(void)
{
return 0;
return BOOT_DEVICE_RAM;
}
void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
{
debug("image entry point: 0x%X\n", spl_image->entry_point);
start_cpu((u32)spl_image->entry_point);
halt_avp();
}

8
arch/arm/cpu/arm920t/ep93xx/u-boot.lds
View File

@ -48,9 +48,11 @@ SECTIONS
.got : { *(.got) }
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
.u_boot_list : {
#include <u-boot.lst>
}
. = ALIGN(4);
__bss_start = .;

6
arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
View File

@ -72,10 +72,10 @@ lowlevel_init:
* enable UART for early debug trace
*/
ldr r1, =(KS8695_IO_BASE+KS8695_UART_DIVISOR)
mov r2, #0xd9
str r2, [r1] /* 115200 baud */
mov r2, #((25000000+CONFIG_BAUDRATE/2) / CONFIG_BAUDRATE)
str r2, [r1]
ldr r1, =(KS8695_IO_BASE+KS8695_UART_LINE_CTRL)
mov r2, #0x03
mov r2, #KS8695_UART_LINEC_WLEN8
str r2, [r1] /* 8 data bits, no parity, 1 stop */
ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
mov r2, #0x41

3
arch/arm/cpu/arm920t/s3c24x0/Makefile
View File

@ -29,9 +29,6 @@ COBJS-$(CONFIG_USE_IRQ) += interrupts.o
COBJS-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o
COBJS-y += speed.o
COBJS-y += timer.o
COBJS-y += usb.o
COBJS-y += usb_ohci.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))

71
arch/arm/cpu/arm920t/s3c24x0/usb.c
View File

@ -1,71 +0,0 @@
/*
* (C) Copyright 2006
* DENX Software Engineering <mk@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#if defined(CONFIG_USB_OHCI_NEW) && \
defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \
defined(CONFIG_S3C24X0)
#include <asm/arch/s3c24x0_cpu.h>
#include <asm/io.h>
int usb_cpu_init(void)
{
struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
/*
* Set the 48 MHz UPLL clocking. Values are taken from
* "PLL value selection guide", 6-23, s3c2400_UM.pdf.
*/
writel((40 << 12) + (1 << 4) + 2, &clk_power->upllcon);
/* 1 = use pads related USB for USB host */
writel(readl(&gpio->misccr) | 0x8, &gpio->misccr);
/*
* Enable USB host clock.
*/
writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);
return 0;
}
int usb_cpu_stop(void)
{
struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
/* may not want to do this */
writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
return 0;
}
int usb_cpu_init_fail(void)
{
struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
return 0;
}
#endif /* defined(CONFIG_USB_OHCI_NEW) && \
defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \
defined(CONFIG_S3C24X0) */

15
arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
View File

@ -118,6 +118,21 @@ void at91_serial2_hw_init(void)
writel(1 << ATMEL_ID_USART2, &pmc->pcer);
}
void at91_mci_hw_init(void)
{
/* Initialize the MCI0 */
at91_set_a_periph(AT91_PIO_PORTA, 17, 1); /* MCCK */
at91_set_a_periph(AT91_PIO_PORTA, 16, 1); /* MCCDA */
at91_set_a_periph(AT91_PIO_PORTA, 15, 1); /* MCDA0 */
at91_set_a_periph(AT91_PIO_PORTA, 18, 1); /* MCDA1 */
at91_set_a_periph(AT91_PIO_PORTA, 19, 1); /* MCDA2 */
at91_set_a_periph(AT91_PIO_PORTA, 20, 1); /* MCDA3 */
/* Enable clock for MCI0 */
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
writel(1 << ATMEL_ID_HSMCI0, &pmc->pcer);
}
#ifdef CONFIG_ATMEL_SPI
void at91_spi0_hw_init(unsigned long cs_mask)
{

7
arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
View File

@ -50,9 +50,10 @@ SECTIONS
}
. = ALIGN(4);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
.u_boot_list : {
#include <u-boot.lst>
}
. = ALIGN(4);

7
arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
View File

@ -50,9 +50,10 @@ SECTIONS
}
. = ALIGN(4);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
.u_boot_list : {
#include <u-boot.lst>
}
. = ALIGN(4);

1
arch/arm/cpu/armv7/am33xx/Makefile
View File

@ -21,6 +21,7 @@ COBJS += sys_info.o
COBJS += ddr.o
COBJS += emif4.o
COBJS += board.o
COBJS += mux.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))

239
arch/arm/cpu/armv7/am33xx/board.c
View File

@ -36,9 +36,6 @@
DECLARE_GLOBAL_DATA_PTR;
struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
static const struct gpio_bank gpio_bank_am33xx[4] = {
{ (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
{ (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
@ -48,153 +45,11 @@ static const struct gpio_bank gpio_bank_am33xx[4] = {
const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
/* MII mode defines */
#define MII_MODE_ENABLE 0x0
#define RGMII_MODE_ENABLE 0xA
/* GPIO that controls power to DDR on EVM-SK */
#define GPIO_DDR_VTT_EN 7
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
static struct am335x_baseboard_id __attribute__((section (".data"))) header;
static inline int board_is_bone(void)
{
return !strncmp(header.name, "A335BONE", HDR_NAME_LEN);
}
static inline int board_is_evm_sk(void)
{
return !strncmp("A335X_SK", header.name, HDR_NAME_LEN);
}
/*
* Read header information from EEPROM into global structure.
*/
static int read_eeprom(void)
{
/* Check if baseboard eeprom is available */
if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
puts("Could not probe the EEPROM; something fundamentally "
"wrong on the I2C bus.\n");
return -ENODEV;
}
/* read the eeprom using i2c */
if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
sizeof(header))) {
puts("Could not read the EEPROM; something fundamentally"
" wrong on the I2C bus.\n");
return -EIO;
}
if (header.magic != 0xEE3355AA) {
/*
* read the eeprom using i2c again,
* but use only a 1 byte address
*/
if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1,
(uchar *)&header, sizeof(header))) {
puts("Could not read the EEPROM; something "
"fundamentally wrong on the I2C bus.\n");
return -EIO;
}
if (header.magic != 0xEE3355AA) {
printf("Incorrect magic number (0x%x) in EEPROM\n",
header.magic);
return -EINVAL;
}
}
return 0;
}
/* UART Defines */
#ifdef CONFIG_SPL_BUILD
#define UART_RESET (0x1 << 1)
#define UART_CLK_RUNNING_MASK 0x1
#define UART_SMART_IDLE_EN (0x1 << 0x3)
#endif
/*
* Determine what type of DDR we have.
*/
static short inline board_memory_type(void)
{
/* The following boards are known to use DDR3. */
if (board_is_evm_sk())
return EMIF_REG_SDRAM_TYPE_DDR3;
return EMIF_REG_SDRAM_TYPE_DDR2;
}
/*
* early system init of muxing and clocks.
*/
void s_init(void)
{
/* WDT1 is already running when the bootloader gets control
* Disable it to avoid "random" resets
*/
writel(0xAAAA, &wdtimer->wdtwspr);
while (readl(&wdtimer->wdtwwps) != 0x0)
;
writel(0x5555, &wdtimer->wdtwspr);
while (readl(&wdtimer->wdtwwps) != 0x0)
;
#ifdef CONFIG_SPL_BUILD
/* Setup the PLLs and the clocks for the peripherals */
pll_init();
/* UART softreset */
u32 regVal;
enable_uart0_pin_mux();
regVal = readl(&uart_base->uartsyscfg);
regVal |= UART_RESET;
writel(regVal, &uart_base->uartsyscfg);
while ((readl(&uart_base->uartsyssts) &
UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
;
/* Disable smart idle */
regVal = readl(&uart_base->uartsyscfg);
regVal |= UART_SMART_IDLE_EN;
writel(regVal, &uart_base->uartsyscfg);
gd = &gdata;
preloader_console_init();
/* Initalize the board header */
enable_i2c0_pin_mux();
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
if (read_eeprom() < 0)
puts("Could not get board ID.\n");
enable_board_pin_mux(&header);
if (board_is_evm_sk()) {
/*
* EVM SK 1.2A and later use gpio0_7 to enable DDR3.
* This is safe enough to do on older revs.
*/
gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
gpio_direction_output(GPIO_DDR_VTT_EN, 1);
}
config_ddr(board_memory_type());
#endif
}
#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
int cpu_mmc_init(bd_t *bis)
{
int ret;
ret = omap_mmc_init(0, 0, 0);
if (ret)
return ret;
@ -208,93 +63,3 @@ void setup_clocks_for_console(void)
/* Not yet implemented */
return;
}
/*
* Basic board specific setup. Pinmux has been handled already.
*/
int board_init(void)
{
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
if (read_eeprom() < 0)
puts("Could not get board ID.\n");
gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
return 0;
}
#ifdef CONFIG_DRIVER_TI_CPSW
static void cpsw_control(int enabled)
{
/* VTP can be added here */
return;
}
static struct cpsw_slave_data cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
.phy_id = 0,
},
{
.slave_reg_ofs = 0x308,
.sliver_reg_ofs = 0xdc0,
.phy_id = 1,
},
};
static struct cpsw_platform_data cpsw_data = {
.mdio_base = AM335X_CPSW_MDIO_BASE,
.cpsw_base = AM335X_CPSW_BASE,
.mdio_div = 0xff,
.channels = 8,
.cpdma_reg_ofs = 0x800,
.slaves = 1,
.slave_data = cpsw_slaves,
.ale_reg_ofs = 0xd00,
.ale_entries = 1024,
.host_port_reg_ofs = 0x108,
.hw_stats_reg_ofs = 0x900,
.mac_control = (1 << 5),
.control = cpsw_control,
.host_port_num = 0,
.version = CPSW_CTRL_VERSION_2,
};
int board_eth_init(bd_t *bis)
{
uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;
if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
debug("<ethaddr> not set. Reading from E-fuse\n");
/* try reading mac address from efuse */
mac_lo = readl(&cdev->macid0l);
mac_hi = readl(&cdev->macid0h);
mac_addr[0] = mac_hi & 0xFF;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
mac_addr[4] = mac_lo & 0xFF;
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
if (is_valid_ether_addr(mac_addr))
eth_setenv_enetaddr("ethaddr", mac_addr);
else
return -1;
}
if (board_is_bone()) {
writel(MII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
PHY_INTERFACE_MODE_MII;
} else {
writel(RGMII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
PHY_INTERFACE_MODE_RGMII;
}
return cpsw_register(&cpsw_data);
}
#endif

41
arch/arm/cpu/armv7/am33xx/clock.c
View File

@ -44,6 +44,7 @@
const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC;
static void enable_interface_clocks(void)
{
@ -114,6 +115,41 @@ static void enable_per_clocks(void)
while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
;
/* UART1 */
#ifdef CONFIG_SERIAL2
writel(PRCM_MOD_EN, &cmper->uart1clkctrl);
while (readl(&cmper->uart1clkctrl) != PRCM_MOD_EN)
;
#endif /* CONFIG_SERIAL2 */
/* UART2 */
#ifdef CONFIG_SERIAL3
writel(PRCM_MOD_EN, &cmper->uart2clkctrl);
while (readl(&cmper->uart2clkctrl) != PRCM_MOD_EN)
;
#endif /* CONFIG_SERIAL3 */
/* UART3 */
#ifdef CONFIG_SERIAL4
writel(PRCM_MOD_EN, &cmper->uart3clkctrl);
while (readl(&cmper->uart3clkctrl) != PRCM_MOD_EN)
;
#endif /* CONFIG_SERIAL4 */
/* UART4 */
#ifdef CONFIG_SERIAL5
writel(PRCM_MOD_EN, &cmper->uart4clkctrl);
while (readl(&cmper->uart4clkctrl) != PRCM_MOD_EN)
;
#endif /* CONFIG_SERIAL5 */
/* UART5 */
#ifdef CONFIG_SERIAL6
writel(PRCM_MOD_EN, &cmper->uart5clkctrl);
while (readl(&cmper->uart5clkctrl) != PRCM_MOD_EN)
;
#endif /* CONFIG_SERIAL6 */
/* MMC0*/
writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
@ -153,6 +189,11 @@ static void enable_per_clocks(void)
writel(PRCM_MOD_EN, &cmper->spi0clkctrl);
while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN)
;
/* RTC */
writel(PRCM_MOD_EN, &cmrtc->rtcclkctrl);
while (readl(&cmrtc->rtcclkctrl) != PRCM_MOD_EN)
;
}
static void mpu_pll_config(void)

1
arch/arm/cpu/armv7/am33xx/config.mk
View File

@ -13,6 +13,7 @@
#
ifdef CONFIG_SPL_BUILD
ALL-y += $(OBJTREE)/MLO
ALL-$(CONFIG_SPL_SPI_SUPPORT) += $(OBJTREE)/MLO.byteswap
else
ALL-y += $(obj)u-boot.img
endif

114
arch/arm/cpu/armv7/am33xx/emif4.c
View File

@ -47,78 +47,6 @@ void dram_init_banksize(void)
static struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR;
static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
static const struct ddr_data ddr2_data = {
.datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
|(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)),
.datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
|(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)),
.datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
|(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)),
.datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
|(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)),
.datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
|(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
.datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
|(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)),
.datauserank0delay = DDR2_PHY_RANK0_DELAY,
.datadldiff0 = PHY_DLL_LOCK_DIFF,
};
static const struct cmd_control ddr2_cmd_ctrl_data = {
.cmd0csratio = DDR2_RATIO,
.cmd0dldiff = DDR2_DLL_LOCK_DIFF,
.cmd0iclkout = DDR2_INVERT_CLKOUT,
.cmd1csratio = DDR2_RATIO,
.cmd1dldiff = DDR2_DLL_LOCK_DIFF,
.cmd1iclkout = DDR2_INVERT_CLKOUT,
.cmd2csratio = DDR2_RATIO,
.cmd2dldiff = DDR2_DLL_LOCK_DIFF,
.cmd2iclkout = DDR2_INVERT_CLKOUT,
};
static const struct emif_regs ddr2_emif_reg_data = {
.sdram_config = DDR2_EMIF_SDCFG,
.ref_ctrl = DDR2_EMIF_SDREF,
.sdram_tim1 = DDR2_EMIF_TIM1,
.sdram_tim2 = DDR2_EMIF_TIM2,
.sdram_tim3 = DDR2_EMIF_TIM3,
.emif_ddr_phy_ctlr_1 = DDR2_EMIF_READ_LATENCY,
};
static const struct ddr_data ddr3_data = {
.datardsratio0 = DDR3_RD_DQS,
.datawdsratio0 = DDR3_WR_DQS,
.datafwsratio0 = DDR3_PHY_FIFO_WE,
.datawrsratio0 = DDR3_PHY_WR_DATA,
.datadldiff0 = PHY_DLL_LOCK_DIFF,
};
static const struct cmd_control ddr3_cmd_ctrl_data = {
.cmd0csratio = DDR3_RATIO,
.cmd0dldiff = DDR3_DLL_LOCK_DIFF,
.cmd0iclkout = DDR3_INVERT_CLKOUT,
.cmd1csratio = DDR3_RATIO,
.cmd1dldiff = DDR3_DLL_LOCK_DIFF,
.cmd1iclkout = DDR3_INVERT_CLKOUT,
.cmd2csratio = DDR3_RATIO,
.cmd2dldiff = DDR3_DLL_LOCK_DIFF,
.cmd2iclkout = DDR3_INVERT_CLKOUT,
};
static struct emif_regs ddr3_emif_reg_data = {
.sdram_config = DDR3_EMIF_SDCFG,
.ref_ctrl = DDR3_EMIF_SDREF,
.sdram_tim1 = DDR3_EMIF_TIM1,
.sdram_tim2 = DDR3_EMIF_TIM2,
.sdram_tim3 = DDR3_EMIF_TIM3,
.zq_config = DDR3_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = DDR3_EMIF_READ_LATENCY,
};
static void config_vtp(void)
{
writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE,
@ -134,46 +62,26 @@ static void config_vtp(void)
;
}
void config_ddr(short ddr_type)
void config_ddr(unsigned int pll, unsigned int ioctrl,
const struct ddr_data *data, const struct cmd_control *ctrl,
const struct emif_regs *regs)
{
int ddr_pll, ioctrl_val;
const struct emif_regs *emif_regs;
const struct ddr_data *ddr_data;
const struct cmd_control *cmd_ctrl_data;
if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR2) {
ddr_pll = 266;
cmd_ctrl_data = &ddr2_cmd_ctrl_data;
ddr_data = &ddr2_data;
ioctrl_val = DDR2_IOCTRL_VALUE;
emif_regs = &ddr2_emif_reg_data;
} else if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR3) {
ddr_pll = 303;
cmd_ctrl_data = &ddr3_cmd_ctrl_data;
ddr_data = &ddr3_data;
ioctrl_val = DDR3_IOCTRL_VALUE;
emif_regs = &ddr3_emif_reg_data;
} else {
puts("Unknown memory type");
hang();
}
enable_emif_clocks();
ddr_pll_config(ddr_pll);
ddr_pll_config(pll);
config_vtp();
config_cmd_ctrl(cmd_ctrl_data);
config_cmd_ctrl(ctrl);
config_ddr_data(0, ddr_data);
config_ddr_data(1, ddr_data);
config_ddr_data(0, data);
config_ddr_data(1, data);
config_io_ctrl(ioctrl_val);
config_io_ctrl(ioctrl);
/* Set CKE to be controlled by EMIF/DDR PHY */
writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
/* Program EMIF instance */
config_ddr_phy(emif_regs);
set_sdram_timings(emif_regs);
config_sdram(emif_regs);
config_ddr_phy(regs);
set_sdram_timings(regs);
config_sdram(regs);
}
#endif

33
arch/arm/cpu/armv7/am33xx/mux.c 100644
View File

@ -0,0 +1,33 @@
/*
* mux.c
*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <common.h>
#include <asm/arch/mux.h>
#include <asm/arch/hardware.h>
#include <asm/io.h>
/*
* Configure the pin mux for the module
*/
void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux)
{
int i;
if (!mod_pin_mux)
return;
for (i = 0; mod_pin_mux[i].reg_offset != -1; i++)
MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset);
}

5
arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
View File

@ -47,6 +47,11 @@ SECTIONS
. = ALIGN(4);
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
.u_boot_list : {
#include <u-boot.lst>
}
. = ALIGN(4);
__image_copy_end = .;
_end = .;

28
arch/arm/cpu/armv7/omap3/board.c
View File

@ -50,7 +50,9 @@ DECLARE_GLOBAL_DATA_PTR;
/* Declarations */
extern omap3_sysinfo sysinfo;
static void omap3_setup_aux_cr(void);
#ifndef CONFIG_SYS_L2CACHE_OFF
static void omap3_invalidate_l2_cache_secure(void);
#endif
static const struct gpio_bank gpio_bank_34xx[6] = {
{ (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
@ -410,19 +412,6 @@ static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
}
}
static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
{
u32 acr;
/* Read ACR */
asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
acr &= ~clear_bits;
acr |= set_bits;
/* Write ACR - affects non-secure banked bits */
asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
}
static void omap3_setup_aux_cr(void)
{
/* Workaround for Cortex-A8 errata: #454179 #430973
@ -436,6 +425,19 @@ static void omap3_setup_aux_cr(void)
}
#ifndef CONFIG_SYS_L2CACHE_OFF
static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
{
u32 acr;
/* Read ACR */
asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
acr &= ~clear_bits;
acr |= set_bits;
/* Write ACR - affects non-secure banked bits */
asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
}
/* Invalidate the entire L2 cache from secure mode */
static void omap3_invalidate_l2_cache_secure(void)
{

4
arch/arm/cpu/armv7/socfpga/spl.c
View File

@ -21,7 +21,6 @@
#include <asm/utils.h>
#include <version.h>
#include <image.h>
#include <malloc.h>
#include <asm/arch/reset_manager.h>
#include <spl.h>
@ -37,9 +36,6 @@ u32 spl_boot_device(void)
*/
void spl_board_init(void)
{
/* init timer for enabling delay function */
timer_init();
/* de-assert reset for peripherals and bridges based on handoff */
reset_deassert_peripherals_handoff();

8
arch/arm/cpu/ixp/u-boot.lds
View File

@ -46,9 +46,11 @@ SECTIONS
. = ALIGN(4);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
.u_boot_list : {
#include <u-boot.lst>
}
. = ALIGN(4);

83
arch/arm/cpu/lh7a40x/speed.c
View File

@ -1,83 +0,0 @@
/*
* (C) Copyright 2001-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2002
* David Mueller, ELSOFT AG, d.mueller@elsoft.ch
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <lh7a40x.h>
/* ------------------------------------------------------------------------- */
/* NOTE: This describes the proper use of this file.
*
* CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
*
* get_FCLK(), get_HCLK(), get_PCLK() return the clock of
* the specified bus in HZ.
*/
/* ------------------------------------------------------------------------- */
ulong get_PLLCLK (void)
{
return CONFIG_SYS_CLK_FREQ;
}
/* return FCLK frequency */
ulong get_FCLK (void)
{
lh7a40x_csc_t* csc = LH7A40X_CSC_PTR;
ulong maindiv1, maindiv2, prediv, ps;
/*
* from userguide 6.1.1.2
*
* FCLK = ((MAINDIV1 +2) * (MAINDIV2 +2) * 14.7456MHz) /
* ((PREDIV+2) * (2^PS))
*/
maindiv2 = (csc->clkset & CLKSET_MAINDIV2) >> 11;
maindiv1 = (csc->clkset & CLKSET_MAINDIV1) >> 7;
prediv = (csc->clkset & CLKSET_PREDIV) >> 2;
ps = (csc->clkset & CLKSET_PS) >> 16;
return (((maindiv2 + 2) * (maindiv1 + 2) * CONFIG_SYS_CLK_FREQ) /
((prediv + 2) * (1 << ps)));
}
/* return HCLK frequency */
ulong get_HCLK (void)
{
lh7a40x_csc_t* csc = LH7A40X_CSC_PTR;
return (get_FCLK () / ((csc->clkset & CLKSET_HCLKDIV) + 1));
}
/* return PCLK frequency */
ulong get_PCLK (void)
{
lh7a40x_csc_t* csc = LH7A40X_CSC_PTR;
return (get_HCLK () /
(1 << (((csc->clkset & CLKSET_PCLKDIV) >> 16) + 1)));
}

506
arch/arm/cpu/lh7a40x/start.S
View File

@ -1,506 +0,0 @@
/*
* armboot - Startup Code for ARM920 CPU-core
*
* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <asm-offsets.h>
#include <config.h>
#include <version.h>
/*
*************************************************************************
*
* Jump vector table as in table 3.1 in [1]
*
*************************************************************************
*/
.globl _start
_start: b reset
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
ldr pc, _data_abort
ldr pc, _not_used
ldr pc, _irq
ldr pc, _fiq
_undefined_instruction: .word undefined_instruction
_software_interrupt: .word software_interrupt
_prefetch_abort: .word prefetch_abort
_data_abort: .word data_abort
_not_used: .word not_used
_irq: .word irq
_fiq: .word fiq
.balignl 16,0xdeadbeef
/*
*************************************************************************
*
* Startup Code (reset vector)
*
* do important init only if we don't start from memory!
* relocate armboot to ram
* setup stack
* jump to second stage
*
*************************************************************************
*/
.globl _TEXT_BASE
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
/*
* These are defined in the board-specific linker script.
* Subtracting _start from them lets the linker put their
* relative position in the executable instead of leaving
* them null.
*/
.globl _bss_start_ofs
_bss_start_ofs:
.word __bss_start - _start
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end__ - _start
.globl _end_ofs
_end_ofs:
.word _end - _start
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
.word 0x0badc0de
/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
.word 0x0badc0de
#endif
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
.word 0x0badc0de
/*
* the actual reset code
*/
reset:
/*
* set the cpu to SVC32 mode
*/
mrs r0,cpsr
bic r0,r0,#0x1f
orr r0,r0,#0xd3
msr cpsr,r0
#define pWDTCTL 0x80001400 /* Watchdog Timer control register */
#define pINTENC 0x8000050C /* Interrupt-Controller enable clear register */
#define pCLKSET 0x80000420 /* clock divisor register */
/* disable watchdog, set watchdog control register to
* all zeros (default reset)
*/
ldr r0, =pWDTCTL
mov r1, #0x0
str r1, [r0]
/*
* mask all IRQs by setting all bits in the INTENC register (default)
*/
mov r1, #0xffffffff
ldr r0, =pINTENC
str r1, [r0]
/* FCLK:HCLK:PCLK = 1:2:2 */
/* default FCLK is 200 MHz, using 14.7456 MHz fin */
ldr r0, =pCLKSET
ldr r1, =0x0004ee39
@ ldr r1, =0x0005ee39 @ 1: 2: 4
str r1, [r0]
/*
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit
#endif
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr r0,=0x00000000
bl board_init_f
/*------------------------------------------------------------------------------*/
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
* This "function" does not return, instead it continues in RAM
* after relocating the monitor code.
*
*/
.globl relocate_code
relocate_code:
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
/* Set up the stack */
stack_setup:
mov sp, r4
adr r0, _start
cmp r0, r6
moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r1!, {r9-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
#ifndef CONFIG_SPL_BUILD
/*
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
fixloop:
ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
add r0, r0, r9 /* r0 <- location to fix up in RAM */
ldr r1, [r2, #4]
and r7, r1, #0xff
cmp r7, #23 /* relative fixup? */
beq fixrel
cmp r7, #2 /* absolute fixup? */
beq fixabs
/* ignore unknown type of fixup */
b fixnext
fixabs:
/* absolute fix: set location to (offset) symbol value */
mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
add r1, r10, r1 /* r1 <- address of symbol in table */
ldr r1, [r1, #4] /* r1 <- symbol value */
add r1, r1, r9 /* r1 <- relocated sym addr */
b fixnext
fixrel:
/* relative fix: increase location by offset */
ldr r1, [r0]
add r1, r1, r9
fixnext:
str r1, [r0]
add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
blo fixloop
#endif
clear_bss:
#ifndef CONFIG_SPL_BUILD
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
mov r4, r6 /* reloc addr */
add r0, r0, r4
add r1, r1, r4
mov r2, #0x00000000 /* clear */
clbss_l:cmp r0, r1 /* clear loop... */
bhs clbss_e /* if reached end of bss, exit */
str r2, [r0]
add r0, r0, #4
b clbss_l
clbss_e:
#endif
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
ldr r0, _board_init_r_ofs
adr r1, _start
add lr, r0, r1
add lr, lr, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
mov r1, r6 /* dest_addr */
/* jump to it ... */
mov pc, lr
_board_init_r_ofs:
.word board_init_r - _start
_rel_dyn_start_ofs:
.word __rel_dyn_start - _start
_rel_dyn_end_ofs:
.word __rel_dyn_end - _start
_dynsym_start_ofs:
.word __dynsym_start - _start
/*
*************************************************************************
*
* CPU_init_critical registers
*
* setup important registers
* setup memory timing
*
*************************************************************************
*/
cpu_init_crit:
/*
* flush v4 I/D caches
*/
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
/*
* disable MMU stuff and caches
*/
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
orr r0, r0, #0x00000002 @ set bit 2 (A) Align
orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
orr r0, r0, #0x40000000 @ set bit 30 (nF) notFastBus
mcr p15, 0, r0, c1, c0, 0
/*
* before relocating, we have to setup RAM timing
* because memory timing is board-dependend, you will
* find a lowlevel_init.S in your board directory.
*/
mov ip, lr
bl lowlevel_init
mov lr, ip
mov pc, lr
/*
*************************************************************************
*
* Interrupt handling
*
*************************************************************************
*/
@
@ IRQ stack frame.
@
#define S_FRAME_SIZE 72
#define S_OLD_R0 68
#define S_PSR 64
#define S_PC 60
#define S_LR 56
#define S_SP 52
#define S_IP 48
#define S_FP 44
#define S_R10 40
#define S_R9 36
#define S_R8 32
#define S_R7 28
#define S_R6 24
#define S_R5 20
#define S_R4 16
#define S_R3 12
#define S_R2 8
#define S_R1 4
#define S_R0 0
#define MODE_SVC 0x13
#define I_BIT 0x80
/*
* use bad_save_user_regs for abort/prefetch/undef/swi ...
* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
*/
.macro bad_save_user_regs
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Calling r0-r12
ldr r2, IRQ_STACK_START_IN
ldmia r2, {r2 - r3} @ get pc, cpsr
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
add r5, sp, #S_SP
mov r1, lr
stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
mov r0, sp
.endm
.macro irq_save_user_regs
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Calling r0-r12
add r8, sp, #S_PC
stmdb r8, {sp, lr}^ @ Calling SP, LR
str lr, [r8, #0] @ Save calling PC
mrs r6, spsr
str r6, [r8, #4] @ Save CPSR
str r0, [r8, #8] @ Save OLD_R0
mov r0, sp
.endm
.macro irq_restore_user_regs
ldmia sp, {r0 - lr}^ @ Calling r0 - lr
mov r0, r0
ldr lr, [sp, #S_PC] @ Get PC
add sp, sp, #S_FRAME_SIZE
subs pc, lr, #4 @ return & move spsr_svc into cpsr
.endm
.macro get_bad_stack
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
str lr, [r13] @ save caller lr / spsr
mrs lr, spsr
str lr, [r13, #4]
mov r13, #MODE_SVC @ prepare SVC-Mode
@ msr spsr_c, r13
msr spsr, r13
mov lr, pc
movs pc, lr
.endm
.macro get_irq_stack @ setup IRQ stack
ldr sp, IRQ_STACK_START
.endm
.macro get_fiq_stack @ setup FIQ stack
ldr sp, FIQ_STACK_START
.endm
/*
* exception handlers
*/
.align 5
undefined_instruction:
get_bad_stack
bad_save_user_regs
bl do_undefined_instruction
.align 5
software_interrupt:
get_bad_stack
bad_save_user_regs
bl do_software_interrupt
.align 5
prefetch_abort:
get_bad_stack
bad_save_user_regs
bl do_prefetch_abort
.align 5
data_abort:
get_bad_stack
bad_save_user_regs
bl do_data_abort
.align 5
not_used:
get_bad_stack
bad_save_user_regs
bl do_not_used
#ifdef CONFIG_USE_IRQ
.align 5
irq:
get_irq_stack
irq_save_user_regs
bl do_irq
irq_restore_user_regs
.align 5
fiq:
get_fiq_stack
/* someone ought to write a more effiction fiq_save_user_regs */
irq_save_user_regs
bl do_fiq
irq_restore_user_regs
#else
.align 5
irq:
get_bad_stack
bad_save_user_regs
bl do_irq
.align 5
fiq:
get_bad_stack
bad_save_user_regs
bl do_fiq
#endif
.align 5
.globl reset_cpu
reset_cpu:
bl disable_interrupts
/* Disable watchdog */
ldr r1, =pWDTCTL
mov r3, #0
str r3, [r1]
/* reset counter */
ldr r3, =0x00001984
str r3, [r1, #4]
/* Enable the watchdog */
mov r3, #1
str r3, [r1]
_loop_forever:
b _loop_forever

182
arch/arm/cpu/lh7a40x/timer.c
View File

@ -1,182 +0,0 @@
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <lh7a40x.h>
static ulong timer_load_val = 0;
/* macro to read the 16 bit timer */
static inline ulong READ_TIMER(void)
{
lh7a40x_timers_t* timers = LH7A40X_TIMERS_PTR;
lh7a40x_timer_t* timer = &timers->timer1;
return (timer->value & 0x0000ffff);
}
static ulong timestamp;
static ulong lastdec;
int timer_init (void)
{
lh7a40x_timers_t* timers = LH7A40X_TIMERS_PTR;
lh7a40x_timer_t* timer = &timers->timer1;
/* a periodic timer using the 508kHz source */
timer->control = (TIMER_PER | TIMER_CLK508K);
if (timer_load_val == 0) {
/*
* 10ms period with 508.469kHz clock = 5084
*/
timer_load_val = CONFIG_SYS_HZ/100;
}
/* load value for 10 ms timeout */
lastdec = timer->load = timer_load_val;
/* auto load, start timer */
timer->control = timer->control | TIMER_EN;
timestamp = 0;
return (0);
}
/*
* timer without interrupts
*/
ulong get_timer (ulong base)
{
return (get_timer_masked() - base);
}
void __udelay (unsigned long usec)
{
ulong tmo,tmp;
/* normalize */
if (usec >= 1000) {
tmo = usec / 1000;
tmo *= CONFIG_SYS_HZ;
tmo /= 1000;
}
else {
if (usec > 1) {
tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000*1000);
}
else
tmo = 1;
}
/* check for rollover during this delay */
tmp = get_timer (0);
if ((tmp + tmo) < tmp )
reset_timer_masked(); /* timer would roll over */
else
tmo += tmp;
while (get_timer_masked () < tmo);
}
void reset_timer_masked (void)
{
/* reset time */
lastdec = READ_TIMER();
timestamp = 0;
}
ulong get_timer_masked (void)
{
ulong now = READ_TIMER();
if (lastdec >= now) {
/* normal mode */
timestamp += (lastdec - now);
} else {
/* we have an overflow ... */
timestamp += ((lastdec + timer_load_val) - now);
}
lastdec = now;
return timestamp;
}
void udelay_masked (unsigned long usec)
{
ulong tmo;
ulong endtime;
signed long diff;
/* normalize */
if (usec >= 1000) {
tmo = usec / 1000;
tmo *= CONFIG_SYS_HZ;
tmo /= 1000;
} else {
if (usec > 1) {
tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000*1000);
} else {
tmo = 1;
}
}
endtime = get_timer_masked () + tmo;
do {
ulong now = get_timer_masked ();
diff = endtime - now;
} while (diff >= 0);
}
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.
*/
unsigned long long get_ticks(void)
{
return get_timer(0);
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
ulong get_tbclk (void)
{
ulong tbclk;
tbclk = timer_load_val * 100;
return tbclk;
}

2
arch/arm/cpu/tegra20-common/emc.c
View File

@ -257,7 +257,7 @@ static int decode_emc(const void *blob, unsigned rate, struct emc_ctlr **emcp,
int tegra_set_emc(const void *blob, unsigned rate)
{
struct emc_ctlr *emc;
const u32 *table;
const u32 *table = NULL;
int err, i;
err = decode_emc(blob, rate, &emc, &table);

20
arch/arm/cpu/u-boot.lds
View File

@ -34,8 +34,8 @@ SECTIONS
.text :
{
__image_copy_start = .;
CPUDIR/start.o (.text)
*(.text)
CPUDIR/start.o (.text*)
*(.text*)
}
. = ALIGN(4);
@ -43,15 +43,17 @@ SECTIONS
. = ALIGN(4);
.data : {
*(.data)
*(.data*)
}
. = ALIGN(4);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
.u_boot_list : {
#include <u-boot.lst>
}
. = ALIGN(4);
@ -81,7 +83,7 @@ SECTIONS
.bss __rel_dyn_start (OVERLAY) : {
__bss_start = .;
*(.bss)
*(.bss*)
. = ALIGN(4);
__bss_end__ = .;
}
@ -92,3 +94,7 @@ SECTIONS
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu*) }
}
#if defined(CONFIG_SPL_TEXT_BASE) && defined(CONFIG_SPL_MAX_SIZE)
ASSERT(__bss_end__ < (CONFIG_SPL_TEXT_BASE + CONFIG_SPL_MAX_SIZE), "SPL image too big");
#endif

11
arch/arm/imx-common/cmd_bmode.c
View File

@ -24,6 +24,7 @@
#include <asm/io.h>
#include <asm/imx-common/boot_mode.h>
#include <malloc.h>
#include <command.h>
static const struct boot_mode *modes[2];
@ -103,9 +104,11 @@ void add_board_boot_modes(const struct boot_mode *p)
int size;
char *dest;
if (__u_boot_cmd_bmode.usage) {
free(__u_boot_cmd_bmode.usage);
__u_boot_cmd_bmode.usage = NULL;
cmd_tbl_t *entry = ll_entry_get(cmd_tbl_t, bmode, cmd);
if (entry->usage) {
free(entry->usage);
entry->usage = NULL;
}
modes[0] = p;
@ -114,6 +117,6 @@ void add_board_boot_modes(const struct boot_mode *p)
dest = malloc(size);
if (dest) {
create_usage(dest);
__u_boot_cmd_bmode.usage = dest;
entry->usage = dest;
}
}

15
arch/arm/include/asm/arch-am33xx/cpu.h
View File

@ -169,6 +169,12 @@ struct cm_dpll {
unsigned int clktimer2clk; /* offset 0x08 */
};
/* Control Module RTC registers */
struct cm_rtc {
unsigned int rtcclkctrl; /* offset 0x0 */
unsigned int clkstctrl; /* offset 0x4 */
};
/* Watchdog timer registers */
struct wd_timer {
unsigned int resv1[4];
@ -218,6 +224,15 @@ struct gptimer {
unsigned int tcar2; /* offset 0x58 */
};
/* RTC Registers */
struct rtc_regs {
unsigned int res[21];
unsigned int osc; /* offset 0x54 */
unsigned int res2[5];
unsigned int kick0r; /* offset 0x6c */
unsigned int kick1r; /* offset 0x70 */
};
/* UART Registers */
struct uart_sys {
unsigned int resv1[21];

69
arch/arm/include/asm/arch-am33xx/ddr_defs.h
View File

@ -29,40 +29,41 @@
#define PHY_DLL_LOCK_DIFF 0x0
#define DDR_CKE_CTRL_NORMAL 0x1
#define DDR2_EMIF_READ_LATENCY 0x100005 /* Enable Dynamic Power Down */
#define DDR2_EMIF_TIM1 0x0666B3C9
#define DDR2_EMIF_TIM2 0x243631CA
#define DDR2_EMIF_TIM3 0x0000033F
#define DDR2_EMIF_SDCFG 0x41805332
#define DDR2_EMIF_SDREF 0x0000081a
#define DDR2_DLL_LOCK_DIFF 0x0
#define DDR2_RATIO 0x80
#define DDR2_INVERT_CLKOUT 0x00
#define DDR2_RD_DQS 0x12
#define DDR2_WR_DQS 0x00
#define DDR2_PHY_WRLVL 0x00
#define DDR2_PHY_GATELVL 0x00
#define DDR2_PHY_WR_DATA 0x40
#define DDR2_PHY_FIFO_WE 0x80
#define DDR2_PHY_RANK0_DELAY 0x1
#define DDR2_IOCTRL_VALUE 0x18B
/* Micron MT47H128M16RT-25E */
#define MT47H128M16RT25E_EMIF_READ_LATENCY 0x100005
#define MT47H128M16RT25E_EMIF_TIM1 0x0666B3C9
#define MT47H128M16RT25E_EMIF_TIM2 0x243631CA
#define MT47H128M16RT25E_EMIF_TIM3 0x0000033F
#define MT47H128M16RT25E_EMIF_SDCFG 0x41805332
#define MT47H128M16RT25E_EMIF_SDREF 0x0000081a
#define MT47H128M16RT25E_DLL_LOCK_DIFF 0x0
#define MT47H128M16RT25E_RATIO 0x80
#define MT47H128M16RT25E_INVERT_CLKOUT 0x00
#define MT47H128M16RT25E_RD_DQS 0x12
#define MT47H128M16RT25E_WR_DQS 0x00
#define MT47H128M16RT25E_PHY_WRLVL 0x00
#define MT47H128M16RT25E_PHY_GATELVL 0x00
#define MT47H128M16RT25E_PHY_WR_DATA 0x40
#define MT47H128M16RT25E_PHY_FIFO_WE 0x80
#define MT47H128M16RT25E_PHY_RANK0_DELAY 0x1
#define MT47H128M16RT25E_IOCTRL_VALUE 0x18B
/* Micron MT41J128M16JT-125 */
#define DDR3_EMIF_READ_LATENCY 0x06
#define DDR3_EMIF_TIM1 0x0888A39B
#define DDR3_EMIF_TIM2 0x26337FDA
#define DDR3_EMIF_TIM3 0x501F830F
#define DDR3_EMIF_SDCFG 0x61C04AB2
#define DDR3_EMIF_SDREF 0x0000093B
#define DDR3_ZQ_CFG 0x50074BE4
#define DDR3_DLL_LOCK_DIFF 0x1
#define DDR3_RATIO 0x40
#define DDR3_INVERT_CLKOUT 0x1
#define DDR3_RD_DQS 0x3B
#define DDR3_WR_DQS 0x85
#define DDR3_PHY_WR_DATA 0xC1
#define DDR3_PHY_FIFO_WE 0x100
#define DDR3_IOCTRL_VALUE 0x18B
#define MT41J128MJT125_EMIF_READ_LATENCY 0x06
#define MT41J128MJT125_EMIF_TIM1 0x0888A39B
#define MT41J128MJT125_EMIF_TIM2 0x26337FDA
#define MT41J128MJT125_EMIF_TIM3 0x501F830F
#define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2
#define MT41J128MJT125_EMIF_SDREF 0x0000093B
#define MT41J128MJT125_ZQ_CFG 0x50074BE4
#define MT41J128MJT125_DLL_LOCK_DIFF 0x1
#define MT41J128MJT125_RATIO 0x40
#define MT41J128MJT125_INVERT_CLKOUT 0x1
#define MT41J128MJT125_RD_DQS 0x3B
#define MT41J128MJT125_WR_DQS 0x85
#define MT41J128MJT125_PHY_WR_DATA 0xC1
#define MT41J128MJT125_PHY_FIFO_WE 0x100
#define MT41J128MJT125_IOCTRL_VALUE 0x18B
/**
* Configure SDRAM
@ -189,6 +190,8 @@ struct ddr_ctrl {
unsigned int ddrckectrl;
};
void config_ddr(short ddr_type);
void config_ddr(unsigned int pll, unsigned int ioctrl,
const struct ddr_data *data, const struct cmd_control *ctrl,
const struct emif_regs *regs);
#endif /* _DDR_DEFS_H */

4
arch/arm/include/asm/arch-am33xx/hardware.h
View File

@ -61,6 +61,7 @@
#define CM_WKUP 0x44E00400
#define CM_DPLL 0x44E00500
#define CM_DEVICE 0x44E00700
#define CM_RTC 0x44E00800
#define CM_CEFUSE 0x44E00A00
#define PRM_DEVICE 0x44E00F00
@ -83,4 +84,7 @@
#define AM335X_CPSW_BASE 0x4A100000
#define AM335X_CPSW_MDIO_BASE 0x4A101000
/* RTC base address */
#define AM335X_RTC_BASE 0x44E3E000
#endif /* __AM33XX_HARDWARE_H */

261
arch/arm/include/asm/arch-am33xx/mux.h 100644
View File

@ -0,0 +1,261 @@
/*
* mux.h
*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _MUX_H_
#define _MUX_H_
#include <common.h>
#include <asm/io.h>
#define MUX_CFG(value, offset) \
__raw_writel(value, (CTRL_BASE + offset));
/* PAD Control Fields */
#define SLEWCTRL (0x1 << 6)
#define RXACTIVE (0x1 << 5)
#define PULLUP_EN (0x1 << 4) /* Pull UP Selection */
#define PULLUDEN (0x0 << 3) /* Pull up enabled */
#define PULLUDDIS (0x1 << 3) /* Pull up disabled */
#define MODE(val) val /* used for Readability */
/*
* PAD CONTROL OFFSETS
* Field names corresponds to the pad signal name
*/
struct pad_signals {
int gpmc_ad0;
int gpmc_ad1;
int gpmc_ad2;
int gpmc_ad3;
int gpmc_ad4;
int gpmc_ad5;
int gpmc_ad6;
int gpmc_ad7;
int gpmc_ad8;
int gpmc_ad9;
int gpmc_ad10;
int gpmc_ad11;
int gpmc_ad12;
int gpmc_ad13;
int gpmc_ad14;
int gpmc_ad15;
int gpmc_a0;
int gpmc_a1;
int gpmc_a2;
int gpmc_a3;
int gpmc_a4;
int gpmc_a5;
int gpmc_a6;
int gpmc_a7;
int gpmc_a8;
int gpmc_a9;
int gpmc_a10;
int gpmc_a11;
int gpmc_wait0;
int gpmc_wpn;
int gpmc_be1n;
int gpmc_csn0;
int gpmc_csn1;
int gpmc_csn2;
int gpmc_csn3;
int gpmc_clk;
int gpmc_advn_ale;
int gpmc_oen_ren;
int gpmc_wen;
int gpmc_be0n_cle;
int lcd_data0;
int lcd_data1;
int lcd_data2;
int lcd_data3;
int lcd_data4;
int lcd_data5;
int lcd_data6;
int lcd_data7;
int lcd_data8;
int lcd_data9;
int lcd_data10;
int lcd_data11;
int lcd_data12;
int lcd_data13;
int lcd_data14;
int lcd_data15;
int lcd_vsync;
int lcd_hsync;
int lcd_pclk;
int lcd_ac_bias_en;
int mmc0_dat3;
int mmc0_dat2;
int mmc0_dat1;
int mmc0_dat0;
int mmc0_clk;
int mmc0_cmd;
int mii1_col;
int mii1_crs;
int mii1_rxerr;
int mii1_txen;
int mii1_rxdv;
int mii1_txd3;
int mii1_txd2;
int mii1_txd1;
int mii1_txd0;
int mii1_txclk;
int mii1_rxclk;
int mii1_rxd3;
int mii1_rxd2;
int mii1_rxd1;
int mii1_rxd0;
int rmii1_refclk;
int mdio_data;
int mdio_clk;
int spi0_sclk;
int spi0_d0;
int spi0_d1;
int spi0_cs0;
int spi0_cs1;
int ecap0_in_pwm0_out;
int uart0_ctsn;
int uart0_rtsn;
int uart0_rxd;
int uart0_txd;
int uart1_ctsn;
int uart1_rtsn;
int uart1_rxd;
int uart1_txd;
int i2c0_sda;
int i2c0_scl;
int mcasp0_aclkx;
int mcasp0_fsx;
int mcasp0_axr0;
int mcasp0_ahclkr;
int mcasp0_aclkr;
int mcasp0_fsr;
int mcasp0_axr1;
int mcasp0_ahclkx;
int xdma_event_intr0;
int xdma_event_intr1;
int nresetin_out;
int porz;
int nnmi;
int osc0_in;
int osc0_out;
int rsvd1;
int tms;
int tdi;
int tdo;
int tck;
int ntrst;
int emu0;
int emu1;
int osc1_in;
int osc1_out;
int pmic_power_en;
int rtc_porz;
int rsvd2;
int ext_wakeup;
int enz_kaldo_1p8v;
int usb0_dm;
int usb0_dp;
int usb0_ce;
int usb0_id;
int usb0_vbus;
int usb0_drvvbus;
int usb1_dm;
int usb1_dp;
int usb1_ce;
int usb1_id;
int usb1_vbus;
int usb1_drvvbus;
int ddr_resetn;
int ddr_csn0;
int ddr_cke;
int ddr_ck;
int ddr_nck;
int ddr_casn;
int ddr_rasn;
int ddr_wen;
int ddr_ba0;
int ddr_ba1;
int ddr_ba2;
int ddr_a0;
int ddr_a1;
int ddr_a2;
int ddr_a3;
int ddr_a4;
int ddr_a5;
int ddr_a6;
int ddr_a7;
int ddr_a8;
int ddr_a9;
int ddr_a10;
int ddr_a11;
int ddr_a12;
int ddr_a13;
int ddr_a14;
int ddr_a15;
int ddr_odt;
int ddr_d0;
int ddr_d1;
int ddr_d2;
int ddr_d3;
int ddr_d4;
int ddr_d5;
int ddr_d6;
int ddr_d7;
int ddr_d8;
int ddr_d9;
int ddr_d10;
int ddr_d11;
int ddr_d12;
int ddr_d13;
int ddr_d14;
int ddr_d15;
int ddr_dqm0;
int ddr_dqm1;
int ddr_dqs0;
int ddr_dqsn0;
int ddr_dqs1;
int ddr_dqsn1;
int ddr_vref;
int ddr_vtp;
int ddr_strben0;
int ddr_strben1;
int ain7;
int ain6;
int ain5;
int ain4;
int ain3;
int ain2;
int ain1;
int ain0;
int vrefp;
int vrefn;
};
struct module_pin_mux {
short reg_offset;
unsigned char val;
};
/* Pad control register offset */
#define PAD_CTRL_BASE 0x800
#define OFFSET(x) (unsigned int) (&((struct pad_signals *) \
(PAD_CTRL_BASE))->x)
/*
* Configure the pin mux for the module
*/
void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux);
#endif

1
arch/arm/include/asm/arch-am33xx/spl.h
View File

@ -27,6 +27,7 @@
#define BOOT_DEVICE_NAND 5
#define BOOT_DEVICE_MMC1 8
#define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */
#define BOOT_DEVICE_SPI 11
#define BOOT_DEVICE_UART 65
#define BOOT_DEVICE_CPGMAC 70
#define BOOT_DEVICE_MMC2_2 0xFF

27
arch/arm/include/asm/arch-am33xx/sys_proto.h
View File

@ -19,24 +19,6 @@
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
/*
* AM335x parts define a system EEPROM that defines certain sub-fields.
* We use these fields to in turn see what board we are on, and what
* that might require us to set or not set.
*/
#define HDR_NO_OF_MAC_ADDR 3
#define HDR_ETH_ALEN 6
#define HDR_NAME_LEN 8
struct am335x_baseboard_id {
unsigned int magic;
char name[HDR_NAME_LEN];
char version[4];
char serial[12];
char config[32];
char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
};
#define BOARD_REV_ID 0x0
u32 get_cpu_rev(void);
@ -51,13 +33,4 @@ u32 get_device_type(void);
void setup_clocks_for_console(void);
void ddr_pll_config(unsigned int ddrpll_M);
/*
* We have three pin mux functions that must exist. We must be able to enable
* uart0, for initial output and i2c0 to read the main EEPROM. We then have a
* main pinmux function that can be overridden to enable all other pinmux that
* is required on the board.
*/
void enable_uart0_pin_mux(void);
void enable_i2c0_pin_mux(void);
void enable_board_pin_mux(struct am335x_baseboard_id *header);
#endif

4
arch/arm/include/asm/arch-arm720t/hardware.h
View File

@ -24,9 +24,7 @@
* MA 02111-1307 USA
*/
#if defined(CONFIG_NETARM)
#include <asm/arch-arm720t/netarm_registers.h>
#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
/* include IntegratorCP/CM720T specific hardware file if there was one */
#else
#error No hardware file defined for this configuration

182
arch/arm/include/asm/arch-arm720t/netarm_dma_module.h
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@ -1,182 +0,0 @@
/* * include/asm-armnommu/arch-netarm/netarm_dma_module.h
*
* Copyright (C) 2000 NETsilicon, Inc.
* Copyright (C) 2000 WireSpeed Communications Corporation
*
* This software is copyrighted by WireSpeed. LICENSEE agrees that
* it will not delete this copyright notice, trademarks or protective
* notices from any copy made by LICENSEE.
*
* This software is provided "AS-IS" and any express or implied
* warranties or conditions, including but not limited to any
* implied warranties of merchantability and fitness for a particular
* purpose regarding this software. In no event shall WireSpeed
* be liable for any indirect, consequential, or incidental damages,
* loss of profits or revenue, loss of use or data, or interruption
* of business, whether the alleged damages are labeled in contract,
* tort, or indemnity.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
* author(s) : Joe deBlaquiere
* David Smith
*/
#ifndef __NETARM_DMA_MODULE_REGISTERS_H
#define __NETARM_DMA_MODULE_REGISTERS_H
/* GEN unit register offsets */
#define NETARM_DMA_MODULE_BASE (0xFF900000)
#define get_dma_reg_addr(c) ((volatile unsigned int *)(NETARM_DMA_MODULE_BASE + (c)))
#define NETARM_DMA1A_BFR_DESCRPTOR_PTR (0x00)
#define NETARM_DMA1A_CONTROL (0x10)
#define NETARM_DMA1A_STATUS (0x14)
#define NETARM_DMA1B_BFR_DESCRPTOR_PTR (0x20)
#define NETARM_DMA1B_CONTROL (0x30)
#define NETARM_DMA1B_STATUS (0x34)
#define NETARM_DMA1C_BFR_DESCRPTOR_PTR (0x40)
#define NETARM_DMA1C_CONTROL (0x50)
#define NETARM_DMA1C_STATUS (0x54)
#define NETARM_DMA1D_BFR_DESCRPTOR_PTR (0x60)
#define NETARM_DMA1D_CONTROL (0x70)
#define NETARM_DMA1D_STATUS (0x74)
#define NETARM_DMA2_BFR_DESCRPTOR_PTR (0x80)
#define NETARM_DMA2_CONTROL (0x90)
#define NETARM_DMA2_STATUS (0x94)
#define NETARM_DMA3_BFR_DESCRPTOR_PTR (0xA0)
#define NETARM_DMA3_CONTROL (0xB0)
#define NETARM_DMA3_STATUS (0xB4)
#define NETARM_DMA4_BFR_DESCRPTOR_PTR (0xC0)
#define NETARM_DMA4_CONTROL (0xD0)
#define NETARM_DMA4_STATUS (0xD4)
#define NETARM_DMA5_BFR_DESCRPTOR_PTR (0xE0)
#define NETARM_DMA5_CONTROL (0xF0)
#define NETARM_DMA5_STATUS (0xF4)
#define NETARM_DMA6_BFR_DESCRPTOR_PTR (0x100)
#define NETARM_DMA6_CONTROL (0x110)
#define NETARM_DMA6_STATUS (0x114)
#define NETARM_DMA7_BFR_DESCRPTOR_PTR (0x120)
#define NETARM_DMA7_CONTROL (0x130)
#define NETARM_DMA7_STATUS (0x134)
#define NETARM_DMA8_BFR_DESCRPTOR_PTR (0x140)
#define NETARM_DMA8_CONTROL (0x150)
#define NETARM_DMA8_STATUS (0x154)
#define NETARM_DMA9_BFR_DESCRPTOR_PTR (0x160)
#define NETARM_DMA9_CONTROL (0x170)
#define NETARM_DMA9_STATUS (0x174)
#define NETARM_DMA10_BFR_DESCRPTOR_PTR (0x180)
#define NETARM_DMA10_CONTROL (0x190)
#define NETARM_DMA10_STATUS (0x194)
/* select bitfield defintions */
/* DMA Control Register ( 0xFF90_0XX0 ) */
#define NETARM_DMA_CTL_ENABLE (0x80000000)
#define NETARM_DMA_CTL_ABORT (0x40000000)
#define NETARM_DMA_CTL_BUS_100_PERCENT (0x00000000)
#define NETARM_DMA_CTL_BUS_75_PERCENT (0x10000000)
#define NETARM_DMA_CTL_BUS_50_PERCENT (0x20000000)
#define NETARM_DMA_CTL_BUS_25_PERCENT (0x30000000)
#define NETARM_DMA_CTL_BUS_MASK (0x30000000)
#define NETARM_DMA_CTL_MODE_FB_TO_MEM (0x00000000)
#define NETARM_DMA_CTL_MODE_FB_FROM_MEM (0x04000000)
#define NETARM_DMA_CTL_MODE_MEM_TO_MEM (0x08000000)
#define NETARM_DMA_CTL_BURST_NONE (0x00000000)
#define NETARM_DMA_CTL_BURST_8_BYTE (0x01000000)
#define NETARM_DMA_CTL_BURST_16_BYTE (0x02000000)
#define NETARM_DMA_CTL_BURST_MASK (0x03000000)
#define NETARM_DMA_CTL_SRC_INCREMENT (0x00200000)
#define NETARM_DMA_CTL_DST_INCREMENT (0x00100000)
/* these apply only to ext xfers on DMA 3 or 4 */
#define NETARM_DMA_CTL_CH_3_4_REQ_EXT (0x00800000)
#define NETARM_DMA_CTL_CH_3_4_DATA_32 (0x00000000)
#define NETARM_DMA_CTL_CH_3_4_DATA_16 (0x00010000)
#define NETARM_DMA_CTL_CH_3_4_DATA_8 (0x00020000)
#define NETARM_DMA_CTL_STATE(X) ((X) & 0xFC00)
#define NETARM_DMA_CTL_INDEX(X) ((X) & 0x03FF)
/* DMA Status Register ( 0xFF90_0XX4 ) */
#define NETARM_DMA_STAT_NC_INTPEN (0x80000000)
#define NETARM_DMA_STAT_EC_INTPEN (0x40000000)
#define NETARM_DMA_STAT_NR_INTPEN (0x20000000)
#define NETARM_DMA_STAT_CA_INTPEN (0x10000000)
#define NETARM_DMA_STAT_INTPEN_MASK (0xF0000000)
#define NETARM_DMA_STAT_NC_INT_EN (0x00800000)
#define NETARM_DMA_STAT_EC_INT_EN (0x00400000)
#define NETARM_DMA_STAT_NR_INT_EN (0x00200000)
#define NETARM_DMA_STAT_CA_INT_EN (0x00100000)
#define NETARM_DMA_STAT_INT_EN_MASK (0x00F00000)
#define NETARM_DMA_STAT_WRAP (0x00080000)
#define NETARM_DMA_STAT_IDONE (0x00040000)
#define NETARM_DMA_STAT_LAST (0x00020000)
#define NETARM_DMA_STAT_FULL (0x00010000)
#define NETARM_DMA_STAT_BUFLEN(X) ((X) & 0x7FFF)
/* DMA Buffer Descriptor Word 0 bitfields. */
#define NETARM_DMA_BD0_WRAP (0x80000000)
#define NETARM_DMA_BD0_IDONE (0x40000000)
#define NETARM_DMA_BD0_LAST (0x20000000)
#define NETARM_DMA_BD0_BUFPTR_MASK (0x1FFFFFFF)
/* DMA Buffer Descriptor Word 1 bitfields. */
#define NETARM_DMA_BD1_STATUS_MASK (0xFFFF0000)
#define NETARM_DMA_BD1_FULL (0x00008000)
#define NETARM_DMA_BD1_BUFLEN_MASK (0x00007FFF)
#ifndef __ASSEMBLER__
typedef struct __NETARM_DMA_Buff_Desc_FlyBy
{
unsigned int word0;
unsigned int word1;
} NETARM_DMA_Buff_Desc_FlyBy, *pNETARM_DMA_Buff_Desc_FlyBy ;
typedef struct __NETARM_DMA_Buff_Desc_M_to_M
{
unsigned int word0;
unsigned int word1;
unsigned int word2;
unsigned int word3;
} NETARM_DMA_Buff_Desc_M_to_M, *pNETARM_DMA_Buff_Desc_M_to_M ;
#endif
#endif

121
arch/arm/include/asm/arch-arm720t/netarm_eni_module.h
View File

@ -1,121 +0,0 @@
/*
* include/asm-armnommu/arch-netarm/netarm_eni_module.h
*
* Copyright (C) 2000 NETsilicon, Inc.
* Copyright (C) 2000 WireSpeed Communications Corporation
*
* This software is copyrighted by WireSpeed. LICENSEE agrees that
* it will not delete this copyright notice, trademarks or protective
* notices from any copy made by LICENSEE.
*
* This software is provided "AS-IS" and any express or implied
* warranties or conditions, including but not limited to any
* implied warranties of merchantability and fitness for a particular
* purpose regarding this software. In no event shall WireSpeed
* be liable for any indirect, consequential, or incidental damages,
* loss of profits or revenue, loss of use or data, or interruption
* of business, whether the alleged damages are labeled in contract,
* tort, or indemnity.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
* author(s) : David Smith
*/
#ifndef __NETARM_ENI_MODULE_REGISTERS_H
#define __NETARM_ENI_MODULE_REGISTERS_H
/* ENI unit register offsets */
/* #ifdef CONFIG_ARCH_NETARM */
#define NETARM_ENI_MODULE_BASE (0xFFA00000)
/* #endif / * CONFIG_ARCH_NETARM */
#define get_eni_reg_addr(c) ((volatile unsigned int *)(NETARM_ENI_MODULE_BASE + (c)))
#define get_eni_ctl_reg_addr(minor) \
(get_eni_reg_addr(NETARM_ENI_1284_PORT1_CONTROL) + (minor))
#define NETARM_ENI_GENERAL_CONTROL (0x00)
#define NETARM_ENI_STATUS_CONTROL (0x04)
#define NETARM_ENI_FIFO_MODE_DATA (0x08)
#define NETARM_ENI_1284_PORT1_CONTROL (0x10)
#define NETARM_ENI_1284_PORT2_CONTROL (0x14)
#define NETARM_ENI_1284_PORT3_CONTROL (0x18)
#define NETARM_ENI_1284_PORT4_CONTROL (0x1c)
#define NETARM_ENI_1284_CHANNEL1_DATA (0x20)
#define NETARM_ENI_1284_CHANNEL2_DATA (0x24)
#define NETARM_ENI_1284_CHANNEL3_DATA (0x28)
#define NETARM_ENI_1284_CHANNEL4_DATA (0x2c)
#define NETARM_ENI_ENI_CONTROL (0x30)
#define NETARM_ENI_ENI_PULSED_INTR (0x34)
#define NETARM_ENI_ENI_SHARED_RAM_ADDR (0x38)
#define NETARM_ENI_ENI_SHARED (0x3c)
/* select bitfield defintions */
/* General Control Register (0xFFA0_0000) */
#define NETARM_ENI_GCR_ENIMODE_IEEE1284 (0x00000001)
#define NETARM_ENI_GCR_ENIMODE_SHRAM16 (0x00000004)
#define NETARM_ENI_GCR_ENIMODE_SHRAM8 (0x00000005)
#define NETARM_ENI_GCR_ENIMODE_FIFO16 (0x00000006)
#define NETARM_ENI_GCR_ENIMODE_FIFO8 (0x00000007)
#define NETARM_ENI_GCR_ENIMODE_MASK (0x00000007)
/* IEEE 1284 Port Control Registers 1-4 (0xFFA0_0010, 0xFFA0_0014,
0xFFA0_0018, 0xFFA0_001c) */
#define NETARM_ENI_1284PC_PORT_ENABLE (0x80000000)
#define NETARM_ENI_1284PC_DMA_ENABLE (0x40000000)
#define NETARM_ENI_1284PC_OBE_INT_EN (0x20000000)
#define NETARM_ENI_1284PC_ACK_INT_EN (0x10000000)
#define NETARM_ENI_1284PC_ECP_MODE (0x08000000)
#define NETARM_ENI_1284PC_LOOPBACK_MODE (0x04000000)
#define NETARM_ENI_1284PC_STROBE_TIME0 (0x00000000) /* 0.5 uS */
#define NETARM_ENI_1284PC_STROBE_TIME1 (0x01000000) /* 1.0 uS */
#define NETARM_ENI_1284PC_STROBE_TIME2 (0x02000000) /* 5.0 uS */
#define NETARM_ENI_1284PC_STROBE_TIME3 (0x03000000) /* 10.0 uS */
#define NETARM_ENI_1284PC_STROBE_MASK (0x03000000)
#define NETARM_ENI_1284PC_MAN_STROBE_EN (0x00800000)
#define NETARM_ENI_1284PC_FAST_MODE (0x00400000)
#define NETARM_ENI_1284PC_BIDIR_MODE (0x00200000)
#define NETARM_ENI_1284PC_MAN_STROBE (0x00080000)
#define NETARM_ENI_1284PC_AUTO_FEED (0x00040000)
#define NETARM_ENI_1284PC_INIT (0x00020000)
#define NETARM_ENI_1284PC_HSELECT (0x00010000)
#define NETARM_ENI_1284PC_FE_INT_EN (0x00008000)
#define NETARM_ENI_1284PC_EPP_MODE (0x00004000)
#define NETARM_ENI_1284PC_IBR_INT_EN (0x00002000)
#define NETARM_ENI_1284PC_IBR (0x00001000)
#define NETARM_ENI_1284PC_RXFDB_1BYTE (0x00000400)
#define NETARM_ENI_1284PC_RXFDB_2BYTE (0x00000800)
#define NETARM_ENI_1284PC_RXFDB_3BYTE (0x00000c00)
#define NETARM_ENI_1284PC_RXFDB_4BYTE (0x00000000)
#define NETARM_ENI_1284PC_RBCC (0x00000200)
#define NETARM_ENI_1284PC_RBCT (0x00000100)
#define NETARM_ENI_1284PC_ACK (0x00000080)
#define NETARM_ENI_1284PC_FIFO_E (0x00000040)
#define NETARM_ENI_1284PC_OBE (0x00000020)
#define NETARM_ENI_1284PC_ACK_INT (0x00000010)
#define NETARM_ENI_1284PC_BUSY (0x00000008)
#define NETARM_ENI_1284PC_PE (0x00000004)
#define NETARM_ENI_1284PC_PSELECT (0x00000002)
#define NETARM_ENI_1284PC_FAULT (0x00000001)
#endif /* __NETARM_ENI_MODULE_REGISTERS_H */

160
arch/arm/include/asm/arch-arm720t/netarm_eth_module.h
View File

@ -1,160 +0,0 @@
/*
* include/asm-armnommu/arch-netarm/netarm_eth_module.h
*
* Copyright (C) 2000 NETsilicon, Inc.
* Copyright (C) 2000 WireSpeed Communications Corporation
*
* This software is copyrighted by WireSpeed. LICENSEE agrees that
* it will not delete this copyright notice, trademarks or protective
* notices from any copy made by LICENSEE.
*
* This software is provided "AS-IS" and any express or implied
* warranties or conditions, including but not limited to any
* implied warranties of merchantability and fitness for a particular
* purpose regarding this software. In no event shall WireSpeed
* be liable for any indirect, consequential, or incidental damages,
* loss of profits or revenue, loss of use or data, or interruption
* of business, whether the alleged damages are labeled in contract,
* tort, or indemnity.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
* author(s) : Jackie Smith Cashion
* David Smith
*/
#ifndef __NETARM_ETH_MODULE_REGISTERS_H
#define __NETARM_ETH_MODULE_REGISTERS_H
/* ETH unit register offsets */
#define NETARM_ETH_MODULE_BASE (0xFF800000)
#define get_eth_reg_addr(c) ((volatile unsigned int *)(NETARM_ETH_MODULE_BASE + (c)))
#define NETARM_ETH_GEN_CTRL (0x000) /* Ethernet Gen Control Reg */
#define NETARM_ETH_GEN_STAT (0x004) /* Ethernet Gen Status Reg */
#define NETARM_ETH_FIFO_DAT1 (0x008) /* Fifo Data Reg 1 */
#define NETARM_ETH_FIFO_DAT2 (0x00C) /* Fifo Data Reg 2 */
#define NETARM_ETH_TX_STAT (0x010) /* Transmit Status Reg */
#define NETARM_ETH_RX_STAT (0x014) /* Receive Status Reg */
#define NETARM_ETH_MAC_CFG (0x400) /* MAC Configuration Reg */
#define NETARM_ETH_PCS_CFG (0x408) /* PCS Configuration Reg */
#define NETARM_ETH_STL_CFG (0x410) /* STL Configuration Reg */
#define NETARM_ETH_B2B_IPG_GAP_TMR (0x440) /* Back-to-back IPG
Gap Timer Reg */
#define NETARM_ETH_NB2B_IPG_GAP_TMR (0x444) /* Non Back-to-back
IPG Gap Timer Reg */
#define NETARM_ETH_MII_CMD (0x540) /* MII (PHY) Command Reg */
#define NETARM_ETH_MII_ADDR (0x544) /* MII Address Reg */
#define NETARM_ETH_MII_WRITE (0x548) /* MII Write Data Reg */
#define NETARM_ETH_MII_READ (0x54C) /* MII Read Data Reg */
#define NETARM_ETH_MII_IND (0x550) /* MII Indicators Reg */
#define NETARM_ETH_MIB_CRCEC (0x580) /* (MIB) CRC Error Counter */
#define NETARM_ETH_MIB_AEC (0x584) /* Alignment Error Counter */
#define NETARM_ETH_MIB_CEC (0x588) /* Code Error Counter */
#define NETARM_ETH_MIB_LFC (0x58C) /* Long Frame Counter */
#define NETARM_ETH_MIB_SFC (0x590) /* Short Frame Counter */
#define NETARM_ETH_MIB_LCC (0x594) /* Late Collision Counter */
#define NETARM_ETH_MIB_EDC (0x598) /* Excessive Deferral
Counter */
#define NETARM_ETH_MIB_MCC (0x59C) /* Maximum Collision Counter */
#define NETARM_ETH_SAL_FILTER (0x5C0) /* SAL Station Address
Filter Reg */
#define NETARM_ETH_SAL_STATION_ADDR_1 (0x5C4) /* SAL Station Address
Reg */
#define NETARM_ETH_SAL_STATION_ADDR_2 (0x5C8)
#define NETARM_ETH_SAL_STATION_ADDR_3 (0x5CC)
#define NETARM_ETH_SAL_HASH_TBL_1 (0x5D0) /* SAL Multicast Hash Table*/
#define NETARM_ETH_SAL_HASH_TBL_2 (0x5D4)
#define NETARM_ETH_SAL_HASH_TBL_3 (0x5D8)
#define NETARM_ETH_SAL_HASH_TBL_4 (0x5DC)
/* select bitfield defintions */
/* Ethernet General Control Register (0xFF80_0000) */
#define NETARM_ETH_GCR_ERX (0x80000000) /* Enable Receive FIFO */
#define NETARM_ETH_GCR_ERXDMA (0x40000000) /* Enable Receive DMA */
#define NETARM_ETH_GCR_ETX (0x00800000) /* Enable Transmit FIFO */
#define NETARM_ETH_GCR_ETXDMA (0x00400000) /* Enable Transmit DMA */
#define NETARM_ETH_GCR_ETXWM_50 (0x00100000) /* Transmit FIFO Water
Mark. Start transmit
when FIFO is 50%
full. */
#define NETARM_ETH_GCR_PNA (0x00000400) /* pSOS pNA Buffer
Descriptor Format */
/* Ethernet General Status Register (0xFF80_0004) */
#define NETARM_ETH_GST_RXFDB (0x30000000)
#define NETARM_ETH_GST_RXREGR (0x08000000) /* Receive Register
Ready */
#define NETARM_ETH_GST_RXFIFOH (0x04000000)
#define NETARM_ETH_GST_RXBR (0x02000000)
#define NETARM_ETH_GST_RXSKIP (0x01000000)
#define NETARM_ETH_GST_TXBC (0x00020000)
/* Ethernet Transmit Status Register (0xFF80_0010) */
#define NETARM_ETH_TXSTAT_TXOK (0x00008000)
/* Ethernet Receive Status Register (0xFF80_0014) */
#define NETARM_ETH_RXSTAT_SIZE (0xFFFF0000)
#define NETARM_ETH_RXSTAT_RXOK (0x00002000)
/* PCS Configuration Register (0xFF80_0408) */
#define NETARM_ETH_PCSC_NOCFR (0x1) /* Disable Ciphering */
#define NETARM_ETH_PCSC_ENJAB (0x2) /* Enable Jabber Protection */
#define NETARM_ETH_PCSC_CLKS_25M (0x0) /* 25 MHz Clock Speed Select */
#define NETARM_ETH_PCSC_CLKS_33M (0x4) /* 33 MHz Clock Speed Select */
/* STL Configuration Register (0xFF80_0410) */
#define NETARM_ETH_STLC_RXEN (0x2) /* Enable Packet Receiver */
#define NETARM_ETH_STLC_AUTOZ (0x4) /* Auto Zero Statistics */
/* MAC Configuration Register (0xFF80_0400) */
#define NETARM_ETH_MACC_HUGEN (0x1) /* Enable Unlimited Transmit
Frame Sizes */
#define NETARM_ETH_MACC_PADEN (0x4) /* Automatic Pad Fill Frames
to 64 Bytes */
#define NETARM_ETH_MACC_CRCEN (0x8) /* Append CRC to Transmit
Frames */
/* MII (PHY) Command Register (0xFF80_0540) */
#define NETARM_ETH_MIIC_RSTAT (0x1) /* Single Scan for Read Data */
/* MII Indicators Register (0xFF80_0550) */
#define NETARM_ETH_MIII_BUSY (0x1) /* MII I/F Busy with
Read/Write */
/* SAL Station Address Filter Register (0xFF80_05C0) */
#define NETARM_ETH_SALF_PRO (0x8) /* Enable Promiscuous Mode */
#define NETARM_ETH_SALF_PRM (0x4) /* Accept All Multicast
Packets */
#define NETARM_ETH_SALF_PRA (0x2) /* Accept Mulitcast Packets
using Hash Table */
#define NETARM_ETH_SALF_BROAD (0x1) /* Accept All Broadcast
Packets */
#endif /* __NETARM_GEN_MODULE_REGISTERS_H */

186
arch/arm/include/asm/arch-arm720t/netarm_gen_module.h
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@ -1,186 +0,0 @@
/*
* include/asm-armnommu/arch-netarm/netarm_gen_module.h
*
* Copyright (C) 2005
* Art Shipkowski, Videon Central, Inc., <art@videon-central.com>
*
* Copyright (C) 2000, 2001 NETsilicon, Inc.
* Copyright (C) 2000, 2001 Red Hat, Inc.
*
* This software is copyrighted by Red Hat. LICENSEE agrees that
* it will not delete this copyright notice, trademarks or protective
* notices from any copy made by LICENSEE.
*
* This software is provided "AS-IS" and any express or implied
* warranties or conditions, including but not limited to any
* implied warranties of merchantability and fitness for a particular
* purpose regarding this software. In no event shall Red Hat
* be liable for any indirect, consequential, or incidental damages,
* loss of profits or revenue, loss of use or data, or interruption
* of business, whether the alleged damages are labeled in contract,
* tort, or indemnity.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
* author(s) : Joe deBlaquiere
*
* Modified to support NS7520 by Art Shipkowski.
*/
#ifndef __NETARM_GEN_MODULE_REGISTERS_H
#define __NETARM_GEN_MODULE_REGISTERS_H
/* GEN unit register offsets */
#define NETARM_GEN_MODULE_BASE (0xFFB00000)
#define get_gen_reg_addr(c) ((volatile unsigned int *)(NETARM_GEN_MODULE_BASE + (c)))
#define NETARM_GEN_SYSTEM_CONTROL (0x00)
#define NETARM_GEN_STATUS_CONTROL (0x04)
#define NETARM_GEN_PLL_CONTROL (0x08)
#define NETARM_GEN_SOFTWARE_SERVICE (0x0c)
#define NETARM_GEN_TIMER1_CONTROL (0x10)
#define NETARM_GEN_TIMER1_STATUS (0x14)
#define NETARM_GEN_TIMER2_CONTROL (0x18)
#define NETARM_GEN_TIMER2_STATUS (0x1c)
#define NETARM_GEN_PORTA (0x20)
#ifndef CONFIG_NETARM_NS7520
#define NETARM_GEN_PORTB (0x24)
#endif
#define NETARM_GEN_PORTC (0x28)
#define NETARM_GEN_INTR_ENABLE (0x30)
#define NETARM_GEN_INTR_ENABLE_SET (0x34)
#define NETARM_GEN_INTR_ENABLE_CLR (0x38)
#define NETARM_GEN_INTR_STATUS_EN (0x34)
#define NETARM_GEN_INTR_STATUS_RAW (0x38)
#define NETARM_GEN_CACHE_CONTROL1 (0x40)
#define NETARM_GEN_CACHE_CONTROL2 (0x44)
/* select bitfield definitions */
/* System Control Register ( 0xFFB0_0000 ) */
#define NETARM_GEN_SYS_CFG_LENDIAN (0x80000000)
#define NETARM_GEN_SYS_CFG_BENDIAN (0x00000000)
#define NETARM_GEN_SYS_CFG_BUSQRTR (0x00000000)
#define NETARM_GEN_SYS_CFG_BUSHALF (0x20000000)
#define NETARM_GEN_SYS_CFG_BUSFULL (0x40000000)
#define NETARM_GEN_SYS_CFG_BCLK_DISABLE (0x10000000)
#define NETARM_GEN_SYS_CFG_WDOG_EN (0x01000000)
#define NETARM_GEN_SYS_CFG_WDOG_IRQ (0x00000000)
#define NETARM_GEN_SYS_CFG_WDOG_FIQ (0x00400000)
#define NETARM_GEN_SYS_CFG_WDOG_RST (0x00800000)
#define NETARM_GEN_SYS_CFG_WDOG_24 (0x00000000)
#define NETARM_GEN_SYS_CFG_WDOG_26 (0x00100000)
#define NETARM_GEN_SYS_CFG_WDOG_28 (0x00200000)
#define NETARM_GEN_SYS_CFG_WDOG_29 (0x00300000)
#define NETARM_GEN_SYS_CFG_BUSMON_EN (0x00040000)
#define NETARM_GEN_SYS_CFG_BUSMON_128 (0x00000000)
#define NETARM_GEN_SYS_CFG_BUSMON_64 (0x00010000)
#define NETARM_GEN_SYS_CFG_BUSMON_32 (0x00020000)
#define NETARM_GEN_SYS_CFG_BUSMON_16 (0x00030000)
#define NETARM_GEN_SYS_CFG_USER_EN (0x00008000)
#define NETARM_GEN_SYS_CFG_BUSER_EN (0x00004000)
#define NETARM_GEN_SYS_CFG_BUSARB_INT (0x00002000)
#define NETARM_GEN_SYS_CFG_BUSARB_EXT (0x00000000)
#define NETARM_GEN_SYS_CFG_DMATST (0x00001000)
#define NETARM_GEN_SYS_CFG_TEALAST (0x00000800)
#define NETARM_GEN_SYS_CFG_ALIGN_ABORT (0x00000400)
#define NETARM_GEN_SYS_CFG_CACHE_EN (0x00000200)
#define NETARM_GEN_SYS_CFG_WRI_BUF_EN (0x00000100)
#define NETARM_GEN_SYS_CFG_CACHE_INIT (0x00000080)
/* PLL Control Register ( 0xFFB0_0008 ) */
#define NETARM_GEN_PLL_CTL_PLLCNT_MASK (0x0F000000)
#define NETARM_GEN_PLL_CTL_PLLCNT(x) (((x)<<24) & \
NETARM_GEN_PLL_CTL_PLLCNT_MASK)
/* Defaults for POLTST and ICP Fields in PLL CTL */
#define NETARM_GEN_PLL_CTL_OUTDIV(x) (x)
#define NETARM_GEN_PLL_CTL_INDIV(x) ((x)<<6)
#define NETARM_GEN_PLL_CTL_POLTST_DEF (0x00000E00)
#define NETARM_GEN_PLL_CTL_ICP_DEF (0x0000003C)
/* Software Service Register ( 0xFFB0_000C ) */
#define NETARM_GEN_SW_SVC_RESETA (0x123)
#define NETARM_GEN_SW_SVC_RESETB (0x321)
/* PORT C Register ( 0xFFB0_0028 ) */
#ifndef CONFIG_NETARM_NS7520
#define NETARM_GEN_PORT_MODE(x) (((x)<<24) + (0xFF00))
#define NETARM_GEN_PORT_DIR(x) (((x)<<16) + (0xFF00))
#else
#define NETARM_GEN_PORT_MODE(x) ((x)<<24)
#define NETARM_GEN_PORT_DIR(x) ((x)<<16)
#define NETARM_GEN_PORT_CSF(x) ((x)<<8)
#endif
/* Timer Registers ( 0xFFB0_0010 0xFFB0_0018 ) */
#define NETARM_GEN_TCTL_ENABLE (0x80000000)
#define NETARM_GEN_TCTL_INT_ENABLE (0x40000000)
#define NETARM_GEN_TCTL_USE_IRQ (0x00000000)
#define NETARM_GEN_TCTL_USE_FIQ (0x20000000)
#define NETARM_GEN_TCTL_USE_PRESCALE (0x10000000)
#define NETARM_GEN_TCTL_INIT_COUNT(x) ((x) & 0x1FF)
#define NETARM_GEN_TSTAT_INTPEN (0x40000000)
#if ~defined(CONFIG_NETARM_NS7520)
#define NETARM_GEN_TSTAT_CTC_MASK (0x000001FF)
#else
#define NETARM_GEN_TSTAT_CTC_MASK (0x0FFFFFFF)
#endif
/* prescale to msecs conversion */
#if !defined(CONFIG_NETARM_PLL_BYPASS)
#define NETARM_GEN_TIMER_MSEC_P(x) ( ( ( 20480 ) * ( 0x1FF - ( (x) & \
NETARM_GEN_TSTAT_CTC_MASK ) + \
1 ) ) / (NETARM_XTAL_FREQ/1000) )
#define NETARM_GEN_TIMER_SET_HZ(x) ( ( ((NETARM_XTAL_FREQ/(20480*(x)))-1) & \
NETARM_GEN_TSTAT_CTC_MASK ) | \
NETARM_GEN_TCTL_USE_PRESCALE )
#else
#define NETARM_GEN_TIMER_MSEC_P(x) ( ( ( 4096 ) * ( 0x1FF - ( (x) & \
NETARM_GEN_TSTAT_CTC_MASK ) + \
1 ) ) / (NETARM_XTAL_FREQ/1000) )
#define NETARM_GEN_TIMER_SET_HZ(x) ( ( ((NETARM_XTAL_FREQ/(4096*(x)))-1) & \
NETARM_GEN_TSTAT_CTC_MASK ) | \
NETARM_GEN_TCTL_USE_PRESCALE )
#endif
#endif

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/*
* include/asm-armnommu/arch-netarm/netarm_mem_module.h
*
* Copyright (C) 2005
* Art Shipkowski, Videon Central, Inc., <art@videon-central.com>
*
* Copyright (C) 2000, 2001 NETsilicon, Inc.
* Copyright (C) 2000, 2001 Red Hat, Inc.
*
* This software is copyrighted by Red Hat. LICENSEE agrees that
* it will not delete this copyright notice, trademarks or protective
* notices from any copy made by LICENSEE.
*
* This software is provided "AS-IS" and any express or implied
* warranties or conditions, including but not limited to any
* implied warranties of merchantability and fitness for a particular
* purpose regarding this software. In no event shall Red Hat
* be liable for any indirect, consequential, or incidental damages,
* loss of profits or revenue, loss of use or data, or interruption
* of business, whether the alleged damages are labeled in contract,
* tort, or indemnity.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
* author(s) : Joe deBlaquiere
*
* Modified to support NS7520 by Art Shipkowski.
*/
#ifndef __NETARM_MEM_MODULE_REGISTERS_H
#define __NETARM_MEM_MODULE_REGISTERS_H
/* GEN unit register offsets */
#define NETARM_MEM_MODULE_BASE (0xFFC00000)
#define NETARM_MEM_MODULE_CONFIG (0x00)
#define NETARM_MEM_CS0_BASE_ADDR (0x10)
#define NETARM_MEM_CS0_OPTIONS (0x14)
#define NETARM_MEM_CS1_BASE_ADDR (0x20)
#define NETARM_MEM_CS1_OPTIONS (0x24)
#define NETARM_MEM_CS2_BASE_ADDR (0x30)
#define NETARM_MEM_CS2_OPTIONS (0x34)
#define NETARM_MEM_CS3_BASE_ADDR (0x40)
#define NETARM_MEM_CS3_OPTIONS (0x44)
#define NETARM_MEM_CS4_BASE_ADDR (0x50)
#define NETARM_MEM_CS4_OPTIONS (0x54)
/* select bitfield defintions */
/* Module Configuration Register ( 0xFFC0_0000 ) */
#define NETARM_MEM_CFG_REFR_COUNT_MASK (0xFF000000)
#define NETARM_MEM_CFG_REFRESH_EN (0x00800000)
#define NETARM_MEM_CFG_REFR_CYCLE_8CLKS (0x00000000)
#define NETARM_MEM_CFG_REFR_CYCLE_6CLKS (0x00200000)
#define NETARM_MEM_CFG_REFR_CYCLE_5CLKS (0x00400000)
#define NETARM_MEM_CFG_REFR_CYCLE_4CLKS (0x00600000)
#define NETARM_MEM_CFG_PORTC_AMUX (0x00100000)
#define NETARM_MEM_CFG_A27_ADDR (0x00080000)
#define NETARM_MEM_CFG_A27_CS0OE (0x00000000)
#define NETARM_MEM_CFG_A26_ADDR (0x00040000)
#define NETARM_MEM_CFG_A26_CS0WE (0x00000000)
#define NETARM_MEM_CFG_A25_ADDR (0x00020000)
#define NETARM_MEM_CFG_A25_BLAST (0x00000000)
#define NETARM_MEM_CFG_PORTC_AMUX2 (0x00010000)
/* range on this period is about 1 to 275 usec (with 18.432MHz clock) */
/* the expression will round down, so make sure to reverse it to verify */
/* it is what you want. period = [( count + 1 ) * 20] / Fcrystal */
/* (note: Fxtal = Fcrystal/5, see HWRefGuide sections 8.2.5 and 11.3.2) */
#define NETARM_MEM_REFR_PERIOD_USEC(p) (NETARM_MEM_CFG_REFR_COUNT_MASK & \
(((((NETARM_XTAL_FREQ/(1000))*p)/(20000) \
) - (1) ) << (24)))
#if 0
/* range on this period is about 1 to 275 usec (with 18.432MHz clock) */
/* the expression will round down, so make sure to reverse it toverify */
/* it is what you want. period = [( count + 1 ) * 4] / Fxtal */
#define NETARM_MEM_REFR_PERIOD_USEC(p) (NETARM_MEM_CFG_REFR_COUNT_MASK & \
(((((NETARM_XTAL_FREQ/(1000))*p)/(4000) \
) - (1) ) << (24)))
#endif
/* Base Address Registers (0xFFC0_00X0) */
#define NETARM_MEM_BAR_BASE_MASK (0xFFFFF000)
/* macro to define base */
#define NETARM_MEM_BAR_BASE(x) ((x) & NETARM_MEM_BAR_BASE_MASK)
#define NETARM_MEM_BAR_DRAM_FP (0x00000000)
#define NETARM_MEM_BAR_DRAM_EDO (0x00000100)
#define NETARM_MEM_BAR_DRAM_SYNC (0x00000200)
#define NETARM_MEM_BAR_DRAM_MUX_INT (0x00000000)
#define NETARM_MEM_BAR_DRAM_MUX_EXT (0x00000080)
#define NETARM_MEM_BAR_DRAM_MUX_BAL (0x00000000)
#define NETARM_MEM_BAR_DRAM_MUX_UNBAL (0x00000020)
#define NETARM_MEM_BAR_1BCLK_IDLE (0x00000010)
#define NETARM_MEM_BAR_DRAM_SEL (0x00000008)
#define NETARM_MEM_BAR_BURST_EN (0x00000004)
#define NETARM_MEM_BAR_WRT_PROT (0x00000002)
#define NETARM_MEM_BAR_VALID (0x00000001)
/* Option Registers (0xFFC0_00X4) */
/* macro to define which bits of the base are significant */
#define NETARM_MEM_OPT_BASE_USE(x) ((x) & NETARM_MEM_BAR_BASE_MASK)
#define NETARM_MEM_OPT_WAIT_MASK (0x00000F00)
#define NETARM_MEM_OPT_WAIT_STATES(x) (((x) << 8 ) & NETARM_MEM_OPT_WAIT_MASK )
#define NETARM_MEM_OPT_BCYC_1 (0x00000000)
#define NETARM_MEM_OPT_BCYC_2 (0x00000040)
#define NETARM_MEM_OPT_BCYC_3 (0x00000080)
#define NETARM_MEM_OPT_BCYC_4 (0x000000C0)
#define NETARM_MEM_OPT_BSIZE_2 (0x00000000)
#define NETARM_MEM_OPT_BSIZE_4 (0x00000010)
#define NETARM_MEM_OPT_BSIZE_8 (0x00000020)
#define NETARM_MEM_OPT_BSIZE_16 (0x00000030)
#define NETARM_MEM_OPT_32BIT (0x00000000)
#define NETARM_MEM_OPT_16BIT (0x00000004)
#define NETARM_MEM_OPT_8BIT (0x00000008)
#define NETARM_MEM_OPT_32BIT_EXT_ACK (0x0000000C)
#define NETARM_MEM_OPT_BUS_SIZE_MASK (0x0000000C)
#define NETARM_MEM_OPT_READ_ASYNC (0x00000000)
#define NETARM_MEM_OPT_READ_SYNC (0x00000002)
#define NETARM_MEM_OPT_WRITE_ASYNC (0x00000000)
#define NETARM_MEM_OPT_WRITE_SYNC (0x00000001)
#ifdef CONFIG_NETARM_NS7520
/* The NS7520 has a second options register for each chip select */
#define NETARM_MEM_CS0_OPTIONS_B (0x18)
#define NETARM_MEM_CS1_OPTIONS_B (0x28)
#define NETARM_MEM_CS2_OPTIONS_B (0x38)
#define NETARM_MEM_CS3_OPTIONS_B (0x48)
#define NETARM_MEM_CS4_OPTIONS_B (0x58)
/* Option B Registers (0xFFC0_00x8) */
#define NETARM_MEM_OPTB_SYNC_1_STAGE (0x00000001)
#define NETARM_MEM_OPTB_SYNC_2_STAGE (0x00000002)
#define NETARM_MEM_OPTB_BCYC_PLUS0 (0x00000000)
#define NETARM_MEM_OPTB_BCYC_PLUS4 (0x00000004)
#define NETARM_MEM_OPTB_BCYC_PLUS8 (0x00000008)
#define NETARM_MEM_OPTB_BCYC_PLUS12 (0x0000000C)
#define NETARM_MEM_OPTB_WAIT_PLUS0 (0x00000000)
#define NETARM_MEM_OPTB_WAIT_PLUS16 (0x00000010)
#define NETARM_MEM_OPTB_WAIT_PLUS32 (0x00000020)
#define NETARM_MEM_OPTB_WAIT_PLUS48 (0x00000030)
#endif
#endif

96
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/*
* linux/include/asm-arm/arch-netarm/netarm_registers.h
*
* Copyright (C) 2005
* Art Shipkowski, Videon Central, Inc., <art@videon-central.com>
*
* Copyright (C) 2000, 2001 NETsilicon, Inc.
* Copyright (C) 2000, 2001 WireSpeed Communications Corporation
*
* This software is copyrighted by WireSpeed. LICENSEE agrees that
* it will not delete this copyright notice, trademarks or protective
* notices from any copy made by LICENSEE.
*
* This software is provided "AS-IS" and any express or implied
* warranties or conditions, including but not limited to any
* implied warranties of merchantability and fitness for a particular
* purpose regarding this software. In no event shall WireSpeed
* be liable for any indirect, consequential, or incidental damages,
* loss of profits or revenue, loss of use or data, or interruption
* of business, whether the alleged damages are labeled in contract,
* tort, or indemnity.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
* author(s) : Joe deBlaquiere
*
* Modified to support NS7520 by Art Shipkowski.
*/
#ifndef __NET_ARM_REGISTERS_H
#define __NET_ARM_REGISTERS_H
#include <config.h>
/* fundamental constants : */
/* the input crystal/clock frequency ( in Hz ) */
#define NETARM_XTAL_FREQ_25MHz (18432000)
#define NETARM_XTAL_FREQ_33MHz (23698000)
#define NETARM_XTAL_FREQ_48MHz (48000000)
#define NETARM_XTAL_FREQ_55MHz (55000000)
#define NETARM_XTAL_FREQ_EMLIN1 (20000000)
/* the frequency of SYS_CLK */
#if defined(CONFIG_NETARM_EMLIN)
/* EMLIN board: 33 MHz (exp.) */
#define NETARM_PLL_COUNT_VAL 6
#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz
#elif defined(CONFIG_NETARM_NET40_REV2)
/* NET+40 Rev2 boards: 33 MHz (with NETARM_XTAL_FREQ_25MHz) */
#define NETARM_PLL_COUNT_VAL 6
#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz
#elif defined(CONFIG_NETARM_NET40_REV4)
/* NET+40 Rev4 boards with EDO must clock slower: 25 MHz (with
NETARM_XTAL_FREQ_25MHz) 4 */
#define NETARM_PLL_COUNT_VAL 4
#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz
#elif defined(CONFIG_NETARM_NET50)
/* NET+50 boards: 40 MHz (with NETARM_XTAL_FREQ_25MHz) */
#define NETARM_PLL_COUNT_VAL 8
#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_25MHz
#else /* CONFIG_NETARM_NS7520 */
#define NETARM_PLL_COUNT_VAL 0
#if defined(CONFIG_BOARD_UNC20)
#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_48MHz
#else
#define NETARM_XTAL_FREQ NETARM_XTAL_FREQ_55MHz
#endif
#endif
/* #include "arm_registers.h" */
#include <asm/arch/netarm_gen_module.h>
#include <asm/arch/netarm_mem_module.h>
#include <asm/arch/netarm_ser_module.h>
#include <asm/arch/netarm_eni_module.h>
#include <asm/arch/netarm_dma_module.h>
#include <asm/arch/netarm_eth_module.h>
#endif

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/*
* linux/include/asm-arm/arch-netarm/netarm_ser_module.h
*
* Copyright (C) 2000 NETsilicon, Inc.
* Copyright (C) 2000 Red Hat, Inc.
*
* This software is copyrighted by Red Hat. LICENSEE agrees that
* it will not delete this copyright notice, trademarks or protective
* notices from any copy made by LICENSEE.
*
* This software is provided "AS-IS" and any express or implied
* warranties or conditions, including but not limited to any
* implied warranties of merchantability and fitness for a particular
* purpose regarding this software. In no event shall Red Hat
* be liable for any indirect, consequential, or incidental damages,
* loss of profits or revenue, loss of use or data, or interruption
* of business, whether the alleged damages are labeled in contract,
* tort, or indemnity.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
* author(s) : Joe deBlaquiere
* Clark Williams
*/
#ifndef __NETARM_SER_MODULE_REGISTERS_H
#define __NETARM_SER_MODULE_REGISTERS_H
#ifndef __ASSEMBLER__
/* (--sub)#include "types.h" */
/* serial channel control structure */
typedef struct {
u32 ctrl_a;
u32 ctrl_b;
u32 status_a;
u32 bitrate;
u32 fifo;
u32 rx_buf_timer;
u32 rx_char_timer;
u32 rx_match;
u32 rx_match_mask;
u32 ctrl_c;
u32 status_b;
u32 status_c;
u32 fifo_last;
u32 unused[3];
} netarm_serial_channel_t;
#endif
/* SER unit register offsets */
/* #ifdef CONFIG_ARCH_NETARM */
#define NETARM_SER_MODULE_BASE (0xFFD00000)
/* #else */
/* extern serial_channel_t netarm_dummy_registers[]; */
/* #define NETARM_SER_MODULE_BASE (netarm_dummy_registers) */
/* #ifndef NETARM_XTAL_FREQ */
/* #define NETARM_XTAL_FREQ 18432000 */
/* #endif */
/* #endif */
/* calculate the sysclk value from the pll setting */
#define NETARM_PLLED_SYSCLK_FREQ (( NETARM_XTAL_FREQ / 5 ) * \
( NETARM_PLL_COUNT_VAL + 3 ))
#define get_serial_channel(c) (&(((netarm_serial_channel_t *)NETARM_SER_MODULE_BASE)[c]))
#define NETARM_SER_CH1_CTRL_A (0x00)
#define NETARM_SER_CH1_CTRL_B (0x04)
#define NETARM_SER_CH1_STATUS_A (0x08)
#define NETARM_SER_CH1_BITRATE (0x0C)
#define NETARM_SER_CH1_FIFO (0x10)
#define NETARM_SER_CH1_RX_BUF_TMR (0x14)
#define NETARM_SER_CH1_RX_CHAR_TMR (0x18)
#define NETARM_SER_CH1_RX_MATCH (0x1c)
#define NETARM_SER_CH1_RX_MATCH_MASK (0x20)
#define NETARM_SER_CH1_CTRL_C (0x24)
#define NETARM_SER_CH1_STATUS_B (0x28)
#define NETARM_SER_CH1_STATUS_C (0x2c)
#define NETARM_SER_CH1_FIFO_LAST (0x30)
#define NETARM_SER_CH2_CTRL_A (0x40)
#define NETARM_SER_CH2_CTRL_B (0x44)
#define NETARM_SER_CH2_STATUS_A (0x48)
#define NETARM_SER_CH2_BITRATE (0x4C)
#define NETARM_SER_CH2_FIFO (0x50)
#define NETARM_SER_CH2_RX_BUF_TMR (0x54)
#define NETARM_SER_CH2_RX_CHAR_TMR (0x58)
#define NETARM_SER_CH2_RX_MATCH (0x5c)
#define NETARM_SER_CH2_RX_MATCH_MASK (0x60)
#define NETARM_SER_CH2_CTRL_C (0x64)
#define NETARM_SER_CH2_STATUS_B (0x68)
#define NETARM_SER_CH2_STATUS_C (0x6c)
#define NETARM_SER_CH2_FIFO_LAST (0x70)
/* select bitfield defintions */
/* Control Register A */
#define NETARM_SER_CTLA_ENABLE (0x80000000)
#define NETARM_SER_CTLA_BRK (0x40000000)
#define NETARM_SER_CTLA_STICKP (0x20000000)
#define NETARM_SER_CTLA_P_EVEN (0x18000000)
#define NETARM_SER_CTLA_P_ODD (0x08000000)
#define NETARM_SER_CTLA_P_NONE (0x00000000)
/* if you read the errata, you will find that the STOP bits don't work right */
#define NETARM_SER_CTLA_2STOP (0x00000000)
#define NETARM_SER_CTLA_3STOP (0x04000000)
#define NETARM_SER_CTLA_5BITS (0x00000000)
#define NETARM_SER_CTLA_6BITS (0x01000000)
#define NETARM_SER_CTLA_7BITS (0x02000000)
#define NETARM_SER_CTLA_8BITS (0x03000000)
#define NETARM_SER_CTLA_CTSTX (0x00800000)
#define NETARM_SER_CTLA_RTSRX (0x00400000)
#define NETARM_SER_CTLA_LOOP_REM (0x00200000)
#define NETARM_SER_CTLA_LOOP_LOC (0x00100000)
#define NETARM_SER_CTLA_GPIO2 (0x00080000)
#define NETARM_SER_CTLA_GPIO1 (0x00040000)
#define NETARM_SER_CTLA_DTR_EN (0x00020000)
#define NETARM_SER_CTLA_RTS_EN (0x00010000)
#define NETARM_SER_CTLA_IE_RX_BRK (0x00008000)
#define NETARM_SER_CTLA_IE_RX_FRMERR (0x00004000)
#define NETARM_SER_CTLA_IE_RX_PARERR (0x00002000)
#define NETARM_SER_CTLA_IE_RX_OVERRUN (0x00001000)
#define NETARM_SER_CTLA_IE_RX_RDY (0x00000800)
#define NETARM_SER_CTLA_IE_RX_HALF (0x00000400)
#define NETARM_SER_CTLA_IE_RX_FULL (0x00000200)
#define NETARM_SER_CTLA_IE_RX_DMAEN (0x00000100)
#define NETARM_SER_CTLA_IE_RX_DCD (0x00000080)
#define NETARM_SER_CTLA_IE_RX_RI (0x00000040)
#define NETARM_SER_CTLA_IE_RX_DSR (0x00000020)
#define NETARM_SER_CTLA_IE_RX_ALL (NETARM_SER_CTLA_IE_RX_BRK \
|NETARM_SER_CTLA_IE_RX_FRMERR \
|NETARM_SER_CTLA_IE_RX_PARERR \
|NETARM_SER_CTLA_IE_RX_OVERRUN \
|NETARM_SER_CTLA_IE_RX_RDY \
|NETARM_SER_CTLA_IE_RX_HALF \
|NETARM_SER_CTLA_IE_RX_FULL \
|NETARM_SER_CTLA_IE_RX_DMAEN \
|NETARM_SER_CTLA_IE_RX_DCD \
|NETARM_SER_CTLA_IE_RX_RI \
|NETARM_SER_CTLA_IE_RX_DSR)
#define NETARM_SER_CTLA_IE_TX_CTS (0x00000010)
#define NETARM_SER_CTLA_IE_TX_EMPTY (0x00000008)
#define NETARM_SER_CTLA_IE_TX_HALF (0x00000004)
#define NETARM_SER_CTLA_IE_TX_FULL (0x00000002)
#define NETARM_SER_CTLA_IE_TX_DMAEN (0x00000001)
#define NETARM_SER_CTLA_IE_TX_ALL (NETARM_SER_CTLA_IE_TX_CTS \
|NETARM_SER_CTLA_IE_TX_EMPTY \
|NETARM_SER_CTLA_IE_TX_HALF \
|NETARM_SER_CTLA_IE_TX_FULL \
|NETARM_SER_CTLA_IE_TX_DMAEN)
/* Control Register B */
#define NETARM_SER_CTLB_MATCH1_EN (0x80000000)
#define NETARM_SER_CTLB_MATCH2_EN (0x40000000)
#define NETARM_SER_CTLB_MATCH3_EN (0x20000000)
#define NETARM_SER_CTLB_MATCH4_EN (0x10000000)
#define NETARM_SER_CTLB_RBGT_EN (0x08000000)
#define NETARM_SER_CTLB_RCGT_EN (0x04000000)
#define NETARM_SER_CTLB_UART_MODE (0x00000000)
#define NETARM_SER_CTLB_HDLC_MODE (0x00100000)
#define NETARM_SER_CTLB_SPI_MAS_MODE (0x00200000)
#define NETARM_SER_CTLB_SPI_SLV_MODE (0x00300000)
#define NETARM_SER_CTLB_REV_BIT_ORDER (0x00080000)
#define NETARM_SER_CTLB_MAM1 (0x00040000)
#define NETARM_SER_CTLB_MAM2 (0x00020000)
/* Status Register A */
#define NETARM_SER_STATA_MATCH1 (0x80000000)
#define NETARM_SER_STATA_MATCH2 (0x40000000)
#define NETARM_SER_STATA_MATCH3 (0x20000000)
#define NETARM_SER_STATA_MATCH4 (0x10000000)
#define NETARM_SER_STATA_BGAP (0x80000000)
#define NETARM_SER_STATA_CGAP (0x40000000)
#define NETARM_SER_STATA_RX_1B (0x00100000)
#define NETARM_SER_STATA_RX_2B (0x00200000)
#define NETARM_SER_STATA_RX_3B (0x00300000)
#define NETARM_SER_STATA_RX_4B (0x00000000)
/* downshifted values */
#define NETARM_SER_STATA_RXFDB_1BYTES (0x001)
#define NETARM_SER_STATA_RXFDB_2BYTES (0x002)
#define NETARM_SER_STATA_RXFDB_3BYTES (0x003)
#define NETARM_SER_STATA_RXFDB_4BYTES (0x000)
#define NETARM_SER_STATA_RXFDB_MASK (0x00300000)
#define NETARM_SER_STATA_RXFDB(x) (((x) & NETARM_SER_STATA_RXFDB_MASK) \
>> 20)
#define NETARM_SER_STATA_DCD (0x00080000)
#define NETARM_SER_STATA_RI (0x00040000)
#define NETARM_SER_STATA_DSR (0x00020000)
#define NETARM_SER_STATA_CTS (0x00010000)
#define NETARM_SER_STATA_RX_BRK (0x00008000)
#define NETARM_SER_STATA_RX_FRMERR (0x00004000)
#define NETARM_SER_STATA_RX_PARERR (0x00002000)
#define NETARM_SER_STATA_RX_OVERRUN (0x00001000)
#define NETARM_SER_STATA_RX_RDY (0x00000800)
#define NETARM_SER_STATA_RX_HALF (0x00000400)
#define NETARM_SER_STATA_RX_CLOSED (0x00000200)
#define NETARM_SER_STATA_RX_FULL (0x00000100)
#define NETARM_SER_STATA_RX_DCD (0x00000080)
#define NETARM_SER_STATA_RX_RI (0x00000040)
#define NETARM_SER_STATA_RX_DSR (0x00000020)
#define NETARM_SER_STATA_TX_CTS (0x00000010)
#define NETARM_SER_STATA_TX_RDY (0x00000008)
#define NETARM_SER_STATA_TX_HALF (0x00000004)
#define NETARM_SER_STATA_TX_FULL (0x00000002)
#define NETARM_SER_STATA_TX_DMAEN (0x00000001)
/* you have to clear all receive signals to get the fifo to move forward */
#define NETARM_SER_STATA_CLR_ALL (NETARM_SER_STATA_RX_BRK | \
NETARM_SER_STATA_RX_FRMERR | \
NETARM_SER_STATA_RX_PARERR | \
NETARM_SER_STATA_RX_OVERRUN | \
NETARM_SER_STATA_RX_HALF | \
NETARM_SER_STATA_RX_CLOSED | \
NETARM_SER_STATA_RX_FULL | \
NETARM_SER_STATA_RX_DCD | \
NETARM_SER_STATA_RX_RI | \
NETARM_SER_STATA_RX_DSR | \
NETARM_SER_STATA_TX_CTS )
/* Bit Rate Registers */
#define NETARM_SER_BR_EN (0x80000000)
#define NETARM_SER_BR_TMODE (0x40000000)
#define NETARM_SER_BR_RX_CLK_INT (0x00000000)
#define NETARM_SER_BR_RX_CLK_EXT (0x20000000)
#define NETARM_SER_BR_TX_CLK_INT (0x00000000)
#define NETARM_SER_BR_TX_CLK_EXT (0x10000000)
#define NETARM_SER_BR_RX_CLK_DRV (0x08000000)
#define NETARM_SER_BR_TX_CLK_DRV (0x04000000)
#define NETARM_SER_BR_CLK_EXT_5 (0x00000000)
#define NETARM_SER_BR_CLK_SYSTEM (0x01000000)
#define NETARM_SER_BR_CLK_OUT1A (0x02000000)
#define NETARM_SER_BR_CLK_OUT2A (0x03000000)
#define NETARM_SER_BR_TX_CLK_INV (0x00800000)
#define NETARM_SER_BR_RX_CLK_INV (0x00400000)
/* complete settings assuming system clock input is 18MHz */
#define NETARM_SER_BR_MASK (0x000007FF)
/* bit rate determined from equation Fbr = Fxtal / [ 10 * ( N + 1 ) ] */
/* from section 7.5.4 of HW Ref Guide */
/* #ifdef CONFIG_NETARM_PLL_BYPASS */
#define NETARM_SER_BR_X16(x) ( NETARM_SER_BR_EN | \
NETARM_SER_BR_RX_CLK_INT | \
NETARM_SER_BR_TX_CLK_INT | \
NETARM_SER_BR_CLK_EXT_5 | \
( ( ( ( NETARM_XTAL_FREQ / \
( x * 10 ) ) - 1 ) / 16 ) & \
NETARM_SER_BR_MASK ) )
/*
#else
#define NETARM_SER_BR_X16(x) ( NETARM_SER_BR_EN | \
NETARM_SER_BR_RX_CLK_INT | \
NETARM_SER_BR_TX_CLK_INT | \
NETARM_SER_BR_CLK_SYSTEM | \
( ( ( ( NETARM_PLLED_SYSCLK_FREQ / \
( x * 2 ) ) - 1 ) / 16 ) & \
NETARM_SER_BR_MASK ) )
#endif
*/
/* Receive Buffer Gap Timer */
#define NETARM_SER_RX_GAP_TIMER_EN (0x80000000)
#define NETARM_SER_RX_GAP_MASK (0x00003FFF)
/* rx gap is a function of bit rate x */
/* #ifdef CONFIG_NETARM_PLL_BYPASS */
#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \
( ( ( ( 10 * NETARM_XTAL_FREQ ) / \
( x * 5 * 512 ) ) - 1 ) & \
NETARM_SER_RX_GAP_MASK ) )
/*
#else
#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \
( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) / \
( x * 512 ) ) - 1 ) & \
NETARM_SER_RX_GAP_MASK ) )
#endif
*/
#if 0
#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \
( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) / \
( x * 5 * 512 ) ) - 1 ) & \
NETARM_SER_RX_GAP_MASK ) )
#define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \
( ( ( ( 10 * NETARM_XTAL_FREQ ) / \
( x * 512 ) ) - 1 ) & \
NETARM_SER_RX_GAP_MASK ) )
#endif
#define MIN_BAUD_RATE 600
#define MAX_BAUD_RATE 115200
/* the default BAUD rate for the BOOTLOADER, there is a separate */
/* setting in the serial driver <arch/armnommu/drivers/char/serial-netarm.h> */
#define DEFAULT_BAUD_RATE 9600
#define NETARM_SER_FIFO_SIZE 32
#define MIN_GAP 0
#endif

225
arch/arm/include/asm/arch-lpc2292/lpc2292_registers.h
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@ -1,225 +0,0 @@
#ifndef __LPC2292_REGISTERS_H
#define __LPC2292_REGISTERS_H
#include <config.h>
/* Macros for reading/writing registers */
#define PUT8(reg, value) (*(volatile unsigned char*)(reg) = (value))
#define PUT16(reg, value) (*(volatile unsigned short*)(reg) = (value))
#define PUT32(reg, value) (*(volatile unsigned int*)(reg) = (value))
#define GET8(reg) (*(volatile unsigned char*)(reg))
#define GET16(reg) (*(volatile unsigned short*)(reg))
#define GET32(reg) (*(volatile unsigned int*)(reg))
/* External Memory Controller */
#define BCFG0 0xFFE00000 /* 32-bits */
#define BCFG1 0xFFE00004 /* 32-bits */
#define BCFG2 0xFFE00008 /* 32-bits */
#define BCFG3 0xFFE0000c /* 32-bits */
/* System Control Block */
#define EXTINT 0xE01FC140
#define EXTWAKE 0xE01FC144
#define EXTMODE 0xE01FC148
#define EXTPOLAR 0xE01FC14C
#define MEMMAP 0xE01FC040
#define PLLCON 0xE01FC080
#define PLLCFG 0xE01FC084
#define PLLSTAT 0xE01FC088
#define PLLFEED 0xE01FC08C
#define PCON 0xE01FC0C0
#define PCONP 0xE01FC0C4
#define VPBDIV 0xE01FC100
/* Memory Acceleration Module */
#define MAMCR 0xE01FC000
#define MAMTIM 0xE01FC004
/* Vectored Interrupt Controller */
#define VICIRQStatus 0xFFFFF000
#define VICFIQStatus 0xFFFFF004
#define VICRawIntr 0xFFFFF008
#define VICIntSelect 0xFFFFF00C
#define VICIntEnable 0xFFFFF010
#define VICIntEnClr 0xFFFFF014
#define VICSoftInt 0xFFFFF018
#define VICSoftIntClear 0xFFFFF01C
#define VICProtection 0xFFFFF020
#define VICVectAddr 0xFFFFF030
#define VICDefVectAddr 0xFFFFF034
#define VICVectAddr0 0xFFFFF100
#define VICVectAddr1 0xFFFFF104
#define VICVectAddr2 0xFFFFF108
#define VICVectAddr3 0xFFFFF10C
#define VICVectAddr4 0xFFFFF110
#define VICVectAddr5 0xFFFFF114
#define VICVectAddr6 0xFFFFF118
#define VICVectAddr7 0xFFFFF11C
#define VICVectAddr8 0xFFFFF120
#define VICVectAddr9 0xFFFFF124
#define VICVectAddr10 0xFFFFF128
#define VICVectAddr11 0xFFFFF12C
#define VICVectAddr12 0xFFFFF130
#define VICVectAddr13 0xFFFFF134
#define VICVectAddr14 0xFFFFF138
#define VICVectAddr15 0xFFFFF13C
#define VICVectCntl0 0xFFFFF200
#define VICVectCntl1 0xFFFFF204
#define VICVectCntl2 0xFFFFF208
#define VICVectCntl3 0xFFFFF20C
#define VICVectCntl4 0xFFFFF210
#define VICVectCntl5 0xFFFFF214
#define VICVectCntl6 0xFFFFF218
#define VICVectCntl7 0xFFFFF21C
#define VICVectCntl8 0xFFFFF220
#define VICVectCntl9 0xFFFFF224
#define VICVectCntl10 0xFFFFF228
#define VICVectCntl11 0xFFFFF22C
#define VICVectCntl12 0xFFFFF230
#define VICVectCntl13 0xFFFFF234
#define VICVectCntl14 0xFFFFF238
#define VICVectCntl15 0xFFFFF23C
/* Pin connect block */
#define PINSEL0 0xE002C000 /* 32 bits */
#define PINSEL1 0xE002C004 /* 32 bits */
#define PINSEL2 0xE002C014 /* 32 bits */
/* GPIO */
#define IO0PIN 0xE0028000
#define IO0SET 0xE0028004
#define IO0DIR 0xE0028008
#define IO0CLR 0xE002800C
#define IO1PIN 0xE0028010
#define IO1SET 0xE0028014
#define IO1DIR 0xE0028018
#define IO1CLR 0xE002801C
#define IO2PIN 0xE0028020
#define IO2SET 0xE0028024
#define IO2DIR 0xE0028028
#define IO2CLR 0xE002802C
#define IO3PIN 0xE0028030
#define IO3SET 0xE0028034
#define IO3DIR 0xE0028038
#define IO3CLR 0xE002803C
/* Uarts */
#define U0RBR 0xE000C000
#define U0THR 0xE000C000
#define U0IER 0xE000C004
#define U0IIR 0xE000C008
#define U0FCR 0xE000C008
#define U0LCR 0xE000C00C
#define U0LSR 0xE000C014
#define U0SCR 0xE000C01C
#define U0DLL 0xE000C000
#define U0DLM 0xE000C004
#define U1RBR 0xE0010000
#define U1THR 0xE0010000
#define U1IER 0xE0010004
#define U1IIR 0xE0010008
#define U1FCR 0xE0010008
#define U1LCR 0xE001000C
#define U1MCR 0xE0010010
#define U1LSR 0xE0010014
#define U1MSR 0xE0010018
#define U1SCR 0xE001001C
#define U1DLL 0xE0010000
#define U1DLM 0xE0010004
/* I2C */
#define I2CONSET 0xE001C000
#define I2STAT 0xE001C004
#define I2DAT 0xE001C008
#define I2ADR 0xE001C00C
#define I2SCLH 0xE001C010
#define I2SCLL 0xE001C014
#define I2CONCLR 0xE001C018
/* SPI */
#define S0SPCR 0xE0020000
#define S0SPSR 0xE0020004
#define S0SPDR 0xE0020008
#define S0SPCCR 0xE002000C
#define S0SPINT 0xE002001C
#define S1SPCR 0xE0030000
#define S1SPSR 0xE0030004
#define S1SPDR 0xE0030008
#define S1SPCCR 0xE003000C
#define S1SPINT 0xE003001C
/* CAN controller */
/* skip for now */
/* Timers */
#define T0IR 0xE0004000
#define T0TCR 0xE0004004
#define T0TC 0xE0004008
#define T0PR 0xE000400C
#define T0PC 0xE0004010
#define T0MCR 0xE0004014
#define T0MR0 0xE0004018
#define T0MR1 0xE000401C
#define T0MR2 0xE0004020
#define T0MR3 0xE0004024
#define T0CCR 0xE0004028
#define T0CR0 0xE000402C
#define T0CR1 0xE0004030
#define T0CR2 0xE0004034
#define T0CR3 0xE0004038
#define T0EMR 0xE000403C
#define T1IR 0xE0008000
#define T1TCR 0xE0008004
#define T1TC 0xE0008008
#define T1PR 0xE000800C
#define T1PC 0xE0008010
#define T1MCR 0xE0008014
#define T1MR0 0xE0008018
#define T1MR1 0xE000801C
#define T1MR2 0xE0008020
#define T1MR3 0xE0008024
#define T1CCR 0xE0008028
#define T1CR0 0xE000802C
#define T1CR1 0xE0008030
#define T1CR2 0xE0008034
#define T1CR3 0xE0008038
#define T1EMR 0xE000803C
/* PWM */
/* skip for now */
/* A/D converter */
/* skip for now */
/* Real Time Clock */
/* skip for now */
/* Watchdog */
#define WDMOD 0xE0000000
#define WDTC 0xE0000004
#define WDFEED 0xE0000008
#define WDTV 0xE000000C
/* EmbeddedICE LOGIC */
/* skip for now */
#endif

82
arch/arm/include/asm/arch-lpc2292/spi.h
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@ -1,82 +0,0 @@
/*
This file defines the interface to the lpc22xx SPI module.
Copyright (C) 2006 Embedded Artists AB (www.embeddedartists.com)
This file may be included in software not adhering to the GPL.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef SPI_H
#define SPI_H
#include <config.h>
#include <common.h>
#include <asm/errno.h>
#include <asm/arch/hardware.h>
#define SPIF 0x80
#define spi_lock() disable_interrupts();
#define spi_unlock() enable_interrupts();
extern unsigned long spi_flags;
extern unsigned char spi_idle;
int spi_init(void);
static inline unsigned char spi_read(void)
{
unsigned char b;
PUT8(S0SPDR, spi_idle);
while (!(GET8(S0SPSR) & SPIF));
b = GET8(S0SPDR);
return b;
}
static inline void spi_write(unsigned char b)
{
PUT8(S0SPDR, b);
while (!(GET8(S0SPSR) & SPIF));
GET8(S0SPDR); /* this will clear the SPIF bit */
}
static inline void spi_set_clock(unsigned char clk_value)
{
PUT8(S0SPCCR, clk_value);
}
static inline void spi_set_cfg(unsigned char phase,
unsigned char polarity,
unsigned char lsbf)
{
unsigned char v = 0x20; /* master bit set */
if (phase)
v |= 0x08; /* set phase bit */
if (polarity) {
v |= 0x10; /* set polarity bit */
spi_idle = 0xFF;
} else {
spi_idle = 0x00;
}
if (lsbf)
v |= 0x40; /* set lsbf bit */
PUT8(S0SPCR, v);
}
#endif /* SPI_H */

1
arch/arm/include/asm/arch-omap3/dss.h
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@ -190,6 +190,7 @@ struct panel_config {
#define PANEL_TIMING_H(bp, fp, sw) (DSS_HBP(bp) | DSS_HFP(fp) | DSS_HSW(sw))
#define PANEL_TIMING_V(bp, fp, sw) (DSS_VBP(bp) | DSS_VFP(fp) | DSS_VSW(sw))
#define PANEL_LCD_SIZE(xres, yres) ((yres - 1) << 16 | (xres - 1))
/* Generic DSS Functions */
void omap3_dss_venc_config(const struct venc_regs *venc_cfg,

272
arch/arm/include/asm/arch-s3c4510b/hardware.h
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@ -1,272 +0,0 @@
#ifndef __HW_S3C4510_H
#define __HW_S3C4510_H
/*
* Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
* Curt Brune <curt@cucy.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Description: Samsung S3C4510B register layout
*/
/*------------------------------------------------------------------------
* ASIC Address Definition
*----------------------------------------------------------------------*/
/* L1 8KB on chip SRAM base address */
#define SRAM_BASE (0x03fe0000)
/* Special Register Start Address After System Reset */
#define REG_BASE (0x03ff0000)
#define SPSTR (REG_BASE)
/* *********************** */
/* System Manager Register */
/* *********************** */
#define REG_SYSCFG (REG_BASE+0x0000)
#define REG_CLKCON (REG_BASE+0x3000)
#define REG_EXTACON0 (REG_BASE+0x3008)
#define REG_EXTACON1 (REG_BASE+0x300c)
#define REG_EXTDBWTH (REG_BASE+0x3010)
#define REG_ROMCON0 (REG_BASE+0x3014)
#define REG_ROMCON1 (REG_BASE+0x3018)
#define REG_ROMCON2 (REG_BASE+0x301c)
#define REG_ROMCON3 (REG_BASE+0x3020)
#define REG_ROMCON4 (REG_BASE+0x3024)
#define REG_ROMCON5 (REG_BASE+0x3028)
#define REG_DRAMCON0 (REG_BASE+0x302c)
#define REG_DRAMCON1 (REG_BASE+0x3030)
#define REG_DRAMCON2 (REG_BASE+0x3034)
#define REG_DRAMCON3 (REG_BASE+0x3038)
#define REG_REFEXTCON (REG_BASE+0x303c)
/* *********************** */
/* Ethernet BDMA Register */
/* *********************** */
#define REG_BDMATXCON (REG_BASE+0x9000)
#define REG_BDMARXCON (REG_BASE+0x9004)
#define REG_BDMATXPTR (REG_BASE+0x9008)
#define REG_BDMARXPTR (REG_BASE+0x900c)
#define REG_BDMARXLSZ (REG_BASE+0x9010)
#define REG_BDMASTAT (REG_BASE+0x9014)
/* Content Address Memory */
#define REG_CAM_BASE (REG_BASE+0x9100)
#define REG_BDMATXBUF (REG_BASE+0x9200)
#define REG_BDMARXBUF (REG_BASE+0x9800)
/* *********************** */
/* Ethernet MAC Register */
/* *********************** */
#define REG_MACCON (REG_BASE+0xa000)
#define REG_CAMCON (REG_BASE+0xa004)
#define REG_MACTXCON (REG_BASE+0xa008)
#define REG_MACTXSTAT (REG_BASE+0xa00c)
#define REG_MACRXCON (REG_BASE+0xa010)
#define REG_MACRXSTAT (REG_BASE+0xa014)
#define REG_STADATA (REG_BASE+0xa018)
#define REG_STACON (REG_BASE+0xa01c)
#define REG_CAMEN (REG_BASE+0xa028)
#define REG_EMISSCNT (REG_BASE+0xa03c)
#define REG_EPZCNT (REG_BASE+0xa040)
#define REG_ERMPZCNT (REG_BASE+0xa044)
#define REG_ETXSTAT (REG_BASE+0x9040)
#define REG_MACRXDESTR (REG_BASE+0xa064)
#define REG_MACRXSTATEM (REG_BASE+0xa090)
#define REG_MACRXFIFO (REG_BASE+0xa200)
/********************/
/* I2C Bus Register */
/********************/
#define REG_I2C_CON (REG_BASE+0xf000)
#define REG_I2C_BUF (REG_BASE+0xf004)
#define REG_I2C_PS (REG_BASE+0xf008)
#define REG_I2C_COUNT (REG_BASE+0xf00c)
/********************/
/* GDMA 0 */
/********************/
#define REG_GDMACON0 (REG_BASE+0xb000)
#define REG_GDMA0_RUN_ENABLE (REG_BASE+0xb020)
#define REG_GDMASRC0 (REG_BASE+0xb004)
#define REG_GDMADST0 (REG_BASE+0xb008)
#define REG_GDMACNT0 (REG_BASE+0xb00c)
/********************/
/* GDMA 1 */
/********************/
#define REG_GDMACON1 (REG_BASE+0xc000)
#define REG_GDMA1_RUN_ENABLE (REG_BASE+0xc020)
#define REG_GDMASRC1 (REG_BASE+0xc004)
#define REG_GDMADST1 (REG_BASE+0xc008)
#define REG_GDMACNT1 (REG_BASE+0xc00c)
/********************/
/* UART 0 */
/********************/
#define UART0_BASE (REG_BASE+0xd000)
#define REG_UART0_LCON (REG_BASE+0xd000)
#define REG_UART0_CTRL (REG_BASE+0xd004)
#define REG_UART0_STAT (REG_BASE+0xd008)
#define REG_UART0_TXB (REG_BASE+0xd00c)
#define REG_UART0_RXB (REG_BASE+0xd010)
#define REG_UART0_BAUD_DIV (REG_BASE+0xd014)
#define REG_UART0_BAUD_CNT (REG_BASE+0xd018)
#define REG_UART0_BAUD_CLK (REG_BASE+0xd01C)
/********************/
/* UART 1 */
/********************/
#define UART1_BASE (REG_BASE+0xe000)
#define REG_UART1_LCON (REG_BASE+0xe000)
#define REG_UART1_CTRL (REG_BASE+0xe004)
#define REG_UART1_STAT (REG_BASE+0xe008)
#define REG_UART1_TXB (REG_BASE+0xe00c)
#define REG_UART1_RXB (REG_BASE+0xe010)
#define REG_UART1_BAUD_DIV (REG_BASE+0xe014)
#define REG_UART1_BAUD_CNT (REG_BASE+0xe018)
#define REG_UART1_BAUD_CLK (REG_BASE+0xe01C)
/********************/
/* Timer Register */
/********************/
#define REG_TMOD (REG_BASE+0x6000)
#define REG_TDATA0 (REG_BASE+0x6004)
#define REG_TDATA1 (REG_BASE+0x6008)
#define REG_TCNT0 (REG_BASE+0x600c)
#define REG_TCNT1 (REG_BASE+0x6010)
/**********************/
/* I/O Port Interface */
/**********************/
#define REG_IOPMODE (REG_BASE+0x5000)
#define REG_IOPCON (REG_BASE+0x5004)
#define REG_IOPDATA (REG_BASE+0x5008)
/*********************************/
/* Interrupt Controller Register */
/*********************************/
#define REG_INTMODE (REG_BASE+0x4000)
#define REG_INTPEND (REG_BASE+0x4004)
#define REG_INTMASK (REG_BASE+0x4008)
#define REG_INTPRI0 (REG_BASE+0x400c)
#define REG_INTPRI1 (REG_BASE+0x4010)
#define REG_INTPRI2 (REG_BASE+0x4014)
#define REG_INTPRI3 (REG_BASE+0x4018)
#define REG_INTPRI4 (REG_BASE+0x401c)
#define REG_INTPRI5 (REG_BASE+0x4020)
#define REG_INTOFFSET (REG_BASE+0x4024)
#define REG_INTPNDPRI (REG_BASE+0x4028)
#define REG_INTPNDTST (REG_BASE+0x402C)
/*********************************/
/* CACHE CONTROL MASKS */
/*********************************/
#define CACHE_STALL (0x00000001)
#define CACHE_ENABLE (0x00000002)
#define CACHE_WRITE_BUFF (0x00000004)
#define CACHE_MODE (0x00000030)
#define CACHE_MODE_00 (0x00000000)
#define CACHE_MODE_01 (0x00000010)
#define CACHE_MODE_10 (0x00000020)
/*********************************/
/* CACHE RAM BASE ADDRESSES */
/*********************************/
#define CACHE_SET0_RAM (0x10000000)
#define CACHE_SET1_RAM (0x10800000)
#define CACHE_TAG_RAM (0x11000000)
/*********************************/
/* CACHE_DISABLE MASK */
/*********************************/
#define CACHE_DISABLE_MASK (0x04000000)
#define GET_REG(reg) (*((volatile u32 *)(reg)))
#define PUT_REG(reg, val) (*((volatile u32 *)(reg)) = ((u32)(val)))
#define SET_REG(reg, mask) (PUT_REG((reg), GET_REG((reg)) | mask))
#define CLR_REG(reg, mask) (PUT_REG((reg), GET_REG((reg)) & ~mask))
#define PUT_U16(reg, val) (*((volatile u16 *)(reg)) = ((u16)(val)))
#define PUT__U8(reg, val) (*((volatile u8 *)(reg)) = (( u8)((val)&0xFF)))
#define GET__U8(reg) (*((volatile u8 *)(reg)))
#define PUT_LED(val) (PUT_REG(REG_IOPDATA, (~val)&0xFF))
#define GET_LED() ((~GET_REG( REG_IOPDATA)) & 0xFF)
#define SET_LED(val) { u32 led = GET_LED(); led |= 1 << (val); PUT_LED( led); }
#define CLR_LED(val) { u32 led = GET_LED(); led &= ~(1 << (val)); PUT_LED( led); }
/***********************************/
/* CLOCK CONSTANTS -- 50 MHz Clock */
/***********************************/
#define CLK_FREQ_MHZ (50)
#define t_data_us(t) ((t)*CLK_FREQ_MHZ-1) /* t is time tick,unit[us] */
#define t_data_ms(t) (t_data_us((t)*1000)) /* t is time tick,unit[ms] */
/*********************************************************/
/* TIMER MODE REGISTER */
/*********************************************************/
#define TM0_RUN 0x01 /* Timer 0 enable */
#define TM0_TOGGLE 0x02 /* 0, interval mode */
#define TM0_OUT_1 0x04 /* Timer 0 Initial TOUT0 value */
#define TM1_RUN 0x08 /* Timer 1 enable */
#define TM1_TOGGLE 0x10 /* 0, interval mode */
#define TM1_OUT_1 0x20 /* Timer 0 Initial TOUT0 value */
/*********************************/
/* INTERRUPT SOURCES */
/*********************************/
#define INT_EXTINT0 0
#define INT_EXTINT1 1
#define INT_EXTINT2 2
#define INT_EXTINT3 3
#define INT_UARTTX0 4
#define INT_UARTRX0 5
#define INT_UARTTX1 6
#define INT_UARTRX1 7
#define INT_GDMA0 8
#define INT_GDMA1 9
#define INT_TIMER0 10
#define INT_TIMER1 11
#define INT_HDLCTXA 12
#define INT_HDLCRXA 13
#define INT_HDLCTXB 14
#define INT_HDLCRXB 15
#define INT_BDMATX 16
#define INT_BDMARX 17
#define INT_MACTX 18
#define INT_MACRX 19
#define INT_IIC 20
#define INT_GLOBAL 21
#define N_IRQS (21)
#ifndef __ASSEMBLER__
struct _irq_handler {
void *m_data;
void (*m_func)( void *data);
};
#endif
#endif /* __S3C4510_h */

28
arch/arm/include/asm/arch-tegra20/spl.h 100644
View File

@ -0,0 +1,28 @@
/*
* (C) Copyright 2012
* NVIDIA Corporation <www.nvidia.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _ASM_ARCH_SPL_H_
#define _ASM_ARCH_SPL_H_
#define BOOT_DEVICE_RAM 1
#endif

2
arch/arm/include/asm/global_data.h
View File

@ -34,7 +34,7 @@
typedef struct global_data {
bd_t *bd;
unsigned long flags;
unsigned long baudrate;
unsigned int baudrate;
unsigned long have_console; /* serial_init() was called */
#ifdef CONFIG_PRE_CONSOLE_BUFFER
unsigned long precon_buf_idx; /* Pre-Console buffer index */

5
arch/arm/include/asm/setup.h
View File

@ -267,3 +267,8 @@ struct meminfo {
extern struct meminfo meminfo;
#endif
/*
* Board specified tags
*/
void setup_board_tags(struct tag **in_params);

2
arch/arm/include/asm/u-boot.h
View File

@ -37,7 +37,7 @@
#define _U_BOOT_H_ 1
typedef struct bd_info {
int bi_baudrate; /* serial console baudrate */
unsigned int bi_baudrate; /* serial console baudrate */
ulong bi_arch_number; /* unique id for this board */
ulong bi_boot_params; /* where this board expects params */
unsigned long bi_arm_freq; /* arm frequency */

39
arch/arm/lib/board.c
View File

@ -57,13 +57,6 @@
#include <miiphy.h>
#endif
#ifdef CONFIG_DRIVER_SMC91111
#include "../drivers/net/smc91111.h"
#endif
#ifdef CONFIG_DRIVER_LAN91C96
#include "../drivers/net/lan91c96.h"
#endif
DECLARE_GLOBAL_DATA_PTR;
ulong monitor_flash_len;
@ -274,6 +267,8 @@ void board_init_f(ulong bootflag)
#ifdef CONFIG_PRAM
ulong reg;
#endif
void *new_fdt = NULL;
size_t fdt_size = 0;
bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
@ -409,6 +404,22 @@ void board_init_f(ulong bootflag)
debug("Reserving %zu Bytes for Global Data at: %08lx\n",
sizeof (gd_t), addr_sp);
#if defined(CONFIG_OF_SEPARATE) && defined(CONFIG_OF_CONTROL)
/*
* If the device tree is sitting immediate above our image then we
* must relocate it. If it is embedded in the data section, then it
* will be relocated with other data.
*/
if (gd->fdt_blob) {
fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
addr_sp -= fdt_size;
new_fdt = (void *)addr_sp;
debug("Reserving %zu Bytes for FDT at: %08lx\n",
fdt_size, addr_sp);
}
#endif
/* setup stackpointer for exeptions */
gd->irq_sp = addr_sp;
#ifdef CONFIG_USE_IRQ
@ -442,6 +453,10 @@ void board_init_f(ulong bootflag)
gd->start_addr_sp = addr_sp;
gd->reloc_off = addr - _TEXT_BASE;
debug("relocation Offset is: %08lx\n", gd->reloc_off);
if (new_fdt) {
memcpy(new_fdt, gd->fdt_blob, fdt_size);
gd->fdt_blob = new_fdt;
}
memcpy(id, (void *)gd, sizeof(gd_t));
relocate_code(addr_sp, id, addr);
@ -591,16 +606,6 @@ void board_init_r(gd_t *id, ulong dest_addr)
/* enable exceptions */
enable_interrupts();
/* Perform network card initialisation if necessary */
#if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96)
/* XXX: this needs to be moved to board init */
if (getenv("ethaddr")) {
uchar enetaddr[6];
eth_getenv_enetaddr("ethaddr", enetaddr);
smc_set_mac_addr(enetaddr);
}
#endif /* CONFIG_DRIVER_SMC91111 || CONFIG_DRIVER_LAN91C96 */
/* Initialize from environment */
load_addr = getenv_ulong("loadaddr", 16, load_addr);

4
arch/arm/lib/bootm.c
View File

@ -34,6 +34,7 @@
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/bootm.h>
#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
@ -269,6 +270,8 @@ static int create_fdt(bootm_headers_t *images)
}
#endif
__weak void setup_board_tags(struct tag **in_params) {}
/* Subcommand: PREP */
static void boot_prep_linux(bootm_headers_t *images)
{
@ -310,6 +313,7 @@ static void boot_prep_linux(bootm_headers_t *images)
setup_initrd_tag(gd->bd, images->rd_start,
images->rd_end);
#endif
setup_board_tags(&params);
setup_end_tag(gd->bd);
#else /* all tags */
printf("FDT and ATAGS support not compiled in - hanging\n");

8
arch/avr32/cpu/u-boot.lds
View File

@ -47,11 +47,11 @@ SECTIONS
}
. = ALIGN(4);
__u_boot_cmd_start = .;
.u_boot_cmd : {
KEEP(*(.u_boot_cmd))
. = ALIGN(4);
.u_boot_list : {
#include <u-boot.lst>
}
__u_boot_cmd_end = .;
. = ALIGN(4);
_got = .;

2
arch/avr32/include/asm/global_data.h
View File

@ -33,7 +33,7 @@
typedef struct global_data {
bd_t *bd;
unsigned long flags;
unsigned long baudrate;
unsigned int baudrate;
unsigned long stack_end; /* highest stack address */
unsigned long have_console; /* serial_init() was called */
#ifdef CONFIG_PRE_CONSOLE_BUFFER

2
arch/avr32/include/asm/u-boot.h
View File

@ -23,7 +23,7 @@
#define __ASM_U_BOOT_H__ 1
typedef struct bd_info {
unsigned long bi_baudrate;
unsigned int bi_baudrate;
unsigned char bi_phy_id[4];
unsigned long bi_board_number;
void *bi_boot_params;

4
arch/avr32/lib/board.c
View File

@ -272,8 +272,8 @@ void board_init_r(gd_t *new_gd, ulong dest_addr)
/*
* We have to relocate the command table manually
*/
fixup_cmdtable(&__u_boot_cmd_start,
(ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
ll_entry_count(cmd_tbl_t, cmd));
#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
/* there are some other pointer constants we must deal with */

8
arch/blackfin/cpu/u-boot.lds
View File

@ -112,11 +112,9 @@ SECTIONS
CONSTRUCTORS
} >ram_data
.u_boot_cmd :
{
___u_boot_cmd_start = .;
*(.u_boot_cmd)
___u_boot_cmd_end = .;
.u_boot_list : {
#include <u-boot.lst>
} >ram_data
.text_l1 :

2
arch/blackfin/include/asm/global_data.h
View File

@ -41,7 +41,7 @@ typedef struct global_data {
bd_t *bd;
unsigned long flags;
unsigned long board_type;
unsigned long baudrate;
unsigned int baudrate;
unsigned long have_console; /* serial_init() was called */
#ifdef CONFIG_PRE_CONSOLE_BUFFER
unsigned long precon_buf_idx; /* Pre-Console buffer index */

2
arch/blackfin/include/asm/u-boot.h
View File

@ -29,7 +29,7 @@
#define _U_BOOT_H_ 1
typedef struct bd_info {
int bi_baudrate; /* serial console baudrate */
unsigned int bi_baudrate; /* serial console baudrate */
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_memstart; /* start of DRAM memory */
phys_size_t bi_memsize; /* size of DRAM memory in bytes */

2
arch/blackfin/lib/board.c
View File

@ -78,7 +78,7 @@ static void display_global_data(void)
printf(" gd: %p\n", gd);
printf(" |-flags: %lx\n", gd->flags);
printf(" |-board_type: %lx\n", gd->board_type);
printf(" |-baudrate: %lu\n", gd->baudrate);
printf(" |-baudrate: %u\n", gd->baudrate);
printf(" |-have_console: %lx\n", gd->have_console);
printf(" |-ram_size: %lx\n", gd->ram_size);
printf(" |-env_addr: %lx\n", gd->env_addr);

8
arch/m68k/cpu/mcf5227x/cpu_init.c
View File

@ -31,6 +31,7 @@
#include <asm/immap.h>
#include <asm/io.h>
#include <asm/rtc.h>
#include <linux/compiler.h>
/*
* Breath some life into the CPU...
@ -41,12 +42,13 @@
*/
void cpu_init_f(void)
{
scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
pll_t *pll = (pll_t *)MMAP_PLL;
fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS;
#if !defined(CONFIG_CF_SBF)
scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
pll_t *pll = (pll_t *)MMAP_PLL;
/* Workaround, must place before fbcs */
out_be32(&pll->psr, 0x12);

2
arch/m68k/cpu/mcf5227x/start.S
View File

@ -485,7 +485,7 @@ clear_bss:
/* exception code */
.globl _fault
_fault:
jmp _fault
bra _fault
.globl _exc_handler
_exc_handler:

2
arch/m68k/cpu/mcf523x/start.S
View File

@ -247,7 +247,7 @@ clear_bss:
/* exception code */
.globl _fault
_fault:
jmp _fault
bra _fault
.globl _exc_handler
_exc_handler:

2
arch/m68k/cpu/mcf52x2/start.S
View File

@ -307,7 +307,7 @@ clear_bss:
/* exception code */
.globl _fault
_fault:
jmp _fault
bra _fault
.globl _exc_handler
_exc_handler:

2
arch/m68k/cpu/mcf532x/start.S
View File

@ -261,7 +261,7 @@ clear_bss:
/* exception code */
.globl _fault
_fault:
jmp _fault
bra _fault
.globl _exc_handler
_exc_handler:

10
arch/m68k/cpu/mcf5445x/config.mk
View File

@ -4,6 +4,8 @@
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# Copyright 2011-2012 Freescale Semiconductor, Inc.
#
# See file CREDITS for list of people who contributed to this
# project.
#
@ -24,7 +26,15 @@
#
PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
is5441x:=$(shell grep CONFIG_MCF5441x $(TOPDIR)/include/$(cfg))
ifneq (,$(findstring CONFIG_MCF5441x,$(is5441x)))
PLATFORM_CPPFLAGS += -mcpu=54418 -fPIC
else
PLATFORM_CPPFLAGS += -mcpu=54455 -fPIC
endif
ifneq (,$(findstring -linux-,$(shell $(CC) --version)))
ifneq (,$(findstring GOT,$(shell $(LD) --help)))

17
arch/m68k/cpu/mcf5445x/cpu.c
View File

@ -39,6 +39,8 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
rcm_t *rcm = (rcm_t *) (MMAP_RCM);
udelay(1000);
out_8(&rcm->rcr, RCM_RCR_FRCRSTOUT);
udelay(10000);
setbits_8(&rcm->rcr, RCM_RCR_SOFTRST);
/* we don't return! */
@ -74,6 +76,21 @@ int checkcpu(void)
case 0x4f:
id = 54450;
break;
case 0x9F:
id = 54410;
break;
case 0xA0:
id = 54415;
break;
case 0xA1:
id = 54416;
break;
case 0xA2:
id = 54417;
break;
case 0xA3:
id = 54418;
break;
}
if (id) {

316
arch/m68k/cpu/mcf5445x/cpu_init.c
View File

@ -31,6 +31,7 @@
#include <asm/processor.h>
#include <asm/rtc.h>
#include <asm/io.h>
#include <linux/compiler.h>
#if defined(CONFIG_CMD_NET)
#include <config.h>
@ -38,37 +39,11 @@
#include <asm/fec.h>
#endif
/*
* Breath some life into the CPU...
*
* Set up the memory map,
* initialize a bunch of registers,
* initialize the UPM's
*/
void cpu_init_f(void)
void init_fbcs(void)
{
scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS;
out_be32(&scm1->mpr, 0x77777777);
out_be32(&scm1->pacra, 0);
out_be32(&scm1->pacrb, 0);
out_be32(&scm1->pacrc, 0);
out_be32(&scm1->pacrd, 0);
out_be32(&scm1->pacre, 0);
out_be32(&scm1->pacrf, 0);
out_be32(&scm1->pacrg, 0);
/* FlexBus */
out_8(&gpio->par_be,
GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
out_8(&gpio->par_fbctl,
GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
#if !defined(CONFIG_CF_SBF)
#if !defined(CONFIG_SERIAL_BOOT)
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
@ -106,6 +81,145 @@ void cpu_init_f(void)
out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
#endif
}
/*
* Breath some life into the CPU...
*
* Set up the memory map,
* initialize a bunch of registers,
* initialize the UPM's
*/
void cpu_init_f(void)
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
#ifdef CONFIG_MCF5441x
scm_t *scm = (scm_t *) MMAP_SCM;
pm_t *pm = (pm_t *) MMAP_PM;
/* Disable Switch */
*(unsigned long *)(MMAP_L2_SW0 + 0x00000024) = 0;
/* Disable core watchdog */
out_be16(&scm->cwcr, 0);
out_8(&gpio->par_fbctl,
GPIO_PAR_FBCTL_ALE_FB_ALE | GPIO_PAR_FBCTL_OE_FB_OE |
GPIO_PAR_FBCTL_FBCLK | GPIO_PAR_FBCTL_RW |
GPIO_PAR_FBCTL_TA_TA);
out_8(&gpio->par_be,
GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
/* eDMA */
out_8(&pm->pmcr0, 17);
/* INTR0 - INTR2 */
out_8(&pm->pmcr0, 18);
out_8(&pm->pmcr0, 19);
out_8(&pm->pmcr0, 20);
/* I2C */
out_8(&pm->pmcr0, 22);
out_8(&pm->pmcr1, 4);
out_8(&pm->pmcr1, 7);
/* DTMR0 - DTMR3*/
out_8(&pm->pmcr0, 28);
out_8(&pm->pmcr0, 29);
out_8(&pm->pmcr0, 30);
out_8(&pm->pmcr0, 31);
/* PIT0 - PIT3 */
out_8(&pm->pmcr0, 32);
out_8(&pm->pmcr0, 33);
out_8(&pm->pmcr0, 34);
out_8(&pm->pmcr0, 35);
/* Edge Port */
out_8(&pm->pmcr0, 36);
out_8(&pm->pmcr0, 37);
/* USB OTG */
out_8(&pm->pmcr0, 44);
/* USB Host */
out_8(&pm->pmcr0, 45);
/* ESDHC */
out_8(&pm->pmcr0, 51);
/* ENET0 - ENET1 */
out_8(&pm->pmcr0, 53);
out_8(&pm->pmcr0, 54);
/* NAND */
out_8(&pm->pmcr0, 63);
#ifdef CONFIG_SYS_I2C_0
out_8(&gpio->par_cani2c, 0xF0);
/* I2C0 pull up */
out_be16(&gpio->pcr_b, 0x003C);
/* I2C0 max speed */
out_8(&gpio->srcr_cani2c, 0x03);
#endif
#ifdef CONFIG_SYS_I2C_2
/* I2C2 */
out_8(&gpio->par_ssi0h, 0xA0);
/* I2C2, UART7 */
out_8(&gpio->par_ssi0h, 0xA8);
/* UART7 */
out_8(&gpio->par_ssi0l, 0x2);
/* UART8, UART9 */
out_8(&gpio->par_cani2c, 0xAA);
/* UART4, UART0 */
out_8(&gpio->par_uart0, 0xAF);
/* UART5, UART1 */
out_8(&gpio->par_uart1, 0xAF);
/* UART6, UART2 */
out_8(&gpio->par_uart2, 0xAF);
/* I2C2 pull up */
out_be16(&gpio->pcr_h, 0xF000);
#endif
#ifdef CONFIG_SYS_I2C_5
/* I2C5 */
out_8(&gpio->par_uart1, 0x0A);
/* I2C5 pull up */
out_be16(&gpio->pcr_e, 0x0003);
out_be16(&gpio->pcr_f, 0xC000);
#endif
/* Lowest slew rate for UART0,1,2 */
out_8(&gpio->srcr_uart, 0x00);
#endif /* CONFIG_MCF5441x */
#ifdef CONFIG_MCF5445x
scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
out_be32(&scm1->mpr, 0x77777777);
out_be32(&scm1->pacra, 0);
out_be32(&scm1->pacrb, 0);
out_be32(&scm1->pacrc, 0);
out_be32(&scm1->pacrd, 0);
out_be32(&scm1->pacre, 0);
out_be32(&scm1->pacrf, 0);
out_be32(&scm1->pacrg, 0);
/* FlexBus */
out_8(&gpio->par_be,
GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
out_8(&gpio->par_fbctl,
GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
#ifdef CONFIG_FSL_I2C
out_be16(&gpio->par_feci2c,
GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
#endif
#endif /* CONFIG_MCF5445x */
/* FlexBus Chipselect */
init_fbcs();
/*
* now the flash base address is no longer at 0 (Newer ColdFire family
@ -115,11 +229,6 @@ void cpu_init_f(void)
if (CONFIG_SYS_CS0_BASE != 0)
setvbr(CONFIG_SYS_CS0_BASE);
#ifdef CONFIG_FSL_I2C
out_be16(&gpio->par_feci2c,
GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
#endif
icache_enable();
}
@ -142,9 +251,95 @@ int cpu_init_r(void)
void uart_port_conf(int port)
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
#ifdef CONFIG_MCF5441x
pm_t *pm = (pm_t *) MMAP_PM;
#endif
/* Setup Ports: */
switch (port) {
#ifdef CONFIG_MCF5441x
case 0:
/* UART0 */
out_8(&pm->pmcr0, 24);
clrbits_8(&gpio->par_uart0,
~(GPIO_PAR_UART0_U0RXD_MASK | GPIO_PAR_UART0_U0TXD_MASK));
setbits_8(&gpio->par_uart0,
GPIO_PAR_UART0_U0RXD_U0RXD | GPIO_PAR_UART0_U0TXD_U0TXD);
break;
case 1:
/* UART1 */
out_8(&pm->pmcr0, 25);
clrbits_8(&gpio->par_uart1,
~(GPIO_PAR_UART1_U1RXD_MASK | GPIO_PAR_UART1_U1TXD_MASK));
setbits_8(&gpio->par_uart1,
GPIO_PAR_UART1_U1RXD_U1RXD | GPIO_PAR_UART1_U1TXD_U1TXD);
break;
case 2:
/* UART2 */
out_8(&pm->pmcr0, 26);
clrbits_8(&gpio->par_uart2,
~(GPIO_PAR_UART2_U2RXD_MASK | GPIO_PAR_UART2_U2TXD_MASK));
setbits_8(&gpio->par_uart2,
GPIO_PAR_UART2_U2RXD_U2RXD | GPIO_PAR_UART2_U2TXD_U2TXD);
break;
case 3:
/* UART3 */
out_8(&pm->pmcr0, 27);
clrbits_8(&gpio->par_dspi0,
~(GPIO_PAR_DSPI0_SIN_MASK | GPIO_PAR_DSPI0_SOUT_MASK));
setbits_8(&gpio->par_dspi0,
GPIO_PAR_DSPI0_SIN_U3RXD | GPIO_PAR_DSPI0_SOUT_U3TXD);
break;
case 4:
/* UART4 */
out_8(&pm->pmcr1, 24);
clrbits_8(&gpio->par_uart0,
~(GPIO_PAR_UART0_U0CTS_MASK | GPIO_PAR_UART0_U0RTS_MASK));
setbits_8(&gpio->par_uart0,
GPIO_PAR_UART0_U0CTS_U4TXD | GPIO_PAR_UART0_U0RTS_U4RXD);
break;
case 5:
/* UART5 */
out_8(&pm->pmcr1, 25);
clrbits_8(&gpio->par_uart1,
~(GPIO_PAR_UART1_U1CTS_MASK | GPIO_PAR_UART1_U1RTS_MASK));
setbits_8(&gpio->par_uart1,
GPIO_PAR_UART1_U1CTS_U5TXD | GPIO_PAR_UART1_U1RTS_U5RXD);
break;
case 6:
/* UART6 */
out_8(&pm->pmcr1, 26);
clrbits_8(&gpio->par_uart2,
~(GPIO_PAR_UART2_U2CTS_MASK | GPIO_PAR_UART2_U2RTS_MASK));
setbits_8(&gpio->par_uart2,
GPIO_PAR_UART2_U2CTS_U6TXD | GPIO_PAR_UART2_U2RTS_U6RXD);
break;
case 7:
/* UART7 */
out_8(&pm->pmcr1, 27);
clrbits_8(&gpio->par_ssi0h, ~GPIO_PAR_SSI0H_RXD_MASK);
clrbits_8(&gpio->par_ssi0l, ~GPIO_PAR_SSI0L_BCLK_MASK);
setbits_8(&gpio->par_ssi0h, GPIO_PAR_SSI0H_FS_U7TXD);
setbits_8(&gpio->par_ssi0l, GPIO_PAR_SSI0L_BCLK_U7RXD);
break;
case 8:
/* UART8 */
out_8(&pm->pmcr0, 28);
clrbits_8(&gpio->par_cani2c,
~(GPIO_PAR_CANI2C_I2C0SCL_MASK | GPIO_PAR_CANI2C_I2C0SDA_MASK));
setbits_8(&gpio->par_cani2c,
GPIO_PAR_CANI2C_I2C0SCL_U8TXD | GPIO_PAR_CANI2C_I2C0SDA_U8RXD);
break;
case 9:
/* UART9 */
out_8(&pm->pmcr1, 29);
clrbits_8(&gpio->par_cani2c,
~(GPIO_PAR_CANI2C_CAN1TX_MASK | GPIO_PAR_CANI2C_CAN1RX_MASK));
setbits_8(&gpio->par_cani2c,
GPIO_PAR_CANI2C_CAN1TX_U9TXD | GPIO_PAR_CANI2C_CAN1RX_U9RXD);
break;
#endif
#ifdef CONFIG_MCF5445x
case 0:
clrbits_8(&gpio->par_uart,
GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
@ -177,6 +372,7 @@ void uart_port_conf(int port)
GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD);
#endif
break;
#endif /* CONFIG_MCF5445x */
}
}
@ -186,6 +382,7 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
struct fec_info_s *info = (struct fec_info_s *)dev->priv;
#ifdef CONFIG_MCF5445x
if (setclear) {
#ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
@ -223,6 +420,21 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
#endif
}
}
#endif /* CONFIG_MCF5445x */
#ifdef CONFIG_MCF5441x
if (setclear) {
out_8(&gpio->par_fec, 0x03);
out_8(&gpio->srcr_fec, 0x0F);
clrsetbits_8(&gpio->par_simp0h, ~GPIO_PAR_SIMP0H_DAT_MASK,
GPIO_PAR_SIMP0H_DAT_GPIO);
clrsetbits_8(&gpio->pddr_g, ~GPIO_PDDR_G4_MASK,
GPIO_PDDR_G4_OUTPUT);
clrbits_8(&gpio->podr_g, ~GPIO_PODR_G4_MASK);
} else
clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC_MASK);
#endif
return 0;
}
#endif
@ -232,10 +444,24 @@ void cfspi_port_conf(void)
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
#ifdef CONFIG_MCF5445x
out_8(&gpio->par_dspi,
GPIO_PAR_DSPI_SIN_SIN |
GPIO_PAR_DSPI_SOUT_SOUT |
GPIO_PAR_DSPI_SCK_SCK);
#endif
#ifdef CONFIG_MCF5441x
pm_t *pm = (pm_t *) MMAP_PM;
out_8(&gpio->par_dspi0,
GPIO_PAR_DSPI0_SIN_DSPI0SIN | GPIO_PAR_DSPI0_SOUT_DSPI0SOUT |
GPIO_PAR_DSPI0_SCK_DSPI0SCK);
out_8(&gpio->srcr_dspiow, 3);
/* DSPI0 */
out_8(&pm->pmcr0, 23);
#endif
}
int cfspi_claim_bus(uint bus, uint cs)
@ -249,6 +475,7 @@ int cfspi_claim_bus(uint bus, uint cs)
/* Clear FIFO and resume transfer */
clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
#ifdef CONFIG_MCF5445x
switch (cs) {
case 0:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
@ -271,6 +498,20 @@ int cfspi_claim_bus(uint bus, uint cs)
setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
break;
}
#endif
#ifdef CONFIG_MCF5441x
switch (cs) {
case 0:
clrbits_8(&gpio->par_dspi0, ~GPIO_PAR_DSPI0_PCS0_MASK);
setbits_8(&gpio->par_dspi0, GPIO_PAR_DSPI0_PCS0_DSPI0PCS0);
break;
case 1:
clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
setbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
break;
}
#endif
return 0;
}
@ -283,6 +524,7 @@ void cfspi_release_bus(uint bus, uint cs)
/* Clear FIFO */
clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
#ifdef CONFIG_MCF5445x
switch (cs) {
case 0:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
@ -300,5 +542,11 @@ void cfspi_release_bus(uint bus, uint cs)
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
break;
}
#endif
#ifdef CONFIG_MCF5441x
if (cs == 1)
clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
#endif
}
#endif

89
arch/m68k/cpu/mcf5445x/speed.c
View File

@ -57,8 +57,10 @@ void clock_enter_limp(int lpdiv)
/* Round divider down to nearest power of two */
for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
#ifdef CONFIG_MCF5445x
/* Apply the divider to the system clock */
clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
#endif
/* Enable Limp Mode */
setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
@ -81,19 +83,76 @@ void clock_exit_limp(void)
;
}
/*
* get_clocks() fills in gd->cpu_clock and gd->bus_clk
*/
int get_clocks(void)
#ifdef CONFIG_MCF5441x
void setup_5441x_clocks(void)
{
ccm_t *ccm = (ccm_t *)MMAP_CCM;
pll_t *pll = (pll_t *)MMAP_PLL;
int temp, vco = 0, bootmod_ccr, pdr;
bootmod_ccr = (in_be16(&ccm->ccr) & CCM_CCR_BOOTMOD) >> 14;
switch (bootmod_ccr) {
case 0:
out_be32(&pll->pcr, 0x00000013);
out_be32(&pll->pdr, 0x00e70c61);
clock_exit_limp();
break;
case 2:
break;
case 3:
break;
}
/*Change frequency for Modelo SER1 USB host*/
#ifdef CONFIG_LOW_MCFCLK
temp = in_be32(&pll->pcr);
temp &= ~0x3f;
temp |= 5;
out_be32(&pll->pcr, temp);
temp = in_be32(&pll->pdr);
temp &= ~0x001f0000;
temp |= 0x00040000;
out_be32(&pll->pdr, temp);
__asm__("tpf");
#endif
setbits_be16(&ccm->misccr2, 0x02);
vco = ((in_be32(&pll->pcr) & PLL_CR_FBKDIV_BITS) + 1) *
CONFIG_SYS_INPUT_CLKSRC;
gd->vco_clk = vco;
gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
pdr = in_be32(&pll->pdr);
temp = (pdr & PLL_DR_OUTDIV1_BITS) + 1;
gd->cpu_clk = vco / temp; /* cpu clock */
gd->flb_clk = vco / temp; /* FlexBus clock */
gd->flb_clk >>= 1;
if (in_be16(ccm->misccr2) & 2) /* fsys/4 */
gd->flb_clk >>= 1;
temp = ((pdr & PLL_DR_OUTDIV2_BITS) >> 5) + 1;
gd->bus_clk = vco / temp; /* bus clock */
}
#endif
#ifdef CONFIG_MCF5445x
void setup_5445x_clocks(void)
{
ccm_t *ccm = (ccm_t *)MMAP_CCM;
pll_t *pll = (pll_t *)MMAP_PLL;
int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 };
int pllmult_pci[] = { 12, 6, 16, 8 };
int vco = 0, bPci, temp, fbtemp, pcrvalue;
int vco = 0, temp, fbtemp, pcrvalue;
int *pPllmult = NULL;
u16 fbpll_mask;
#ifdef CONFIG_PCI
int bPci;
#endif
#ifdef CONFIG_M54455EVB
u8 *cpld = (u8 *)(CONFIG_SYS_CS2_BASE + 3);
@ -105,14 +164,16 @@ int get_clocks(void)
((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
pPllmult = &pllmult_pci[0];
fbpll_mask = 3; /* 11b */
#ifdef CONFIG_PCI
bPci = 1;
#endif
} else {
pPllmult = &pllmult_nopci[0];
fbpll_mask = 7; /* 111b */
#ifdef CONFIG_PCI
gd->pci_clk = 0;
#endif
bPci = 0;
#endif
}
#ifdef CONFIG_M54455EVB
@ -212,6 +273,22 @@ int get_clocks(void)
#endif
}
#ifdef CONFIG_FSL_I2C
gd->i2c1_clk = gd->bus_clk;
#endif
}
#endif
/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
int get_clocks(void)
{
#ifdef CONFIG_MCF5441x
setup_5441x_clocks();
#endif
#ifdef CONFIG_MCF5445x
setup_5445x_clocks();
#endif
#ifdef CONFIG_FSL_I2C
gd->i2c1_clk = gd->bus_clk;
#endif

273
arch/m68k/cpu/mcf5445x/start.S
View File

@ -2,6 +2,9 @@
* Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
* Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
*
* Copyright 2010-2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
@ -21,8 +24,10 @@
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm-offsets.h>
#include <config.h>
#include <timestamp.h>
#include "version.h"
#include <asm/cache.h>
@ -43,8 +48,9 @@
addl #60,%sp; /* space for 15 regs */ \
rte;
#if defined(CONFIG_CF_SBF)
#if defined(CONFIG_SERIAL_BOOT)
#define ASM_DRAMINIT (asm_dram_init - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
#define ASM_DRAMINIT_N (asm_dram_init - TEXT_BASE)
#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
#endif
@ -55,10 +61,15 @@
* These vectors are to catch any un-intended traps.
*/
_vectors:
#if defined(CONFIG_CF_SBF)
#if defined(CONFIG_SERIAL_BOOT)
INITSP: .long 0 /* Initial SP */
#ifdef CONFIG_CF_SBF
INITPC: .long ASM_DRAMINIT /* Initial PC */
#endif
#ifdef CONFIG_SYS_NAND_BOOT
INITPC: .long ASM_DRAMINIT_N /* Initial PC */
#endif
#else
@ -95,7 +106,7 @@ vector1D: .long _FAULT /* Autovector Level 5 */
vector1E: .long _FAULT /* Autovector Level 6 */
vector1F: .long _FAULT /* Autovector Level 7 */
#if !defined(CONFIG_CF_SBF)
#if !defined(CONFIG_SERIAL_BOOT)
/* TRAP #0 - #15 */
vector20_2F:
@ -138,16 +149,26 @@ vector192_255:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
#endif
#if defined(CONFIG_CF_SBF)
#if defined(CONFIG_SERIAL_BOOT)
/* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
asm_sbf_img_hdr:
.long 0x00000000 /* checksum, not yet implemented */
.long 0x00030000 /* image length */
.long 0x00040000 /* image length */
.long CONFIG_SYS_TEXT_BASE /* image to be relocated at */
asm_dram_init:
move.w #0x2700,%sr /* Mask off Interrupt */
#ifdef CONFIG_SYS_NAND_BOOT
/* for assembly stack */
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
clr.l %sp@-
#endif
#ifdef CONFIG_CF_SBF
move.l #CONFIG_SYS_INIT_RAM_ADDR, %d0
movec %d0, %VBR
@ -180,7 +201,90 @@ asm_dram_init:
move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
move.l #0xFC008004, %a1
move.l #(CONFIG_SYS_CS0_MASK), (%a1)
#endif /* CONFIG_CF_SBF */
#ifdef CONFIG_MCF5441x
/* TC: enable all peripherals,
in the future only enable certain peripherals */
move.l #0xFC04002D, %a1
#if defined(CONFIG_CF_SBF)
move.b #23, (%a1) /* dspi */
#endif
move.b #46, (%a1) /* DDR */
/* slew settings */
move.l #0xEC094060, %a1
move.b #0, (%a1)
/* use vco instead of cpu*2 clock for ddr clock */
move.l #0xEC09001A, %a1
move.w #0xE01D, (%a1)
/* DDR settings */
move.l #0xFC0B8180, %a1
move.l #0x00000000, (%a1)
move.l #0x40000000, (%a1)
move.l #0xFC0B81AC, %a1
move.l #0x01030203, (%a1)
move.l #0xFC0B8000, %a1
move.l #0x01010101, (%a1)+ /* 0x00 */
move.l #0x00000101, (%a1)+ /* 0x04 */
move.l #0x01010100, (%a1)+ /* 0x08 */
move.l #0x01010000, (%a1)+ /* 0x0C */
move.l #0x00010101, (%a1)+ /* 0x10 */
move.l #0xFC0B8018, %a1
move.l #0x00010100, (%a1)+ /* 0x18 */
move.l #0x00000001, (%a1)+ /* 0x1C */
move.l #0x01000001, (%a1)+ /* 0x20 */
move.l #0x00000100, (%a1)+ /* 0x24 */
move.l #0x00010001, (%a1)+ /* 0x28 */
move.l #0x00000200, (%a1)+ /* 0x2C */
move.l #0x01000002, (%a1)+ /* 0x30 */
move.l #0x00000000, (%a1)+ /* 0x34 */
move.l #0x00000100, (%a1)+ /* 0x38 */
move.l #0x02000100, (%a1)+ /* 0x3C */
move.l #0x02000407, (%a1)+ /* 0x40 */
move.l #0x02030007, (%a1)+ /* 0x44 */
move.l #0x02000100, (%a1)+ /* 0x48 */
move.l #0x0A030203, (%a1)+ /* 0x4C */
move.l #0x00020708, (%a1)+ /* 0x50 */
move.l #0x00050008, (%a1)+ /* 0x54 */
move.l #0x04030002, (%a1)+ /* 0x58 */
move.l #0x00000004, (%a1)+ /* 0x5C */
move.l #0x020A0000, (%a1)+ /* 0x60 */
move.l #0x0C00000E, (%a1)+ /* 0x64 */
move.l #0x00002004, (%a1)+ /* 0x68 */
move.l #0x00000000, (%a1)+ /* 0x6C */
move.l #0x00100010, (%a1)+ /* 0x70 */
move.l #0x00100010, (%a1)+ /* 0x74 */
move.l #0x00000000, (%a1)+ /* 0x78 */
move.l #0x07990000, (%a1)+ /* 0x7C */
move.l #0xFC0B80A0, %a1
move.l #0x00000000, (%a1)+ /* 0xA0 */
move.l #0x00C80064, (%a1)+ /* 0xA4 */
move.l #0x44520002, (%a1)+ /* 0xA8 */
move.l #0x00C80023, (%a1)+ /* 0xAC */
move.l #0xFC0B80B4, %a1
move.l #0x0000C350, (%a1) /* 0xB4 */
move.l #0xFC0B80E0, %a1
move.l #0x04000000, (%a1)+ /* 0xE0 */
move.l #0x03000304, (%a1)+ /* 0xE4 */
move.l #0x40040000, (%a1)+ /* 0xE8 */
move.l #0xC0004004, (%a1)+ /* 0xEC */
move.l #0x0642C000, (%a1)+ /* 0xF0 */
move.l #0x00000642, (%a1)+ /* 0xF4 */
move.l #0xFC0B8024, %a1
tpf
move.l #0x01000100, (%a1) /* 0x24 */
move.l #0x2000, %d1
jsr asm_delay
#endif /* CONFIG_MCF5441x */
#ifdef CONFIG_MCF5445x
/* Dram Initialization a1, a2, and d0 */
/* mscr sdram */
move.l #0xFC0A4074, %a1
@ -203,7 +307,9 @@ dramsz_loop:
add.l #1, %d1
cmp.l #1, %d2
bne dramsz_loop
#ifdef CONFIG_SYS_NAND_BOOT
beq asm_nand_chk_status
#endif
/* SDRAM Chip 0 and 1 */
move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
or.l %d1, (%a1)
@ -275,7 +381,9 @@ dramsz_loop:
move.l #2000, %d1
jsr asm_delay
#endif /* CONFIG_MCF5445x */
#ifdef CONFIG_CF_SBF
/*
* DSPI Initialization
* a0 - general, sram - 0x80008000 - 32, see M54455EVB.h
@ -286,15 +394,28 @@ dramsz_loop:
*/
/* Enable pins for DSPI mode - chip-selects are enabled later */
asm_dspi_init:
#ifdef CONFIG_MCF5441x
move.l #0xEC09404E, %a1
move.l #0xEC09404F, %a2
move.b #0xFF, (%a1)
move.b #0x80, (%a2)
#endif
#ifdef CONFIG_MCF5445x
move.l #0xFC0A4063, %a0
move.b #0x7F, (%a0)
#endif
/* Configure DSPI module */
move.l #0xFC05C000, %a0
move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */
move.l #0xFC05C00C, %a0
#ifdef CONFIG_MCF5441x
move.l #0x3E000016, (%a0)
#endif
#ifdef CONFIG_MCF5445x
move.l #0x3E000011, (%a0)
#endif
move.l #0xFC05C034, %a2 /* dtfr */
move.l #0xFC05C03B, %a3 /* drfr */
@ -379,19 +500,148 @@ asm_dspi_rd_status:
move.b (%a3), %d1
rts
#endif /* CONFIG_CF_SBF */
#ifdef CONFIG_SYS_NAND_BOOT
/* copy 4 boot pages to dram as soon as possible */
/* each page is 996 bytes (1056 total with 60 ECC bytes */
move.l #0x00000000, %a1 /* src */
move.l #TEXT_BASE, %a2 /* dst */
move.l #0x3E0, %d0 /* sz in long */
asm_boot_nand_copy:
move.l (%a1)+, (%a2)+
subq.l #1, %d0
bne asm_boot_nand_copy
/* jump to memory and execute */
move.l #(asm_nand_init), %a0
jmp (%a0)
asm_nand_init:
/* exit nand boot-mode */
move.l #0xFC0FFF30, %a1
or.l #0x00000040, %d1
move.l %d1, (%a1)
/* initialize general use internal ram */
move.l #0, %d0
move.l #(CACR_STATUS), %a1 /* CACR */
move.l #(ICACHE_STATUS), %a2 /* icache */
move.l #(DCACHE_STATUS), %a3 /* dcache */
move.l %d0, (%a1)
move.l %d0, (%a2)
move.l %d0, (%a3)
/* invalidate and disable cache */
move.l #0x01004100, %d0 /* Invalidate cache cmd */
movec %d0, %CACR /* Invalidate cache */
move.l #0, %d0
movec %d0, %ACR0
movec %d0, %ACR1
movec %d0, %ACR2
movec %d0, %ACR3
/* Must disable global address */
move.l #0xFC008000, %a1
move.l #(CONFIG_SYS_CS0_BASE), (%a1)
move.l #0xFC008008, %a1
move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
move.l #0xFC008004, %a1
move.l #(CONFIG_SYS_CS0_MASK), (%a1)
/* NAND port configuration */
move.l #0xEC094048, %a1
move.b #0xFD, (%a1)+
move.b #0x5F, (%a1)+
move.b #0x04, (%a1)+
/* reset nand */
move.l #0xFC0FFF38, %a1 /* isr */
move.l #0x000e0000, (%a1)
move.l #0xFC0FFF08, %a2
move.l #0x00000000, (%a2)+ /* car */
move.l #0x11000000, (%a2)+ /* rar */
move.l #0x00000000, (%a2)+ /* rpt */
move.l #0x00000000, (%a2)+ /* rai */
move.l #0xFC0FFF2c, %a2 /* cfg */
move.l #0x00000000, (%a2)+ /* secsz */
move.l #0x000e0681, (%a2)+
move.l #0xFC0FFF04, %a2 /* cmd2 */
move.l #0xFF404001, (%a2)
move.l #0x000e0000, (%a1)
move.l #0x2000, %d1
jsr asm_delay
/* setup nand */
move.l #0xFC0FFF00, %a1
move.l #0x30700000, (%a1)+ /* cmd1 */
move.l #0x007EF000, (%a1)+ /* cmd2 */
move.l #0xFC0FFF2C, %a1
move.l #0x00000841, (%a1)+ /* secsz */
move.l #0x000e0681, (%a1)+ /* cfg */
move.l #100, %d4 /* 100 pages ~200KB */
move.l #4, %d2 /* start at 4 */
move.l #0xFC0FFF04, %a0 /* cmd2 */
move.l #0xFC0FFF0C, %a1 /* rar */
move.l #(TEXT_BASE + 0xF80), %a2 /* dst */
asm_nand_read:
move.l #0x11000000, %d0 /* rar */
or.l %d2, %d0
move.l %d0, (%a1)
add.l #1, %d2
move.l (%a0), %d0 /* cmd2 */
or.l #1, %d0
move.l %d0, (%a0)
move.l #0x200, %d1
jsr asm_delay
asm_nand_chk_status:
move.l #0xFC0FFF38, %a4 /* isr */
move.l (%a4), %d0
and.l #0x40000000, %d0
tst.l %d0
beq asm_nand_chk_status
move.l #0xFC0FFF38, %a4 /* isr */
move.l (%a4), %d0
or.l #0x000E0000, %d0
move.l %d0, (%a4)
move.l #0x200, %d3
move.l #0xFC0FC000, %a3 /* buf 1 */
asm_nand_copy:
move.l (%a3)+, (%a2)+
subq.l #1, %d3
bgt asm_nand_copy
subq.l #1, %d4
bgt asm_nand_read
/* jump to memory and execute */
move.l #(TEXT_BASE + 0x400), %a0
jmp (%a0)
#endif /* CONFIG_SYS_NAND_BOOT */
asm_delay:
nop
subq.l #1, %d1
bne asm_delay
rts
#endif /* CONFIG_CF_SBF */
#endif /* CONFIG_CF_SBF || CONFIG_NAND_U_BOOT */
.text
. = 0x400
.globl _start
_start:
#if !defined(CONFIG_CF_SBF)
#if !defined(CONFIG_SERIAL_BOOT)
nop
nop
move.w #0x2700,%sr /* Mask off Interrupt */
@ -418,12 +668,15 @@ _start:
movec %d0, %ACR1
movec %d0, %ACR2
movec %d0, %ACR3
#else
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR1
#endif
/* set stackpointer to end of internal ram to get some stackspace for
the first c-code */
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
clr.l %sp@-
#endif
move.l #__got_start, %a5 /* put relocation table address to a5 */

4
arch/m68k/cpu/mcf547x_8x/start.S
View File

@ -164,8 +164,8 @@ _start:
move.l #__got_start, %a5 /* put relocation table address to a5 */
bsr cpu_init_f /* run low-level CPU init code (from flash) */
bsr board_init_f /* run low-level board init code (from flash) */
jbsr cpu_init_f /* run low-level CPU init code (from flash) */
jbsr board_init_f /* run low-level board init code (from flash) */
/* board_init_f() does not return */

11
arch/m68k/include/asm/cache.h
View File

@ -1,7 +1,7 @@
/*
* ColdFire cache
*
* Copyright (C) 2004-2010 Freescale Semiconductor, Inc.
* Copyright 2004-2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@ -37,10 +37,9 @@
#if defined(CONFIG_MCF547x_8x) || defined(CONFIG_MCF5445x)
#define CONFIG_CF_V4
#if defined(CONFIG_MCF5441x)
#elif defined(CONFIG_MCF5441x)
#define CONFIG_CF_V4E /* Four Extra ACRn */
#endif
#endif
/* ***** CACR ***** */
/* V2 Core */
@ -87,7 +86,7 @@
#endif /* CONFIG_CF_V3 */
/* V4 Core */
#ifdef CONFIG_CF_V4
#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
#define CF_CACR_DEC (1 << 31)
#define CF_CACR_DW (1 << 30)
@ -113,7 +112,7 @@
#define CF_CACR_IDSP (1 << 7)
#define CF_CACR_EUSP (1 << 5)
#ifdef CONFIG_MCF5445x
#if defined(CONFIG_MCF5445x) || defined(CONFIG_MCF5441x)
#define CF_CACR_IVO (1 << 20)
#define CF_CACR_SPA (1 << 14)
#else
@ -148,7 +147,7 @@
#endif /* CONFIG_CF_V2 */
/* V4 Core */
#ifdef CONFIG_CF_V4
#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
#define CF_ACR_AMM (1 << 10)
#define CF_ACR_SP (1 << 3)
#endif /* CONFIG_CF_V4 */

2
arch/m68k/include/asm/global_data.h
View File

@ -34,7 +34,7 @@
typedef struct global_data {
bd_t *bd;
unsigned long flags;
unsigned long baudrate;
unsigned int baudrate;
unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long bus_clk;
#ifdef CONFIG_PCI

43
arch/m68k/include/asm/immap.h
View File

@ -1,7 +1,7 @@
/*
* ColdFire Internal Memory Map and Defines
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* Copyright 2004-2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@ -318,6 +318,47 @@
#define CONFIG_SYS_NUM_IRQS (128)
#endif /* CONFIG_M5329 && CONFIG_M5373 */
#if defined(CONFIG_M54418)
#include <asm/immap_5441x.h>
#include <asm/m5441x.h>
#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
#if (CONFIG_SYS_UART_PORT < 4)
#define CONFIG_SYS_UART_BASE (MMAP_UART0 + \
(CONFIG_SYS_UART_PORT * 0x4000))
#else
#define CONFIG_SYS_UART_BASE (MMAP_UART4 + \
((CONFIG_SYS_UART_PORT - 4) * 0x4000))
#endif
#define MMAP_DSPI MMAP_DSPI0
#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
/* Timer */
#ifdef CONFIG_MCFTMR
#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
#define CONFIG_SYS_TMRPND_REG (((int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
#define CONFIG_SYS_TMRINTR_PRI (6)
#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
#ifdef CONFIG_MCFPIT
#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
#define CONFIG_SYS_PIT_PRESCALE (6)
#endif
#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
#define CONFIG_SYS_NUM_IRQS (128)
#endif /* CONFIG_M54418 */
#if defined(CONFIG_M54451) || defined(CONFIG_M54455)
#include <asm/immap_5445x.h>
#include <asm/m5445x.h>

387
arch/m68k/include/asm/immap_5441x.h 100644
View File

@ -0,0 +1,387 @@
/*
* MCF5441x Internal Memory Map
*
* Copyright 2010-2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __IMMAP_5441X__
#define __IMMAP_5441X__
/* Module Base Addresses */
#define MMAP_XBS 0xFC004000
#define MMAP_FBCS 0xFC008000
#define MMAP_CAN0 0xFC020000
#define MMAP_CAN1 0xFC024000
#define MMAP_I2C1 0xFC038000
#define MMAP_DSPI1 0xFC03C000
#define MMAP_SCM 0xFC040000
#define MMAP_PM 0xFC04002C
#define MMAP_EDMA 0xFC044000
#define MMAP_INTC0 0xFC048000
#define MMAP_INTC1 0xFC04C000
#define MMAP_INTC2 0xFC050000
#define MMAP_IACK 0xFC054000
#define MMAP_I2C0 0xFC058000
#define MMAP_DSPI0 0xFC05C000
#define MMAP_UART0 0xFC060000
#define MMAP_UART1 0xFC064000
#define MMAP_UART2 0xFC068000
#define MMAP_UART3 0xFC06C000
#define MMAP_DTMR0 0xFC070000
#define MMAP_DTMR1 0xFC074000
#define MMAP_DTMR2 0xFC078000
#define MMAP_DTMR3 0xFC07C000
#define MMAP_PIT0 0xFC080000
#define MMAP_PIT1 0xFC084000
#define MMAP_PIT2 0xFC088000
#define MMAP_PIT3 0xFC08C000
#define MMAP_EPORT0 0xFC090000
#define MMAP_ADC 0xFC094000
#define MMAP_DAC0 0xFC098000
#define MMAP_DAC1 0xFC09C000
#define MMAP_RRTC 0xFC0A8000
#define MMAP_SIM 0xFC0AC000
#define MMAP_USBOTG 0xFC0B0000
#define MMAP_USBEHCI 0xFC0B4000
#define MMAP_SDRAM 0xFC0B8000
#define MMAP_SSI0 0xFC0BC000
#define MMAP_PLL 0xFC0C0000
#define MMAP_RNG 0xFC0C4000
#define MMAP_SSI1 0xFC0C8000
#define MMAP_ESDHC 0xFC0CC000
#define MMAP_FEC0 0xFC0D4000
#define MMAP_FEC1 0xFC0D8000
#define MMAP_L2_SW0 0xFC0DC000
#define MMAP_L2_SW1 0xFC0E0000
#define MMAP_NFC_RAM 0xFC0FC000
#define MMAP_NFC 0xFC0FF000
#define MMAP_1WIRE 0xEC008000
#define MMAP_I2C2 0xEC010000
#define MMAP_I2C3 0xEC014000
#define MMAP_I2C4 0xEC018000
#define MMAP_I2C5 0xEC01C000
#define MMAP_DSPI2 0xEC038000
#define MMAP_DSPI3 0xEC03C000
#define MMAP_UART4 0xEC060000
#define MMAP_UART5 0xEC064000
#define MMAP_UART6 0xEC068000
#define MMAP_UART7 0xEC06C000
#define MMAP_UART8 0xEC070000
#define MMAP_UART9 0xEC074000
#define MMAP_RCM 0xEC090000
#define MMAP_CCM 0xEC090000
#define MMAP_GPIO 0xEC094000
#include <asm/coldfire/crossbar.h>
#include <asm/coldfire/dspi.h>
#include <asm/coldfire/edma.h>
#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/flexcan.h>
#include <asm/coldfire/intctrl.h>
#include <asm/coldfire/ssi.h>
/* Serial Boot Facility (SBF) */
typedef struct sbf {
u8 resv0[0x18];
u16 sbfsr; /* Serial Boot Facility Status */
u8 resv1[0x6];
u16 sbfcr; /* Serial Boot Facility Control */
} sbf_t;
/* Reset Controller Module (RCM) */
typedef struct rcm {
u8 rcr;
u8 rsr;
} rcm_t;
/* Chip Configuration Module (CCM) */
typedef struct ccm {
u8 ccm_resv0[0x4]; /* 0x00 */
u16 ccr; /* 0x04 Chip Configuration */
u8 resv1[0x2]; /* 0x06 */
u16 rcon; /* 0x08 Reset Configuration */
u16 cir; /* 0x0A Chip Identification */
u8 resv2[0x2]; /* 0x0C */
u16 misccr; /* 0x0E Miscellaneous Control */
u16 cdrh; /* 0x10 Clock Divider */
u16 cdrl; /* 0x12 Clock Divider */
u16 uocsr; /* 0x14 USB On-the-Go Controller Status */
u16 uhcsr; /* 0x16 */
u16 misccr3; /* 0x18 */
u16 misccr2; /* 0x1A */
u16 adctsr; /* 0x1C */
u16 dactsr; /* 0x1E */
u16 sbfsr; /* 0x20 */
u16 sbfcr; /* 0x22 */
u32 fnacr; /* 0x24 */
} ccm_t;
/* General Purpose I/O Module (GPIO) */
typedef struct gpio {
u8 podr_a; /* 0x00 */
u8 podr_b; /* 0x01 */
u8 podr_c; /* 0x02 */
u8 podr_d; /* 0x03 */
u8 podr_e; /* 0x04 */
u8 podr_f; /* 0x05 */
u8 podr_g; /* 0x06 */
u8 podr_h; /* 0x07 */
u8 podr_i; /* 0x08 */
u8 podr_j; /* 0x09 */
u8 podr_k; /* 0x0A */
u8 rsvd0; /* 0x0B */
u8 pddr_a; /* 0x0C */
u8 pddr_b; /* 0x0D */
u8 pddr_c; /* 0x0E */
u8 pddr_d; /* 0x0F */
u8 pddr_e; /* 0x10 */
u8 pddr_f; /* 0x11 */
u8 pddr_g; /* 0x12 */
u8 pddr_h; /* 0x13 */
u8 pddr_i; /* 0x14 */
u8 pddr_j; /* 0x15 */
u8 pddr_k; /* 0x16 */
u8 rsvd1; /* 0x17 */
u8 ppdsdr_a; /* 0x18 */
u8 ppdsdr_b; /* 0x19 */
u8 ppdsdr_c; /* 0x1A */
u8 ppdsdr_d; /* 0x1B */
u8 ppdsdr_e; /* 0x1C */
u8 ppdsdr_f; /* 0x1D */
u8 ppdsdr_g; /* 0x1E */
u8 ppdsdr_h; /* 0x1F */
u8 ppdsdr_i; /* 0x20 */
u8 ppdsdr_j; /* 0x21 */
u8 ppdsdr_k; /* 0x22 */
u8 rsvd2; /* 0x23 */
u8 pclrr_a; /* 0x24 */
u8 pclrr_b; /* 0x25 */
u8 pclrr_c; /* 0x26 */
u8 pclrr_d; /* 0x27 */
u8 pclrr_e; /* 0x28 */
u8 pclrr_f; /* 0x29 */
u8 pclrr_g; /* 0x2A */
u8 pclrr_h; /* 0x2B */
u8 pclrr_i; /* 0x2C */
u8 pclrr_j; /* 0x2D */
u8 pclrr_k; /* 0x2E */
u8 rsvd3; /* 0x2F */
u16 pcr_a; /* 0x30 */
u16 pcr_b; /* 0x32 */
u16 pcr_c; /* 0x34 */
u16 pcr_d; /* 0x36 */
u16 pcr_e; /* 0x38 */
u16 pcr_f; /* 0x3A */
u16 pcr_g; /* 0x3C */
u16 pcr_h; /* 0x3E */
u16 pcr_i; /* 0x40 */
u16 pcr_j; /* 0x42 */
u16 pcr_k; /* 0x44 */
u16 rsvd4; /* 0x46 */
u8 par_fbctl; /* 0x48 */
u8 par_be; /* 0x49 */
u8 par_cs; /* 0x4A */
u8 par_cani2c; /* 0x4B */
u8 par_irqh; /* 0x4C */
u8 par_irql; /* 0x4D */
u8 par_dspi0; /* 0x4E */
u8 par_dspiow; /* 0x4F */
u8 par_timer; /* 0x50 */
u8 par_uart2; /* 0x51 */
u8 par_uart1; /* 0x52 */
u8 par_uart0; /* 0x53 */
u8 par_sdhch; /* 0x54 */
u8 par_sdhcl; /* 0x55 */
u8 par_simp0h; /* 0x56 */
u8 par_simp1h; /* 0x57 */
u8 par_ssi0h; /* 0x58 */
u8 par_ssi0l; /* 0x59 */
u8 par_dbg1h; /* 0x5A */
u8 par_dbg0h; /* 0x5B */
u8 par_dbgl; /* 0x5C */
u8 rsvd5; /* 0x5D */
u8 par_fec; /* 0x5E */
u8 rsvd6; /* 0x5F */
u8 mscr_sdram; /* 0x60 */
u8 rsvd7[3]; /* 0x61-0x63 */
u8 srcr_fb1; /* 0x64 */
u8 srcr_fb2; /* 0x65 */
u8 srcr_fb3; /* 0x66 */
u8 srcr_fb4; /* 0x67 */
u8 srcr_dspiow; /* 0x68 */
u8 srcr_cani2c; /* 0x69 */
u8 srcr_irq; /* 0x6A */
u8 srcr_timer; /* 0x6B */
u8 srcr_uart; /* 0x6C */
u8 srcr_fec; /* 0x6D */
u8 srcr_sdhc; /* 0x6E */
u8 srcr_simp0; /* 0x6F */
u8 srcr_ssi0; /* 0x70 */
u8 rsvd8[3]; /* 0x71-0x73 */
u16 urts_pol; /* 0x74 */
u16 ucts_pol; /* 0x76 */
u16 utxd_wom; /* 0x78 */
u32 urxd_wom; /* 0x7c */
u32 hcr1; /* 0x80 */
u32 hcr0; /* 0x84 */
} gpio_t;
/* SDRAM Controller (SDRAMC) */
typedef struct sdramc {
u32 cr00; /* 0x00 */
u32 cr01; /* 0x04 */
u32 cr02; /* 0x08 */
u32 cr03; /* 0x0C */
u32 cr04; /* 0x10 */
u32 cr05; /* 0x14 */
u32 cr06; /* 0x18 */
u32 cr07; /* 0x1C */
u32 cr08; /* 0x20 */
u32 cr09; /* 0x24 */
u32 cr10; /* 0x28 */
u32 cr11; /* 0x2C */
u32 cr12; /* 0x30 */
u32 cr13; /* 0x34 */
u32 cr14; /* 0x38 */
u32 cr15; /* 0x3C */
u32 cr16; /* 0x40 */
u32 cr17; /* 0x44 */
u32 cr18; /* 0x48 */
u32 cr19; /* 0x4C */
u32 cr20; /* 0x50 */
u32 cr21; /* 0x54 */
u32 cr22; /* 0x58 */
u32 cr23; /* 0x5C */
u32 cr24; /* 0x60 */
u32 cr25; /* 0x64 */
u32 cr26; /* 0x68 */
u32 cr27; /* 0x6C */
u32 cr28; /* 0x70 */
u32 cr29; /* 0x74 */
u32 cr30; /* 0x78 */
u32 cr31; /* 0x7C */
u32 cr32; /* 0x80 */
u32 cr33; /* 0x84 */
u32 cr34; /* 0x88 */
u32 cr35; /* 0x8C */
u32 cr36; /* 0x90 */
u32 cr37; /* 0x94 */
u32 cr38; /* 0x98 */
u32 cr39; /* 0x9C */
u32 cr40; /* 0xA0 */
u32 cr41; /* 0xA4 */
u32 cr42; /* 0xA8 */
u32 cr43; /* 0xAC */
u32 cr44; /* 0xB0 */
u32 cr45; /* 0xB4 */
u32 cr46; /* 0xB8 */
u32 cr47; /* 0xBC */
u32 cr48; /* 0xC0 */
u32 cr49; /* 0xC4 */
u32 cr50; /* 0xC8 */
u32 cr51; /* 0xCC */
u32 cr52; /* 0xD0 */
u32 cr53; /* 0xD4 */
u32 cr54; /* 0xD8 */
u32 cr55; /* 0xDC */
u32 cr56; /* 0xE0 */
u32 cr57; /* 0xE4 */
u32 cr58; /* 0xE8 */
u32 cr59; /* 0xEC */
u32 cr60; /* 0xF0 */
u32 cr61; /* 0xF4 */
u32 cr62; /* 0xF8 */
u32 cr63; /* 0xFC */
u32 rsvd3[32]; /* 0xF4-0x1A8 */
u32 rcrcr; /* 0x180 */
u32 swrcr; /* 0x184 */
u32 rcr; /* 0x188 */
u32 msovr; /* 0x18C */
u32 rcrdbg; /* 0x190 */
u32 sl0adj; /* 0x194 */
u32 sl1adj; /* 0x198 */
u32 sl2adj; /* 0x19C */
u32 sl3adj; /* 0x1A0 */
u32 sl4adj; /* 0x1A4 */
u32 flight_tm; /* 0x1A8 */
u32 padcr; /* 0x1AC */
} sdramc_t;
/* Phase Locked Loop (PLL) */
typedef struct pll {
u32 pcr; /* Control */
u32 pdr; /* Divider */
u32 psr; /* Status */
} pll_t;
typedef struct scm {
u8 rsvd1[19]; /* 0x00 - 0x12 */
u8 wcr; /* 0x13 */
u16 rsvd2; /* 0x14 - 0x15 */
u16 cwcr; /* 0x16 */
u8 rsvd3[3]; /* 0x18 - 0x1A */
u8 cwsr; /* 0x1B */
u8 rsvd4[3]; /* 0x1C - 0x1E */
u8 scmisr; /* 0x1F */
u32 rsvd5; /* 0x20 - 0x23 */
u32 bcr; /* 0x24 */
u8 rsvd6[72]; /* 0x28 - 0x6F */
u32 cfadr; /* 0x70 */
u8 rsvd7; /* 0x74 */
u8 cfier; /* 0x75 */
u8 cfloc; /* 0x76 */
u8 cfatr; /* 0x77 */
u32 rsvd8; /* 0x78 - 0x7B */
u32 cfdtr; /* 0x7C */
} scm_t;
typedef struct pm {
u8 pmsr0; /* */
u8 pmcr0;
u8 pmsr1;
u8 pmcr1;
u32 pmhr0;
u32 pmlr0;
u32 pmhr1;
u32 pmlr1;
} pm_t;
#endif /* __IMMAP_5441X__ */

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arch/m68k/include/asm/m5441x.h 100644
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@ -0,0 +1,887 @@
/*
* MCF5441X Internal Memory Map
*
* Copyright 2010-2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __MCF5441X__
#define __MCF5441X__
/* Interrupt Controller (INTC) */
#define INT0_LO_RSVD0 (0)
#define INT0_LO_EPORT1 (1)
#define INT0_LO_EPORT2 (2)
#define INT0_LO_EPORT3 (3)
#define INT0_LO_EPORT4 (4)
#define INT0_LO_EPORT5 (5)
#define INT0_LO_EPORT6 (6)
#define INT0_LO_EPORT7 (7)
#define INT0_LO_EDMA_00 (8)
#define INT0_LO_EDMA_01 (9)
#define INT0_LO_EDMA_02 (10)
#define INT0_LO_EDMA_03 (11)
#define INT0_LO_EDMA_04 (12)
#define INT0_LO_EDMA_05 (13)
#define INT0_LO_EDMA_06 (14)
#define INT0_LO_EDMA_07 (15)
#define INT0_LO_EDMA_08 (16)
#define INT0_LO_EDMA_09 (17)
#define INT0_LO_EDMA_10 (18)
#define INT0_LO_EDMA_11 (19)
#define INT0_LO_EDMA_12 (20)
#define INT0_LO_EDMA_13 (21)
#define INT0_LO_EDMA_14 (22)
#define INT0_LO_EDMA_15 (23)
#define INT0_LO_EDMA_ERR (24)
#define INT0_LO_SCM (25)
#define INT0_LO_UART0 (26)
#define INT0_LO_UART1 (27)
#define INT0_LO_UART2 (28)
#define INT0_LO_UART3 (29)
#define INT0_LO_I2C0 (30)
#define INT0_LO_DSPI0 (31)
#define INT0_HI_DTMR0 (32)
#define INT0_HI_DTMR1 (33)
#define INT0_HI_DTMR2 (34)
#define INT0_HI_DTMR3 (35)
#define INT0_HI_MACNET0_TXF (36)
#define INT0_HI_MACNET0_TXB (37)
#define INT0_HI_MACNET0_UN (38)
#define INT0_HI_MACNET0_RL (39)
#define INT0_HI_MACNET0_RXF (40)
#define INT0_HI_MACNET0_RXB (41)
#define INT0_HI_MACNET0_MII (42)
#define INT0_HI_MACNET0_LC (43)
/* not used 44 */
#define INT0_HI_MACNET0_GRA (45)
#define INT0_HI_MACNET0_EBERR (46)
#define INT0_HI_MACNET0_BABT (47)
#define INT0_HI_MACNET0_BABR (48)
#define INT0_HI_MACNET1_TXF (49)
#define INT0_HI_MACNET1_TXB (50)
#define INT0_HI_MACNET1_UN (51)
#define INT0_HI_MACNET1_RL (52)
#define INT0_HI_MACNET1_RXF (53)
#define INT0_HI_MACNET1_RXB (54)
#define INT0_HI_MACNET1_MII (55)
#define INT0_HI_MACNET1_LC (56)
/* not used 57 */
#define INT0_HI_MACNET1_GRA (58)
#define INT0_HI_MACNET1_EBERR (59)
#define INT0_HI_MACNET1_BABT (60)
#define INT0_HI_MACNET1_BABR (61)
#define INT0_HI_SCMIR (62)
#define INT0_HI_OW (63)
#define INT1_LO_CAN0_IFG (0)
#define INT1_LO_CAN0_BOFF (1)
/* not used 2 */
#define INT1_LO_CAN0_TXRXWRN (3)
#define INT1_LO_CAN1_IFG (4)
#define INT1_LO_CAN1_BOFF (5)
/* not used 6 */
#define INT1_LO_CAN1_TXRXWRN (7)
#define INT1_LO_EDMA_16 (8)
#define INT1_LO_EDMA_17 (9)
#define INT1_LO_EDMA_18 (10)
#define INT1_LO_EDMA_19 (11)
#define INT1_LO_EDMA_20 (12)
#define INT1_LO_EDMA_21 (13)
#define INT1_LO_EDMA_22 (14)
#define INT1_LO_EDMA_23 (15)
#define INT1_LO_EDMA_24 (16)
#define INT1_LO_EDMA_25 (17)
#define INT1_LO_EDMA_26 (18)
#define INT1_LO_EDMA_27 (19)
#define INT1_LO_EDMA_28 (20)
#define INT1_LO_EDMA_29 (21)
#define INT1_LO_EDMA_30 (22)
#define INT1_LO_EDMA_31 (23)
#define INT1_LO_EDMA_32 (24)
#define INT1_LO_EDMA_33 (25)
#define INT1_LO_EDMA_34 (26)
#define INT1_LO_EDMA_35 (27)
#define INT1_LO_EDMA_36 (28)
#define INT1_LO_EDMA_37 (29)
#define INT1_LO_EDMA_38 (30)
#define INT1_LO_EDMA_39 (31)
#define INT1_LO_EDMA_40 (32)
#define INT1_HI_EDMA_41 (33)
#define INT1_HI_EDMA_42 (34)
#define INT1_HI_EDMA_43 (35)
#define INT1_HI_EDMA_44 (36)
#define INT1_HI_EDMA_45 (37)
#define INT1_HI_EDMA_46 (38)
#define INT1_HI_EDMA_47 (39)
#define INT1_HI_EDMA_48 (40)
#define INT1_HI_EDMA_49 (41)
#define INT1_HI_EDMA_50 (42)
#define INT1_HI_EDMA_51 (43)
#define INT1_HI_EDMA_52 (44)
#define INT1_HI_EDMA_53 (45)
#define INT1_HI_EDMA_54 (46)
#define INT1_HI_EDMA_55 (47)
#define INT1_HI_UART4 (48)
#define INT1_HI_UART5 (49)
#define INT1_HI_UART6 (50)
#define INT1_HI_UART7 (51)
#define INT1_HI_UART8 (52)
#define INT1_HI_UART9 (53)
#define INT1_HI_DSPI1 (54)
#define INT1_HI_DSPI2 (55)
#define INT1_HI_DSPI3 (56)
#define INT1_HI_I2C1 (57)
#define INT1_HI_I2C2 (58)
#define INT1_HI_I2C3 (59)
#define INT1_HI_I2C4 (60)
#define INT1_HI_I2C5 (61)
#define INT2_LO_EDMA56_63 (0)
#define INT2_LO_PWM_SM0SR_CF (1)
#define INT2_LO_PWM_SM1SR_CF (2)
#define INT2_LO_PWM_SM2SR_CF (3)
#define INT2_LO_PWM_SM3SR_CF (4)
#define INT2_LO_PWM_SM0SR_RF (5)
#define INT2_LO_PWM_SM1SR_RF (6)
#define INT2_LO_PWM_SM2SR_RF (7)
#define INT2_LO_PWM_SM3SR_RF (8)
#define INT2_LO_PWM_FSR (9)
#define INT2_LO_PWM_SMSR_REF (10)
#define INT2_LO_PLL_SR_LOCF (11)
#define INT2_LO_PLL_SR_LOLF (12)
#define INT2_LO_PIT0_PIF (13)
#define INT2_LO_PIT1_PIF (14)
#define INT2_LO_PIT2_PIF (15)
#define INT2_LO_PIT3_PIF (16)
#define INT2_LO_USBOTG_USBSTS (17)
#define INT2_LO_USBH_USBSTS (18)
/* not used 19-20 */
#define INT2_LO_SSI0 (21)
#define INT2_LO_SSI1 (22)
#define INT2_LO_NFC (23)
/* not used 24-25 */
#define INT2_LO_RTC (26)
#define INT2_LO_CCM_UOCSR (27)
#define INT2_LO_RNG_EI (28)
#define INT2_LO_SIM1_DATA (29)
#define INT2_LO_SIM1 (30)
#define INT2_LO_SDHC (31)
/* not used 32-37 */
#define INT2_HI_L2SW_BERR (38)
#define INT2_HI_L2SW_RXB (39)
#define INT2_HI_L2SW_RXF (40)
#define INT2_HI_L2SW_TXB (41)
#define INT2_HI_L2SW_TXF (42)
#define INT2_HI_L2SW_QM (43)
#define INT2_HI_L2SW_OD0 (44)
#define INT2_HI_L2SW_OD1 (45)
#define INT2_HI_L2SW_OD2 (46)
#define INT2_HI_L2SW_LRN (47)
#define INT2_HI_MACNET0_TS (48)
#define INT2_HI_MACNET0_WAKE (49)
#define INT2_HI_MACNET0_PLR (50)
/* not used 51-54 */
#define INT2_HI_MACNET1_TS (51)
#define INT2_HI_MACNET1_WAKE (52)
#define INT2_HI_MACNET1_PLR (53)
/* Serial Boot Facility (SBF) */
#define SBF_SBFCR_BLDIV(x) (((x)&0x000F))
#define SBF_SBFCR_FR (0x0010)
/* Reset Controller Module (RCM) */
#define RCM_RCR_SOFTRST (0x80)
#define RCM_RCR_FRCRSTOUT (0x40)
#define RCM_RSR_SOFT (0x20)
#define RCM_RSR_LOC (0x10)
#define RCM_RSR_POR (0x08)
#define RCM_RSR_EXT (0x04)
#define RCM_RSR_WDR_CORE (0x02)
#define RCM_RSR_LOL (0x01)
/* Chip Configuration Module (CCM) */
#define CCM_CCR_BOOTMOD (0xC000)
#define CCM_CCR_PLLMULT (0x0FC0)
#define CCM_CCR_BOOTPS (0x0030)
#define CCM_CCR_BOOTPS_32 (0x0000)
#define CCM_CCR_BOOTPS_16 (0x0020)
#define CCM_CCR_BOOTPS_8 (0x0010)
#define CCM_CCR_BOOTPS_ (0x0000)
#define CCM_CCR_ALESEL (0x0008)
#define CCM_CCR_OSCMOD (0x0004)
#define CCM_CCR_PLLMOD (0x0002)
#define CCM_CCR_BOOTMEM (0x0001)
#define CCM_CIR_PIN_MASK (0xFFC0)
#define CCM_CIR_PRN_MASK (0x003F)
#define CCM_CIR_PIN_MCF54410 (0x9F<<6)
#define CCM_CIR_PIN_MCF54415 (0xA0<<6)
#define CCM_CIR_PIN_MCF54416 (0xA1<<6)
#define CCM_CIR_PIN_MCF54417 (0xA2<<6)
#define CCM_CIR_PIN_MCF54418 (0xA3<<6)
#define CCM_MISCCR_PWM_EXTCLK(x) (((x)&(0x0003)<<14)
#define CCM_MISCCR_PWM_EXTCLK_MASK (0x3FFF)
#define CCM_MISCCR_PWM_EXTCLK_TMR0 (0x0000)
#define CCM_MISCCR_PWM_EXTCLK_TMR1 (0x4000)
#define CCM_MISCCR_PWM_EXTCLK_TMR2 (0x8000)
#define CCM_MISCCR_PWM_EXTCLK_TMR3 (0xC000)
#define CCM_MISCCR_LIMP (0x1000)
#define CCM_MISCCR_BME (0x0800)
#define CCM_MISCCR_BMT(x) (((x)&0x0007)<<8)
#define CCM_MISCCR_BMT_65536 (0)
#define CCM_MISCCR_BMT_32768 (1)
#define CCM_MISCCR_BMT_16384 (2)
#define CCM_MISCCR_BMT_8192 (3)
#define CCM_MISCCR_BMT_4096 (4)
#define CCM_MISCCR_BMT_2048 (5)
#define CCM_MISCCR_BMT_1024 (6)
#define CCM_MISCCR_BMT_512 (7)
#define CCM_MISCCR_SDHCSRC (0x0040)
#define CCM_MISCCR_SSI1SRC (0x0020)
#define CCM_MISCCR_SSI0SRC (0x0010)
#define CCM_MISCCR_USBHOC (0x0008)
#define CCM_MISCCR_USBOOC (0x0004)
#define CCM_MISCCR_USBPUE (0x0002)
#define CCM_MISCCR_USBSRC (0x0001)
#define CCM_CDRH_SSI0DIV(x) (((x)&0x00FF)<<8)
#define CCM_CDRH_SSI0DIV_MASK (0x00FF)
#define CCM_CDRH_SSI1DIV(x) (((x)&0x00FF))
#define CCM_CDRH_SSI1DIV_MASK (0xFF00)
#define CCM_CDRL_LPDIV(x) (((x)&0x000F)<<8)
#define CCM_CDRL_LPDIV_MASK (0xFF0F)
#define CCM_CDR_LPDIV(x) CCM_CDRL_LPDIV(x)
#define CCM_UOCSR_DPPD (0x2000)
#define CCM_UOCSR_DMPD (0x1000)
#define CCM_UOCSR_DRV_VBUS (0x0800)
#define CCM_UOCSR_CRG_VBUS (0x0400)
#define CCM_UOCSR_DCR_VBUS (0x0200)
#define CCM_UOCSR_DPPU (0x0100)
#define CCM_UOCSR_AVLD (0x0080)
#define CCM_UOCSR_BVLD (0x0040)
#define CCM_UOCSR_VVLD (0x0020)
#define CCM_UOCSR_SEND (0x0010)
#define CCM_UOCSR_PWRFLT (0x0008)
#define CCM_UOCSR_WKUP (0x0004)
#define CCM_UOCSR_UOMIE (0x0002)
#define CCM_UOCSR_XPDE (0x0001)
#define CCM_UHCSR_DRV_VBUS (0x0010)
#define CCM_UHCSR_PWRFLT (0x0008)
#define CCM_UHCSR_WKUP (0x0004)
#define CCM_UHCSR_UOMIE (0x0002)
#define CCM_UHCSR_XPDE (0x0001)
#define CCM_MISCCR3_TMR_ENET (0x1000)
#define CCM_MISCCR3_ENETCLK(x) (((x)&7)<<8)
#define CCM_MISCCR3_ENETCLK_MASK (0xF8FF)
#define CCM_MISCCR3_ENETCLK_MII (0x0700)
#define CCM_MISCCR3_ENETCLK_OSC (0x0600)
#define CCM_MISCCR3_ENETCLK_USB (0x0500)
#define CCM_MISCCR3_ENETCLK_TMR3 (0x0400)
#define CCM_MISCCR3_ENETCLK_TMR2 (0x0300)
#define CCM_MISCCR3_ENETCLK_TMR1 (0x0200)
#define CCM_MISCCR3_ENETCLK_TMR0 (0x0100)
#define CCM_MISCCR3_ENETCLK_INTBUS (0x0000)
#define CCM_MISCCR2_EXTCLKBYP (0x8000)
#define CCM_MISCCR2_DDR2CLK (0x4000)
#define CCM_MISCCR2_RGPIO_HALF (0x2000)
#define CCM_MISCCR2_SWTSCR (0x1000)
#define CCM_MISCCR2_PLLMODE(x) (((x)&7)<<8)
#define CCM_MISCCR2_PLLMODE_MASK (0xF8FF)
#define CCM_MISCCR2_DCCBYP (0x0080)
#define CCM_MISCCR2_DAC1SEL (0x0040)
#define CCM_MISCCR2_DAC0SEL (0x0020)
#define CCM_MISCCR2_ADCEN (0x0010)
#define CCM_MISCCR2_ADC7SEL (0x0008)
#define CCM_MISCCR2_ADC3SEL (0x0004)
#define CCM_MISCCR2_FBHALF (0x0002)
#define CCM_MISCCR2_ULPI (0x0001)
#define CCM_FNACR_PCR(x) (((x)&0x0F)<<24)
#define CCM_FNACR_PCR_MASK (0xF0FFFFFF)
#define CCM_FNACR_MCC(x) ((x)&0xFFFF)
#define CCM_FNACR_MCC_MASK (0xFFFF0000)
/* General Purpose I/O Module (GPIO) */
#define GPIO_PAR_FBCTL_ALE(x) (((x)&3)<<6)
#define GPIO_PAR_FBCTL_ALE_MASK (0x3F)
#define GPIO_PAR_FBCTL_ALE_FB_ALE (0xC0)
#define GPIO_PAR_FBCTL_ALE_FB_TS (0x80)
#define GPIO_PAR_FBCTL_ALE_GPIO (0x00)
#define GPIO_PAR_FBCTL_OE(x) (((x)&3)<<4)
#define GPIO_PAR_FBCTL_OE_MASK (0xCF)
#define GPIO_PAR_FBCTL_OE_FB_OE (0x30)
#define GPIO_PAR_FBCTL_OE_FB_TBST (0x20)
#define GPIO_PAR_FBCTL_OE_NFC_RE (0x20)
#define GPIO_PAR_FBCTL_OE_GPIO (0x00)
#define GPIO_PAR_FBCTL_FBCLK (0x08)
#define GPIO_PAR_FBCTL_RW (0x04)
#define GPIO_PAR_FBCTL_TA(x) ((x)&3)
#define GPIO_PAR_FBCTL_TA_MASK (0xFC)
#define GPIO_PAR_FBCTL_TA_TA (0x03)
#define GPIO_PAR_FBCTL_TA_NFC_RB (0x01)
#define GPIO_PAR_FBCTL_TA_GPIO (0x00)
#define GPIO_PAR_BE_BS3(x) (((x)&0x03)<<6)
#define GPIO_PAR_BE_BE3_MASK (0x3F)
#define GPIO_PAR_BE_BE3_BE3 (0xC0)
#define GPIO_PAR_BE_BE3_CS3 (0x80)
#define GPIO_PAR_BE_BE3_FB_A1 (0x40)
#define GPIO_PAR_BE_BE3_NFC_ALE (0x40)
#define GPIO_PAR_BE_BE3_GPIO (0x00)
#define GPIO_PAR_BE_BS2(x) (((x)&0x03)<<4)
#define GPIO_PAR_BE_BE2_MASK (0xCF)
#define GPIO_PAR_BE_BE2_BE2 (0x30)
#define GPIO_PAR_BE_BE2_CS2 (0x20)
#define GPIO_PAR_BE_BE2_FB_A0 (0x10)
#define GPIO_PAR_BE_BE2_NFC_CLE (0x10)
#define GPIO_PAR_BE_BE2_GPIO (0x00)
#define GPIO_PAR_BE_BS1(x) (((x)&0x03)<<2)
#define GPIO_PAR_BE_BE1_MASK (0xF3)
#define GPIO_PAR_BE_BE1_BE1 (0x0C)
#define GPIO_PAR_BE_BE1_FB_TSZ1 (0x08)
#define GPIO_PAR_BE_BE1_GPIO (0x00)
#define GPIO_PAR_BE_BS0(x) ((x)&0x03)
#define GPIO_PAR_BE_BE0_MASK (0xFC)
#define GPIO_PAR_BE_BE0_BE0 (0x03)
#define GPIO_PAR_BE_BE0_FB_TSZ0 (0x02)
#define GPIO_PAR_BE_BE0_GPIO (0x00)
#define GPIO_PAR_CS_CS5(x) (((x)&0x03)<<6)
#define GPIO_PAR_CS_CS5_MASK (0x3F)
#define GPIO_PAR_CS_CS5_CS5 (0xC0)
#define GPIO_PAR_CS_CS5_DACK1 (0x80)
#define GPIO_PAR_CS_CS5_GPIO (0x00)
#define GPIO_PAR_CS_CS4(x) (((x)&0x03)<<4)
#define GPIO_PAR_CS_CS4_MASK (0xCF)
#define GPIO_PAR_CS_CS4_CS4 (0x30)
#define GPIO_PAR_CS_CS4_DREQ1 (0x20)
#define GPIO_PAR_CS_CS4_GPIO (0x00)
#define GPIO_PAR_CS_CS1(x) (((x)&0x03)<<2)
#define GPIO_PAR_CS_CS1_MASK (0xF3)
#define GPIO_PAR_CS_CS1_CS1 (0x0C)
#define GPIO_PAR_CS_CS1_NFC_CE (0x04)
#define GPIO_PAR_CS_CS1_GPIO (0x00)
#define GPIO_PAR_CS_CS0_CS0 (0x01)
#define GPIO_PAR_CANI2C_I2C0SCL(x) (((x)&0x03)<<6)
#define GPIO_PAR_CANI2C_I2C0SCL_MASK (0x3F)
#define GPIO_PAR_CANI2C_I2C0SCL_I2C0SCL (0xC0)
#define GPIO_PAR_CANI2C_I2C0SCL_U8TXD (0x80)
#define GPIO_PAR_CANI2C_I2C0SCL_CAN0TX (0x40)
#define GPIO_PAR_CANI2C_I2C0SCL_GPIO (0x00)
#define GPIO_PAR_CANI2C_I2C0SDA(x) (((x)&0x03)<<4)
#define GPIO_PAR_CANI2C_I2C0SDA_MASK (0xCF)
#define GPIO_PAR_CANI2C_I2C0SDA_I2C0SDA (0x30)
#define GPIO_PAR_CANI2C_I2C0SDA_U8RXD (0x20)
#define GPIO_PAR_CANI2C_I2C0SDA_CAN0RX (0x10)
#define GPIO_PAR_CANI2C_I2C0SDA_GPIO (0x00)
#define GPIO_PAR_CANI2C_CAN1TX(x) (((x)&0x03)<<2)
#define GPIO_PAR_CANI2C_CAN1TX_MASK (0xF3)
#define GPIO_PAR_CANI2C_CAN1TX_CAN1TX (0x0C)
#define GPIO_PAR_CANI2C_CAN1TX_U9TXD (0x08)
#define GPIO_PAR_CANI2C_CAN1TX_I2C1SCL (0x04)
#define GPIO_PAR_CANI2C_CAN1TX_GPIO (0x00)
#define GPIO_PAR_CANI2C_CAN1RX(x) ((x)&0x03)
#define GPIO_PAR_CANI2C_CAN1RX_MASK (0xFC)
#define GPIO_PAR_CANI2C_CAN1RX_CAN1RX (0x03)
#define GPIO_PAR_CANI2C_CAN1RX_U9RXD (0x02)
#define GPIO_PAR_CANI2C_CAN1RX_I2C1SDA (0x01)
#define GPIO_PAR_CANI2C_CAN1RX_GPIO (0x00)
#define GPIO_PAR_IRQH_IRQ7 (0x10)
#define GPIO_PAR_IRQH_IRQ4(x) (((x)&0x03)<<2)
#define GPIO_PAR_IRQH_IRQ4_MASK (0xF3)
#define GPIO_PAR_IRQH_IRQ4_IRQ4 (0x0C)
#define GPIO_PAR_IRQH_IRQ4_DREQ0 (0x08)
#define GPIO_PAR_IRQH_IRQ4_GPIO (0x00)
#define GPIO_PAR_IRQH_IRQ1 (0x03)
#define GPIO_PAR_IRQL_IRQ6(x) (((x)&0x03)<<6)
#define GPIO_PAR_IRQL_IRQ6_MASK (0x3F)
#define GPIO_PAR_IRQL_IRQ6_IRQ6 (0xC0)
#define GPIO_PAR_IRQL_IRQ6_USBCLKIN (0x40)
#define GPIO_PAR_IRQL_IRQ6_GPIO (0x00)
#define GPIO_PAR_IRQL_IRQ3(x) (((x)&0x03)<<4)
#define GPIO_PAR_IRQL_IRQ3_MASK (0xCF)
#define GPIO_PAR_IRQL_IRQ3_IRQ3 (0x30)
#define GPIO_PAR_IRQL_IRQ3_DSPI0_PCS3 (0x20)
#define GPIO_PAR_IRQL_IRQ3_USB1_VBUS_EN (0x10)
#define GPIO_PAR_IRQL_IRQ3_GPIO (0x00)
#define GPIO_PAR_IRQL_IRQ2(x) (((x)&0x03)<<2)
#define GPIO_PAR_IRQL_IRQ2_MASK (0xF3)
#define GPIO_PAR_IRQL_IRQ2_IRQ2 (0x0C)
#define GPIO_PAR_IRQL_IRQ2_DSPI0_PCS2 (0x08)
#define GPIO_PAR_IRQL_IRQ2_USB1_VBUS_OC (0x04)
#define GPIO_PAR_IRQL_IRQ2_GPIO (0x00)
#define GPIO_PAR_DSPI0_SIN(x) (((x)&0x03)<<6)
#define GPIO_PAR_DSPI0_SIN_MASK (0x3F)
#define GPIO_PAR_DSPI0_SIN_DSPI0SIN (0xC0)
#define GPIO_PAR_DSPI0_SIN_SBF_DI (0xC0)
#define GPIO_PAR_DSPI0_SIN_U3RXD (0x80)
#define GPIO_PAR_DSPI0_SIN_SDHC_CMD (0x40)
#define GPIO_PAR_DSPI0_SIN_GPIO (0x00)
#define GPIO_PAR_DSPI0_SOUT(x) (((x)&0x03)<<4)
#define GPIO_PAR_DSPI0_SOUT_MASK (0xCF)
#define GPIO_PAR_DSPI0_SOUT_DSPI0SOUT (0x30)
#define GPIO_PAR_DSPI0_SOUT_SBF_DO (0x30)
#define GPIO_PAR_DSPI0_SOUT_U3TXD (0x20)
#define GPIO_PAR_DSPI0_SOUT_SDHC_DAT0 (0x10)
#define GPIO_PAR_DSPI0_SOUT_GPIO (0x00)
#define GPIO_PAR_DSPI0_SCK(x) (((x)&0x03)<<2)
#define GPIO_PAR_DSPI0_SCK_MASK (0xF3)
#define GPIO_PAR_DSPI0_SCK_DSPI0SCK (0x0C)
#define GPIO_PAR_DSPI0_SCK_SBF_CK (0x0C)
#define GPIO_PAR_DSPI0_SCK_I2C3SCL (0x08)
#define GPIO_PAR_DSPI0_SCK_SDHC_CLK (0x04)
#define GPIO_PAR_DSPI0_SCK_GPIO (0x00)
#define GPIO_PAR_DSPI0_PCS0(x) ((x)&0x03)
#define GPIO_PAR_DSPI0_PCS0_MASK (0xFC)
#define GPIO_PAR_DSPI0_PCS0_DSPI0PCS0 (0x03)
#define GPIO_PAR_DSPI0_PCS0_SS (0x03)
#define GPIO_PAR_DSPI0_PCS0_I2C3SDA (0x02)
#define GPIO_PAR_DSPI0_PCS0_SDHC_DAT3 (0x01)
#define GPIO_PAR_DSPI0_PCS0_GPIO (0x00)
#define GPIO_PAR_DSPIOW_DSPI0PSC1 (0x80)
#define GPIO_PAR_DSPIOW_SBF_CS (0x80)
#define GPIO_PAR_DSPIOW_OWDAT (((x)&0x03)<<4)
#define GPIO_PAR_DSPIOW_OWDAT_MASK (0xCF)
#define GPIO_PAR_DSPIOW_OWDAT_OWDAT (0x30)
#define GPIO_PAR_DSPIOW_OWDAT_DACK0 (0x20)
#define GPIO_PAR_DSPIOW_OWDAT_GPIO (0x00)
#define GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6)
#define GPIO_PAR_TIMER_T3IN_MASK (0x3F)
#define GPIO_PAR_TIMER_T3IN_T3IN (0xC0)
#define GPIO_PAR_TIMER_T3IN_EXTA3 (0xC0)
#define GPIO_PAR_TIMER_T3IN_T3OUT (0x80)
#define GPIO_PAR_TIMER_T3IN_USB0_VBUSEN (0x40)
#define GPIO_PAR_TIMER_T3IN_ULIPI_DIR (0x40)
#define GPIO_PAR_TIMER_T3IN_GPIO (0x00)
#define GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4)
#define GPIO_PAR_TIMER_T2IN_MASK (0xCF)
#define GPIO_PAR_TIMER_T2IN_T2IN (0x30)
#define GPIO_PAR_TIMER_T2IN_EXTA2 (0x30)
#define GPIO_PAR_TIMER_T2IN_T2OUT (0x20)
#define GPIO_PAR_TIMER_T2IN_SDHC_DAT2 (0x10)
#define GPIO_PAR_TIMER_T2IN_GPIO (0x00)
#define GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2)
#define GPIO_PAR_TIMER_T1IN_MASK (0xF3)
#define GPIO_PAR_TIMER_T1IN_T1IN (0x0C)
#define GPIO_PAR_TIMER_T1IN_EXTA1 (0x0C)
#define GPIO_PAR_TIMER_T1IN_T1OUT (0x08)
#define GPIO_PAR_TIMER_T1IN_SDHC_DAT1 (0x04)
#define GPIO_PAR_TIMER_T1IN_GPIO (0x00)
#define GPIO_PAR_TIMER_T0IN(x) ((x)&0x03)
#define GPIO_PAR_TIMER_T0IN_MASK (0xFC)
#define GPIO_PAR_TIMER_T0IN_T0IN (0x03)
#define GPIO_PAR_TIMER_T0IN_EXTA0 (0x03)
#define GPIO_PAR_TIMER_T0IN_T0OUT (0x02)
#define GPIO_PAR_TIMER_T0IN_USBO_VBUSOC (0x01)
#define GPIO_PAR_TIMER_T0IN_ULPI_NXT (0x01)
#define GPIO_PAR_TIMER_T0IN_GPIO (0x00)
#define GPIO_PAR_UART2_U2CTS(x) (((x)&0x03)<<6)
#define GPIO_PAR_UART2_U2CTS_MASK (0x3F)
#define GPIO_PAR_UART2_U2CTS_U2CTS (0xC0)
#define GPIO_PAR_UART2_U2CTS_U6TXD (0x80)
#define GPIO_PAR_UART2_U2CTS_SSI1_BCLK (0x40)
#define GPIO_PAR_UART2_U2CTS_GPIO (0x00)
#define GPIO_PAR_UART2_U2RTS(x) (((x)&0x03)<<4)
#define GPIO_PAR_UART2_U2RTS_MASK (0xCF)
#define GPIO_PAR_UART2_U2RTS_U2RTS (0x30)
#define GPIO_PAR_UART2_U2RTS_U6RXD (0x20)
#define GPIO_PAR_UART2_U2RTS_SSI1_FS (0x10)
#define GPIO_PAR_UART2_U2RTS_GPIO (0x00)
#define GPIO_PAR_UART2_U2RXD(x) (((x)&0x03)<<2)
#define GPIO_PAR_UART2_U2RXD_MASK (0xF3)
#define GPIO_PAR_UART2_U2RXD_U2RXD (0x0C)
#define GPIO_PAR_UART2_U2RXD_PWM_A3 (0x08)
#define GPIO_PAR_UART2_U2RXD_SSI1_RXD (0x04)
#define GPIO_PAR_UART2_U2RXD_GPIO (0x00)
#define GPIO_PAR_UART2_U2TXD(x) ((x)&0x03)
#define GPIO_PAR_UART2_U2TXD_MASK (0xFC)
#define GPIO_PAR_UART2_U2TXD_U2TXD (0x03)
#define GPIO_PAR_UART2_U2TXD_PWM_B3 (0x02)
#define GPIO_PAR_UART2_U2TXD_SSI1_TXD (0x01)
#define GPIO_PAR_UART2_U2TXD_GPIO (0x00)
#define GPIO_PAR_UART1_U1CTS(x) (((x)&0x03)<<6)
#define GPIO_PAR_UART1_U1CTS_MASK (0x3F)
#define GPIO_PAR_UART1_U1CTS_U1CTS (0xC0)
#define GPIO_PAR_UART1_U1CTS_U5TXD (0x80)
#define GPIO_PAR_UART1_U1CTS_DSPI3_SCK (0x40)
#define GPIO_PAR_UART1_U1CTS_GPIO (0x00)
#define GPIO_PAR_UART1_U1RTS(x) (((x)&0x03)<<4)
#define GPIO_PAR_UART1_U1RTS_MASK (0xCF)
#define GPIO_PAR_UART1_U1RTS_U1RTS (0x30)
#define GPIO_PAR_UART1_U1RTS_U5RXD (0x20)
#define GPIO_PAR_UART1_U1RTS_DSPI3_PCS0 (0x10)
#define GPIO_PAR_UART1_U1RTS_GPIO (0x00)
#define GPIO_PAR_UART1_U1RXD(x) (((x)&0x03)<<2)
#define GPIO_PAR_UART1_U1RXD_MASK (0xF3)
#define GPIO_PAR_UART1_U1RXD_U1RXD (0x0C)
#define GPIO_PAR_UART1_U1RXD_I2C5SDA (0x08)
#define GPIO_PAR_UART1_U1RXD_DSPI3_SIN (0x04)
#define GPIO_PAR_UART1_U1RXD_GPIO (0x00)
#define GPIO_PAR_UART1_U1TXD(x) ((x)&0x03)
#define GPIO_PAR_UART1_U1TXD_MASK (0xFC)
#define GPIO_PAR_UART1_U1TXD_U1TXD (0x03)
#define GPIO_PAR_UART1_U1TXD_I2C5SCL (0x02)
#define GPIO_PAR_UART1_U1TXD_DSPI3_SOUT (0x01)
#define GPIO_PAR_UART1_U1TXD_GPIO (0x00)
#define GPIO_PAR_UART0_U0CTS(x) (((x)&0x03)<<6)
#define GPIO_PAR_UART0_U0CTS_MASK (0x3F)
#define GPIO_PAR_UART0_U0CTS_U0CTS (0xC0)
#define GPIO_PAR_UART0_U0CTS_U4TXD (0x80)
#define GPIO_PAR_UART0_U0CTS_DSPI2_SCK (0x40)
#define GPIO_PAR_UART0_U0CTS_GPIO (0x00)
#define GPIO_PAR_UART0_U0RTS(x) (((x)&0x03)<<4)
#define GPIO_PAR_UART0_U0RTS_MASK (0xCF)
#define GPIO_PAR_UART0_U0RTS_U0RTS (0x30)
#define GPIO_PAR_UART0_U0RTS_U4RXD (0x20)
#define GPIO_PAR_UART0_U0RTS_DSPI2_PCS0 (0x10)
#define GPIO_PAR_UART0_U0RTS_GPIO (0x00)
#define GPIO_PAR_UART0_U0RXD(x) (((x)&0x03)<<2)
#define GPIO_PAR_UART0_U0RXD_MASK (0xF3)
#define GPIO_PAR_UART0_U0RXD_U0RXD (0x0C)
#define GPIO_PAR_UART0_U0RXD_I2C4SDA (0x08)
#define GPIO_PAR_UART0_U0RXD_DSPI2_SIN (0x04)
#define GPIO_PAR_UART0_U0RXD_GPIO (0x00)
#define GPIO_PAR_UART0_U0TXD(x) ((x)&0x03)
#define GPIO_PAR_UART0_U0TXD_MASK (0xFC)
#define GPIO_PAR_UART0_U0TXD_U0TXD (0x03)
#define GPIO_PAR_UART0_U0TXD_I2C4SCL (0x02)
#define GPIO_PAR_UART0_U0TXD_DSPI2_SOUT (0x01)
#define GPIO_PAR_UART0_U0TXD_GPIO (0x00)
#define GPIO_PAR_SDHCH_DAT3(x) (((x)&0x03)<<6)
#define GPIO_PAR_SDHCH_DAT3_MASK (0x3F)
#define GPIO_PAR_SDHCH_DAT3_DAT3 (0xC0)
#define GPIO_PAR_SDHCH_DAT3_PWM_A1 (0x80)
#define GPIO_PAR_SDHCH_DAT3_DSPI1_PCS0 (0x40)
#define GPIO_PAR_SDHCH_DAT3_GPIO (0x00)
#define GPIO_PAR_SDHCH_DAT2(x) (((x)&0x03)<<4)
#define GPIO_PAR_SDHCH_DAT2_MASK (0xCF)
#define GPIO_PAR_SDHCH_DAT2_DAT2 (0x30)
#define GPIO_PAR_SDHCH_DAT2_PWM_B1 (0x20)
#define GPIO_PAR_SDHCH_DAT2_DSPI1_PCS2 (0x10)
#define GPIO_PAR_SDHCH_DAT2_GPIO (0x00)
#define GPIO_PAR_SDHCH_DAT1(x) (((x)&0x03)<<2)
#define GPIO_PAR_SDHCH_DAT1_MASK (0xF3)
#define GPIO_PAR_SDHCH_DAT1_DAT1 (0x0C)
#define GPIO_PAR_SDHCH_DAT1_PWM_A2 (0x08)
#define GPIO_PAR_SDHCH_DAT1_DSPI1_PCS1 (0x04)
#define GPIO_PAR_SDHCH_DAT1_GPIO (0x00)
#define GPIO_PAR_SDHCH_DAT0(x) ((x)&0x03)
#define GPIO_PAR_SDHCH_DAT0_MASK (0xFC)
#define GPIO_PAR_SDHCH_DAT0_DAT0 (0x03)
#define GPIO_PAR_SDHCH_DAT0_PWM_B2 (0x02)
#define GPIO_PAR_SDHCH_DAT0_DSPI1_SOUT (0x01)
#define GPIO_PAR_SDHCH_DAT0_GPIO (0x00)
#define GPIO_PAR_SDHCL_CMD(x) (((x)&0x03)<<2)
#define GPIO_PAR_SDHCL_CMD_MASK (0xF3)
#define GPIO_PAR_SDHCL_CMD_CMD (0x0C)
#define GPIO_PAR_SDHCL_CMD_PWM_A0 (0x08)
#define GPIO_PAR_SDHCL_CMD_DSPI1_SIN (0x04)
#define GPIO_PAR_SDHCL_CMD_GPIO (0x00)
#define GPIO_PAR_SDHCL_CLK(x) ((x)&0x03)
#define GPIO_PAR_SDHCL_CLK_MASK (0xFC)
#define GPIO_PAR_SDHCL_CLK_CLK (0x03)
#define GPIO_PAR_SDHCL_CLK_PWM_B0 (0x02)
#define GPIO_PAR_SDHCL_CLK_DSPI1_SCK (0x01)
#define GPIO_PAR_SDHCL_CLK_GPIO (0x00)
#define GPIO_PAR_SIMP0H_DAT(x) (((x)&0x03)<<6)
#define GPIO_PAR_SIMP0H_DAT_MASK (0x3F)
#define GPIO_PAR_SIMP0H_DAT_DAT (0xC0)
#define GPIO_PAR_SIMP0H_DAT_PWM_FAULT2 (0x80)
#define GPIO_PAR_SIMP0H_DAT_SDHC_DAT7 (0x40)
#define GPIO_PAR_SIMP0H_DAT_GPIO (0x00)
#define GPIO_PAR_SIMP0H_VEN(x) (((x)&0x03)<<4)
#define GPIO_PAR_SIMP0H_VEN_MASK (0xCF)
#define GPIO_PAR_SIMP0H_VEN_VEN (0x30)
#define GPIO_PAR_SIMP0H_VEN_PWM_FAULT0 (0x20)
#define GPIO_PAR_SIMP0H_VEN_GPIO (0x00)
#define GPIO_PAR_SIMP0H_RST(x) (((x)&0x03)<<2)
#define GPIO_PAR_SIMP0H_RST_MASK (0xF3)
#define GPIO_PAR_SIMP0H_RST_RST (0x0C)
#define GPIO_PAR_SIMP0H_RST_PWM_FORCE (0x08)
#define GPIO_PAR_SIMP0H_RST_SDHC_DAT6 (0x04)
#define GPIO_PAR_SIMP0H_RST_GPIO (0x00)
#define GPIO_PAR_SIMP0H_PD(x) ((x)&0x03)
#define GPIO_PAR_SIMP0H_PD_MASK (0xFC)
#define GPIO_PAR_SIMP0H_PD_PD (0x03)
#define GPIO_PAR_SIMP0H_PD_PWM_SYNC (0x02)
#define GPIO_PAR_SIMP0H_PD_SDHC_DAT5 (0x01)
#define GPIO_PAR_SIMP0H_PD_GPIO (0x00)
#define GPIO_PAR_SIMP0L_CLK(x) ((x)&0x03)
#define GPIO_PAR_SIMP0L_CLK_MASK (0xFC)
#define GPIO_PAR_SIMP0L_CLK_CLK (0x03)
#define GPIO_PAR_SIMP0L_CLK_PWM_FAULT1 (0x02)
#define GPIO_PAR_SIMP0L_CLK_SDHC_DAT4 (0x01)
#define GPIO_PAR_SIMP0L_CLK_GPIO (0x00)
#define GPIO_PAR_SSI0H_RXD(x) (((x)&0x03)<<6)
#define GPIO_PAR_SSI0H_RXD_MASK (0x3F)
#define GPIO_PAR_SSI0H_RXD_RXD (0xC0)
#define GPIO_PAR_SSI0H_RXD_I2C2SDA (0x80)
#define GPIO_PAR_SSI0H_RXD_SIM1_VEN (0x40)
#define GPIO_PAR_SSI0H_RXD_GPIO (0x00)
#define GPIO_PAR_SSI0H_TXD(x) (((x)&0x03)<<4)
#define GPIO_PAR_SSI0H_TXD_MASK (0xCF)
#define GPIO_PAR_SSI0H_TXD_TXD (0x30)
#define GPIO_PAR_SSI0H_TXD_I2C2SCL (0x20)
#define GPIO_PAR_SSI0H_TXD_SIM1_DAT (0x10)
#define GPIO_PAR_SSI0H_TXD_GPIO (0x00)
#define GPIO_PAR_SSI0H_FS(x) (((x)&0x03)<<2)
#define GPIO_PAR_SSI0H_FS_MASK (0xF3)
#define GPIO_PAR_SSI0H_FS_FS (0x0C)
#define GPIO_PAR_SSI0H_FS_U7TXD (0x08)
#define GPIO_PAR_SSI0H_FS_SIM1_RST (0x04)
#define GPIO_PAR_SSI0H_FS_GPIO (0x00)
#define GPIO_PAR_SSI0H_MCLK(x) ((x)&0x03)
#define GPIO_PAR_SSI0H_MCLK_MASK (0xFC)
#define GPIO_PAR_SSI0H_MCLK_MCLK (0x03)
#define GPIO_PAR_SSI0H_MCLK_SSI_CLKIN (0x02)
#define GPIO_PAR_SSI0H_MCLK_SIM1_CLK (0x01)
#define GPIO_PAR_SSI0H_MCLK_GPIO (0x00)
#define GPIO_PAR_SSI0L_BCLK(x) ((x)&0x03)
#define GPIO_PAR_SSI0L_BCLK_MASK (0xFC)
#define GPIO_PAR_SSI0L_BCLK_BCLK (0x03)
#define GPIO_PAR_SSI0L_BCLK_U7RXD (0x02)
#define GPIO_PAR_SSI0L_BCLK_SIM1_PD (0x01)
#define GPIO_PAR_SSI0L_BCLK_GPIO (0x00)
#define GPIO_PAR_DEBUGH1_DAT3 (0x40)
#define GPIO_PAR_DEBUGH1_DAT2 (0x10)
#define GPIO_PAR_DEBUGH1_DAT1 (0x04)
#define GPIO_PAR_DEBUGH1_DAT0 (0x01)
#define GPIO_PAR_DEBUGH0_PST3 (0x40)
#define GPIO_PAR_DEBUGH0_PST2 (0x10)
#define GPIO_PAR_DEBUGH0_PST1 (0x04)
#define GPIO_PAR_DEBUGH0_PST0 (0x01)
#define GPIO_PODR_G4_VAL (0x01 << 4)
#define GPIO_PODR_G4_MASK (0xff & ~GPIO_PODR_G4_VAL)
#define GPIO_PDDR_G4_OUTPUT (0x01 << 4)
#define GPIO_PDDR_G4_MASK (0xff & ~GPIO_PDDR_G4_OUTPUT)
#define GPIO_PAR_DEBUGL_ALLPST (0x01)
#define GPIO_PAR_FEC_FEC(x) ((x)&0x0F)
#define GPIO_PAR_FEC_FEC_MASK (0xF0)
#define GPIO_PAR_FEC_FEC_GPIO (0x0D)
#define GPIO_PAR_FEC_FEC_RMII1 (0x0C)
#define GPIO_PAR_FEC_FEC_RMII1FUL (0x0B)
#define GPIO_PAR_FEC_FEC_RMII_ULPI (0x0A)
#define GPIO_PAR_FEC_FEC_RMII0 (0x09)
#define GPIO_PAR_FEC_FEC_RMII0FUL_ULPI (0x08)
#define GPIO_PAR_FEC_FEC_RMII0FUL (0x07)
#define GPIO_PAR_FEC_FEC_RMII0_1FUL (0x06)
#define GPIO_PAR_FEC_FEC_RMII0FUL_1 (0x05) /* 0:Full 1: */
/* Both 0&1: MDC, MDIO, COL & TXER - GPIO */
#define GPIO_PAR_FEC_FEC_RMII0_1 (0x04)
#define GPIO_PAR_FEC_FEC_RMII0FUL_1FUL (0x03)
#define GPIO_PAR_FEC_FEC_MII (0x01) /* MDC & MDIO - GPIO */
#define GPIO_PAR_FEC_FEC_MIIFUL (0x00)
/* TC: Need to edit here.... */
/* Mode Select Control */
#define GPIO_MSCR_SDRAM_MSC(x) ((x)&0x03)
#define GPIO_MSCR_SDRAM_MSC_MASK (0xFC)
/* Slew Rate Control */
#define GPIO_SRCR_FB3_FB3(x) ((x)&0x03)
#define GPIO_SRCR_FB3_FB3_MASK (0xFC)
#define GPIO_SRCR_FB2_FB2(x) ((x)&0x03)
#define GPIO_SRCR_FB2_FB2_MASK (0xFC)
#define GPIO_SRCR_FB1_FB1(x) ((x)&0x03)
#define GPIO_SRCR_FB1_FB1_MASK (0xFC)
#define GPIO_SRCR_FB4_FB5(x) (((x)&0x03)<<2)
#define GPIO_SRCR_FB4_FB5_MASK (0xF3)
#define GPIO_SRCR_FB4_FB4(x) ((x)&0x03)
#define GPIO_SRCR_FB4_FB4_MASK (0xFC)
#define GPIO_SRCR_DSPIOW_OWDAT(x) (((x)&0x03)<<4)
#define GPIO_SRCR_DSPIOW_OWDAT_MASK (0xCF)
#define GPIO_SRCR_DSPIOW_DSPI0(x) ((x)&0x03)
#define GPIO_SRCR_DSPIOW_DSPI0_MASK (0xFC)
#define GPIO_SRCR_CANI2C_CAN1(x) (((x)&0x03)<<2)
#define GPIO_SRCR_CANI2C_CAN1_MASK (0xF3)
#define GPIO_SRCR_CANI2C_I2C0(x) ((x)&0x03)
#define GPIO_SRCR_CANI2C_I2C0_MASK (0xFC)
#define GPIO_SRCR_IRQ0_IRQ0(x) ((x)&0x03)
#define GPIO_SRCR_IRQ0_IRQ0_MASK (0xFC)
#define GPIO_SRCR_TIMER_TMR3(x) (((x)&0x03)<<6)
#define GPIO_SRCR_TIMER_TMR3_MASK (0x3F)
#define GPIO_SRCR_TIMER_TMR2(x) (((x)&0x03)<<4)
#define GPIO_SRCR_TIMER_TMR2_MASK (0xCF)
#define GPIO_SRCR_TIMER_TMR1(x) (((x)&0x03)<<2)
#define GPIO_SRCR_TIMER_TMR1_MASK (0xF3)
#define GPIO_SRCR_TIMER_TMR0(x) ((x)&0x03)
#define GPIO_SRCR_TIMER_TMR0_MASK (0xFC)
#define GPIO_SRCR_UART_U2(x) (((x)&0x03)<<4)
#define GPIO_SRCR_UART_U2_MASK (0xCF)
#define GPIO_SRCR_UART_U1(x) (((x)&0x03)<<2)
#define GPIO_SRCR_UART_U1_MASK (0xF3)
#define GPIO_SRCR_UART_U0(x) ((x)&0x03)
#define GPIO_SRCR_UART_U0_MASK (0xFC)
#define GPIO_SRCR_FEC_RMII0(x) (((x)&0x03)<<2)
#define GPIO_SRCR_FEC_RMII0_MASK (0xF3)
#define GPIO_SRCR_FEC_RMII1(x) ((x)&0x03)
#define GPIO_SRCR_FEC_RMII1_MASK (0xFC)
#define GPIO_SRCR_SDHC_SDHC(x) ((x)&0x03)
#define GPIO_SRCR_SDHC_SDHC_MASK (0xFC)
#define GPIO_SRCR_SIM0_SIMP0(x) ((x)&0x03)
#define GPIO_SRCR_SIM0_SIMP0_MASK (0xFC)
#define GPIO_SRCR_SSI0_SSI0(x) ((x)&0x03)
#define GPIO_SRCR_SSI0_SSI0_MASK (0xFC)
#define GPIO_PCR_URTS_U2 (0x0004)
#define GPIO_PCR_URTS_U1 (0x0002)
#define GPIO_PCR_URTS_U0 (0x0001)
#define GPIO_PCR_UCTS_U2 (0x0004)
#define GPIO_PCR_UCTS_U1 (0x0002)
#define GPIO_PCR_UCTS_U0 (0x0001)
#define GPIO_UTXD_WOM_U9 (0x0200)
#define GPIO_UTXD_WOM_U8 (0x0100)
#define GPIO_UTXD_WOM_U7 (0x0080)
#define GPIO_UTXD_WOM_U6 (0x0040)
#define GPIO_UTXD_WOM_U5 (0x0020)
#define GPIO_UTXD_WOM_U4 (0x0010)
#define GPIO_UTXD_WOM_U3 (0x0008)
#define GPIO_UTXD_WOM_U2 (0x0004)
#define GPIO_UTXD_WOM_U1 (0x0002)
#define GPIO_UTXD_WOM_U0 (0x0001)
#define GPIO_URXD_WOM_U9(x) (((x)&3)<<18)
#define GPIO_URXD_WOM_U9_MASK (0xFFF3FFFF)
#define GPIO_URXD_WOM_U8(x) (((x)&3)<<16)
#define GPIO_URXD_WOM_U8_MASK (0xFFFCFFFF)
#define GPIO_URXD_WOM_U7(x) (((x)&3)<<14)
#define GPIO_URXD_WOM_U7_MASK (0xFFFF3FFF)
#define GPIO_URXD_WOM_U6(x) (((x)&3)<<12)
#define GPIO_URXD_WOM_U6_MASK (0xFFFFCFFF)
#define GPIO_URXD_WOM_U5(x) (((x)&3)<<10)
#define GPIO_URXD_WOM_U5_MASK (0xFFFFF3FF)
#define GPIO_URXD_WOM_U4(x) (((x)&3)<<8)
#define GPIO_URXD_WOM_U4_MASK (0xFFFFFCFF)
#define GPIO_URXD_WOM_U3(x) (((x)&3)<<6)
#define GPIO_URXD_WOM_U3_MASK (0xFFFFFF3F)
#define GPIO_URXD_WOM_U2(x) (((x)&3)<<4)
#define GPIO_URXD_WOM_U2_MASK (0xFFFFFFCF)
#define GPIO_URXD_WOM_U1(x) (((x)&3)<<2)
#define GPIO_URXD_WOM_U1_MASK (0xFFFFFFF3)
#define GPIO_URXD_WOM_U0(x) ((x)&3)
#define GPIO_URXD_WOM_U0_MASK (0xFFFFFFFC)
#define GPIO_HCR1_PG4_0(x) (((x)&0x1F)<<27)
#define GPIO_HCR1_PG4_0_MASK (0x07FFFFFF)
#define GPIO_HCR1_PF7_3(x) (((x)&0x1F)<<22)
#define GPIO_HCR1_PF7_3_MASK (0xF83FFFFF)
#define GPIO_HCR1_PE6_0(x) (((x)&0x7F)<<15)
#define GPIO_HCR1_PE6_0_MASK (0xFFC07FFF)
#define GPIO_HCR1_PD7_3(x) (((x)&0x1F)<<10)
#define GPIO_HCR1_PD7_3_MASK (0xFFFF83FF)
#define GPIO_HCR1_PC7_1(x) (((x)&0x7F)<<3)
#define GPIO_HCR1_PC7_1_MASK (0xFFFFFC07)
#define GPIO_HCR1_PB2_0(x) ((x)&7)
#define GPIO_HCR1_PB2_0_MASK (0xFFFFFFF8)
#define GPIO_HCR0_PK3 (0x00000400)
#define GPIO_HCR0_PK0 (0x00000200)
#define GPIO_HCR0_PD2_0(x) (((x)&7)<<6)
#define GPIO_HCR0_PD2_0_MASK (0xFFFFFE3F)
#define GPIO_HCR0_PE7 (0x00000020)
#define GPIO_HCR0_PH7_3(x) ((x)&0x1F)
#define GPIO_HCR0_PH7_3_MASK(x) (0xFFFFFFE0)
/* SDRAM Controller (SDRAMC) */
/* Phase Locked Loop (PLL) */
#define PLL_CR_LOCIRQ (0x00040000)
#define PLL_CR_LOCRE (0x00020000)
#define PLL_CR_LOCEN (0x00010000)
#define PLL_CR_LOLIRQ (0x00004000)
#define PLL_CR_LOLRE (0x00002000)
#define PLL_CR_LOLEN (0x00001000)
#define PLL_CR_REFDIV(x) (((x)&7)<<8)
#define PLL_CR_REFDIV_MASK (0xFFFFF8FF)
#define PLL_CR_FBKDIV(x) ((x)&0x3F)
#define PLL_CR_FBKDIV_MASK (0xFFFFFFC0)
#define PLL_CR_FBKDIV_BITS (0x3F)
#define PLL_DR_OUTDIV5(x) (((x)&0x1F)<<21)
#define PLL_DR_OUTDIV5_MASK (0xFC1FFFFF)
#define PLL_DR_OUTDIV5_BITS (0x03E00000)
#define PLL_DR_OUTDIV4(x) (((x)&0x1F)<<16)
#define PLL_DR_OUTDIV4_MASK (0xFFE0FFFF)
#define PLL_DR_OUTDIV4_BITS (0x001F0000)
#define PLL_DR_OUTDIV3(x) (((x)&0x1F)<<10)
#define PLL_DR_OUTDIV3_MASK (0xFFFF83FF)
#define PLL_DR_OUTDIV3_BITS (0x00007C00)
#define PLL_DR_OUTDIV2(x) (((x)&0x1F)<<5)
#define PLL_DR_OUTDIV2_MASK (0xFFFFFC1F)
#define PLL_DR_OUTDIV2_BITS (0x000003E0)
#define PLL_DR_OUTDIV1(x) ((x)&0x1F)
#define PLL_DR_OUTDIV1_MASK (0xFFFFFFE0)
#define PLL_DR_OUTDIV1_BITS (0x0000001F)
#define PLL_SR_LOCF (0x00000200)
#define PLL_SR_LOC (0x00000100)
#define PLL_SR_LOLF (0x00000040)
#define PLL_SR_LOCKS (0x00000020)
#define PLL_SR_LOCK (0x00000010)
#define PLL_PSR_LOCK PLL_SR_LOCK /* compatible with 5x */
#define PLL_SR_MODE(x) ((x)&7)
#define PLL_SR_MODE_MASK (0xFFFFFFF8)
#endif /* __MCF5441X__ */

2
arch/m68k/include/asm/u-boot.h
View File

@ -58,7 +58,7 @@ typedef struct bd_info {
unsigned long bi_vcofreq; /* vco Freq in MHz */
unsigned long bi_flbfreq; /* Flexbus Freq in MHz */
#endif
unsigned long bi_baudrate; /* Console Baudrate */
unsigned int bi_baudrate; /* Console Baudrate */
} bd_t;
#endif /* __ASSEMBLY__ */

7
arch/m68k/lib/board.c
View File

@ -29,6 +29,7 @@
#include <command.h>
#include <malloc.h>
#include <stdio_dev.h>
#include <linux/compiler.h>
#include <asm/immap.h>
@ -387,7 +388,7 @@ board_init_f (ulong bootflag)
*/
void board_init_r (gd_t *id, ulong dest_addr)
{
char *s;
char *s __maybe_unused;
bd_t *bd;
#ifndef CONFIG_ENV_IS_NOWHERE
@ -415,8 +416,8 @@ void board_init_r (gd_t *id, ulong dest_addr)
/*
* We have to relocate the command table manually
*/
fixup_cmdtable(&__u_boot_cmd_start,
(ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
ll_entry_count(cmd_tbl_t, cmd));
#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
/* there are some other pointer constants we must deal with */

5
arch/microblaze/cpu/cache.c
View File

@ -61,12 +61,7 @@ void dcache_enable (void) {
void dcache_disable(void) {
#ifdef XILINX_USE_DCACHE
#ifdef XILINX_DCACHE_BYTE_SIZE
flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
#else
#warning please rebuild BSPs and update configuration
flush_cache(0, 32768);
#endif
#endif
MSRCLR(0x80);
}

6
arch/microblaze/cpu/start.S
View File

@ -132,6 +132,12 @@ _start:
rsubi r8, r10, 0x26
sh r6, r0, r8
/* Flush cache before enable cache */
addik r5, r0, 0
addik r6, r0, XILINX_DCACHE_BYTE_SIZE
flush: bralid r15, flush_cache
nop
/* enable instruction and data cache */
mfs r12, rmsr
ori r12, r12, 0xa0

11
arch/microblaze/cpu/u-boot.lds
View File

@ -45,17 +45,16 @@ SECTIONS
.data ALIGN(0x4):
{
__data_start = .;
#ifdef CONFIG_OF_EMBED
dts/libdts.o (.data)
#endif
*(.data)
__data_end = .;
}
.u_boot_cmd ALIGN(0x4):
{
. = .;
__u_boot_cmd_start = .;
*(.u_boot_cmd)
__u_boot_cmd_end = .;
. = ALIGN(4);
.u_boot_list : {
#include <u-boot.lst>
}
.bss ALIGN(0x4):

3
arch/microblaze/include/asm/bitops.h
View File

@ -319,7 +319,8 @@ extern __inline__ int ext2_test_bit(int nr, const volatile void * addr)
#define ext2_find_first_zero_bit(addr, size) \
ext2_find_next_zero_bit((addr), (size), 0)
extern __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset)
static inline unsigned long ext2_find_next_zero_bit(void *addr,
unsigned long size, unsigned long offset)
{
unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
unsigned long result = offset & ~31UL;

23
arch/microblaze/include/asm/byteorder.h
View File

@ -20,29 +20,6 @@
#ifdef __GNUC__
/* This is effectively a dupe of the arch-independent byteswap
code in include/linux/byteorder/swab.h, however we force a cast
of the result up to 32 bits. This in turn forces the compiler
to explicitly clear the high 16 bits, which it wasn't doing otherwise.
I think this is a symptom of a bug in mb-gcc. JW 20040303
*/
static __inline__ __u16 ___arch__swab16 (__u16 half_word)
{
/* 32 bit temp to cast result, forcing clearing of high word */
__u32 temp;
temp = ((half_word & 0x00FFU) << 8) | ((half_word & 0xFF00U) >> 8);
return (__u16) temp;
}
#define __arch__swab16(x) ___arch__swab16(x)
/* Microblaze has no arch-specific endian conversion insns */
#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
# define __BYTEORDER_HAS_U64__
# define __SWAB_64_THRU_32__

2
arch/microblaze/include/asm/global_data.h
View File

@ -35,7 +35,7 @@
typedef struct global_data {
bd_t *bd;
unsigned long flags;
unsigned long baudrate;
unsigned int baudrate;
unsigned long have_console; /* serial_init() was called */
#ifdef CONFIG_PRE_CONSOLE_BUFFER
unsigned long precon_buf_idx; /* Pre-Console buffer index */

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