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ARM: DRA7: DDR: Enable SR in Power Management Control 

If EMIF is idle for certain amount of DDR cycles, EMIF will put the
DDR in self refresh mode to save power if EMIF_PWR_MGMT_CTRL register
is programmed. And also before entering suspend-resume ddr needs to
be put in self-refresh. Linux kernel does not program this register
before entering suspend and relies on u-boot setting.
So configuring it in u-boot.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
utp
Nishanth Menon 2016-03-09 17:39:56 +05:30 committed by Tom Rini
parent d28a86c07a
commit 3eb80d10c7
1 changed files with 3 additions and 3 deletions
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6
arch/arm/include/asm/emif.h
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@ -914,8 +914,8 @@ struct dmm_lisa_map_regs {
/* Maximum delay before Low Power Modes */
#define REG_CS_TIM 0x0
#define REG_SR_TIM 0x0
#define REG_PD_TIM 0x0
#define REG_SR_TIM 0xF
#define REG_PD_TIM 0xF
/* EMIF_PWR_MGMT_CTRL register */
@ -923,7 +923,7 @@ struct dmm_lisa_map_regs {
((REG_CS_TIM << EMIF_REG_CS_TIM_SHIFT) & EMIF_REG_CS_TIM_MASK)|\
((REG_SR_TIM << EMIF_REG_SR_TIM_SHIFT) & EMIF_REG_SR_TIM_MASK)|\
((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\
((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)\
((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)\
& EMIF_REG_LP_MODE_MASK) |\
((DPD_DISABLE << EMIF_REG_DPD_EN_SHIFT)\
& EMIF_REG_DPD_EN_MASK))\