ARM: uniphier: add a field to specify DDR3+
Add a field to distinguish DDR3+ from (standard) DDR3. It also allows to delete CONFIG_DDR_STANDARD (this is not a software configuration, but a board attribute). Default DDR3 spec for each SoC: PH1-LD4, PH1-sLD8: DDR3+ Others: DDR3 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>utp
Masahiro Yamada
parent
3c963d4899
commit
4021b4381d
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@ -38,6 +38,7 @@ static const struct uniphier_board_data ph1_sld3_data = {
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static const struct uniphier_board_data ph1_ld4_data = {
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.dram_freq = 1600,
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.dram_nr_ch = 2,
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.dram_ddr3plus = true,
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.dram_ch[0] = {
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.base = 0x80000000,
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.size = 0x10000000,
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@ -89,6 +90,7 @@ static const struct uniphier_board_data ph1_pro4_2g_data = {
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static const struct uniphier_board_data ph1_sld8_data = {
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.dram_freq = 1333,
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.dram_nr_ch = 2,
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.dram_ddr3plus = true,
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.dram_ch[0] = {
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.base = 0x80000000,
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.size = 0x10000000,
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@ -9,7 +9,8 @@
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#include "ddrphy-regs.h"
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int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
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int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size,
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bool ddr3plus)
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{
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u32 tmp;
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@ -61,7 +62,7 @@ int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
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else
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writel(0x00000298, &phy->mr2);
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writel(0x00000800, &phy->mr3);
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writel(ddr3plus ? 0x00000800 : 0x00000000, &phy->mr3);
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while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
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;
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@ -9,7 +9,8 @@
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#include "ddrphy-regs.h"
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int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
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int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size,
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bool ddr3plus)
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{
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u32 tmp;
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@ -55,7 +56,7 @@ int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
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else
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writel(0x00000298, &phy->mr2);
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writel(0x00000000, &phy->mr3);
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writel(ddr3plus ? 0x00000800 : 0x00000000, &phy->mr3);
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while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
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;
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@ -10,7 +10,8 @@
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#include "ddrphy-regs.h"
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int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
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int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size,
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bool ddr3plus)
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{
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u32 tmp;
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@ -62,11 +63,7 @@ int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
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else
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writel(0x00000298, &phy->mr2);
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#ifdef CONFIG_DDR_STANDARD
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writel(0x00000000, &phy->mr3);
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#else
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writel(0x00000800, &phy->mr3);
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#endif
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writel(ddr3plus ? 0x00000800 : 0x00000000, &phy->mr3);
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while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
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;
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@ -11,6 +11,7 @@
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#include <linux/bitops.h>
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#include <linux/compiler.h>
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#include <linux/types.h>
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#ifndef __ASSEMBLY__
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@ -169,9 +170,12 @@ struct ddrphy {
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#define DDRPHY_BASE(ch, phy) (0x5bc01000 + 0x200000 * (ch) + 0x1000 * (phy))
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#ifndef __ASSEMBLY__
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int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
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int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
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int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
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int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size,
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bool ddr3plus);
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int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size,
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bool ddr3plus);
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int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size,
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bool ddr3plus);
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void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank);
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int ddrphy_training(struct ddrphy __iomem *phy);
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#endif
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@ -96,7 +96,7 @@ static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
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writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
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}
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static int umc_init_sub(int freq, int size_ch0, int size_ch1)
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static int umc_init_sub(int freq, int size_ch0, int size_ch1, bool ddr3plus)
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{
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void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
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void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
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@ -113,14 +113,14 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1)
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writel(0x00000101, dramcont0 + UMC_DIOCTLA);
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ph1_ld4_ddrphy_init(phy0_0, freq, size_ch0);
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ph1_ld4_ddrphy_init(phy0_0, freq, size_ch0, ddr3plus);
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ddrphy_prepare_training(phy0_0, 0);
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ddrphy_training(phy0_0);
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writel(0x00000101, dramcont1 + UMC_DIOCTLA);
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ph1_ld4_ddrphy_init(phy1_0, freq, size_ch1);
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ph1_ld4_ddrphy_init(phy1_0, freq, size_ch1, ddr3plus);
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ddrphy_prepare_training(phy1_0, 1);
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ddrphy_training(phy1_0);
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@ -141,7 +141,8 @@ int ph1_ld4_umc_init(const struct uniphier_board_data *bd)
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bd->dram_ch[0].width == 16 && bd->dram_ch[1].width == 16) {
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return umc_init_sub(bd->dram_freq,
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bd->dram_ch[0].size / SZ_128M,
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bd->dram_ch[1].size / SZ_128M);
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bd->dram_ch[1].size / SZ_128M,
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bd->dram_ddr3plus);
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} else {
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pr_err("Unsupported DDR configuration\n");
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return -EINVAL;
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@ -138,28 +138,32 @@ int ph1_pro4_umc_init(const struct uniphier_board_data *bd)
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writel(0x00000101, dramcont0 + UMC_DIOCTLA);
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ph1_pro4_ddrphy_init(phy0_0, bd->dram_freq, bd->dram_ch[0].size);
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ph1_pro4_ddrphy_init(phy0_0, bd->dram_freq, bd->dram_ch[0].size,
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bd->dram_ddr3plus);
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ddrphy_prepare_training(phy0_0, 0);
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ddrphy_training(phy0_0);
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writel(0x00000103, dramcont0 + UMC_DIOCTLA);
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ph1_pro4_ddrphy_init(phy0_1, bd->dram_freq, bd->dram_ch[0].size);
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ph1_pro4_ddrphy_init(phy0_1, bd->dram_freq, bd->dram_ch[0].size,
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bd->dram_ddr3plus);
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ddrphy_prepare_training(phy0_1, 1);
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ddrphy_training(phy0_1);
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writel(0x00000101, dramcont1 + UMC_DIOCTLA);
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ph1_pro4_ddrphy_init(phy1_0, bd->dram_freq, bd->dram_ch[1].size);
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ph1_pro4_ddrphy_init(phy1_0, bd->dram_freq, bd->dram_ch[1].size,
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bd->dram_ddr3plus);
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ddrphy_prepare_training(phy1_0, 0);
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ddrphy_training(phy1_0);
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writel(0x00000103, dramcont1 + UMC_DIOCTLA);
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ph1_pro4_ddrphy_init(phy1_1, bd->dram_freq, bd->dram_ch[1].size);
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ph1_pro4_ddrphy_init(phy1_1, bd->dram_freq, bd->dram_ch[1].size,
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bd->dram_ddr3plus);
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ddrphy_prepare_training(phy1_1, 1);
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ddrphy_training(phy1_1);
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@ -48,15 +48,10 @@ static void umc_start_ssif(void __iomem *ssif_base)
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}
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static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
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int size, int freq)
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int size, int freq, bool ddr3plus)
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{
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#ifdef CONFIG_DDR_STANDARD
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writel(0x55990b11, dramcont + UMC_CMDCTLA);
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writel(0x16958944, dramcont + UMC_CMDCTLB);
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#else
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writel(0x45990b11, dramcont + UMC_CMDCTLA);
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writel(0x16958924, dramcont + UMC_CMDCTLB);
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#endif
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writel(ddr3plus ? 0x45990b11 : 0x55990b11, dramcont + UMC_CMDCTLA);
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writel(ddr3plus ? 0x16958924 : 0x16958944, dramcont + UMC_CMDCTLB);
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if (size == 1)
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writel(0x00240512, dramcont + UMC_SPCCTLA);
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@ -85,7 +80,7 @@ static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
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writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
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}
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static int umc_init_sub(int freq, int size_ch0, int size_ch1)
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static int umc_init_sub(int freq, int size_ch0, int size_ch1, bool ddr3plus)
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{
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void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
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void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
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@ -102,20 +97,20 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1)
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writel(0x00000101, dramcont0 + UMC_DIOCTLA);
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ph1_sld8_ddrphy_init(phy0_0, freq, size_ch0);
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ph1_sld8_ddrphy_init(phy0_0, freq, size_ch0, ddr3plus);
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ddrphy_prepare_training(phy0_0, 0);
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ddrphy_training(phy0_0);
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writel(0x00000101, dramcont1 + UMC_DIOCTLA);
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ph1_sld8_ddrphy_init(phy1_0, freq, size_ch1);
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ph1_sld8_ddrphy_init(phy1_0, freq, size_ch1, ddr3plus);
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ddrphy_prepare_training(phy1_0, 1);
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ddrphy_training(phy1_0);
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umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
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umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
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umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq, ddr3plus);
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umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq, ddr3plus);
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umc_start_ssif(ssif_base);
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@ -130,7 +125,8 @@ int ph1_sld8_umc_init(const struct uniphier_board_data *bd)
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bd->dram_ch[0].width == 16 && bd->dram_ch[1].width == 16) {
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return umc_init_sub(bd->dram_freq,
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bd->dram_ch[0].size / SZ_128M,
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bd->dram_ch[1].size / SZ_128M);
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bd->dram_ch[1].size / SZ_128M,
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bd->dram_ddr3plus);
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} else {
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pr_err("Unsupported DDR configuration\n");
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return -EINVAL;
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@ -7,6 +7,8 @@
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#ifndef __MACH_INIT_H
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#define __MACH_INIT_H
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#include <linux/types.h>
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#define UNIPHIER_MAX_NR_DRAM_CH 3
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struct uniphier_dram_ch {
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@ -18,6 +20,7 @@ struct uniphier_dram_ch {
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struct uniphier_board_data {
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unsigned int dram_freq;
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unsigned int dram_nr_ch;
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bool dram_ddr3plus;
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struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH];
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};
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