Merge git://git.denx.de/u-boot-uniphier
Tom Rini
commit
413978d118
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@ -129,6 +129,15 @@
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status = "disabled";
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};
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i2c4: i2c@58600000 {
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compatible = "panasonic,uniphier-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x58600000 0x40>;
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clock-frequency = <400000>;
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status = "okay";
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};
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system-bus-controller-misc@59800000 {
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compatible = "socionext,uniphier-system-bus-controller-misc",
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"syscon";
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@ -8,7 +8,7 @@
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&i2c0 {
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eeprom {
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compatible = "i2c-eeprom";
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compatible = "microchip,24lc128", "i2c-eeprom";
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reg = <0x50>;
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u-boot,i2c-offset-len = <2>;
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};
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@ -10,13 +10,17 @@ choice
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prompt "UniPhier SoC select"
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default MACH_PH1_PRO4
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config MACH_PH1_PRO4
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bool "PH1-Pro4"
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config MACH_PH1_SLD3
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bool "PH1-sLD3"
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select UNIPHIER_SMP
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config MACH_PH1_LD4
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bool "PH1-LD4"
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config MACH_PH1_PRO4
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bool "PH1-Pro4"
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select UNIPHIER_SMP
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config MACH_PH1_SLD8
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bool "PH1-sLD8"
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@ -64,11 +68,11 @@ choice
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config DDR_FREQ_1600
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bool "DDR3 1600"
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depends on MACH_PH1_PRO4 || MACH_PH1_LD4
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depends on MACH_PH1_SLD3 || MACH_PH1_LD4 || MACH_PH1_PRO4
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config DDR_FREQ_1333
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bool "DDR3 1333"
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depends on MACH_PH1_LD4 || MACH_PH1_SLD8
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depends on MACH_PH1_SLD3 || MACH_PH1_LD4 || MACH_PH1_SLD8
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endchoice
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@ -32,6 +32,7 @@ obj-y += timer.o
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obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += support_card.o
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obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += support_card.o
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obj-$(CONFIG_MACH_PH1_LD4) += ph1-ld4/
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obj-$(CONFIG_MACH_PH1_PRO4) += ph1-pro4/
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obj-$(CONFIG_MACH_PH1_SLD8) += ph1-sld8/
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obj-$(CONFIG_MACH_PH1_SLD3) += ph1-sld3/
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obj-$(CONFIG_MACH_PH1_LD4) += ph1-ld4/
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obj-$(CONFIG_MACH_PH1_PRO4) += ph1-pro4/
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obj-$(CONFIG_MACH_PH1_SLD8) += ph1-sld8/
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@ -1,7 +1,7 @@
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/*
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* UniPhier SC (System Control) block registers
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*
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* Copyright (C) 2011-2015 Panasonic Corporation
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* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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@ -9,7 +9,11 @@
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#ifndef ARCH_SC_REGS_H
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#define ARCH_SC_REGS_H
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#if defined(CONFIG_MACH_PH1_SLD3)
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#define SC_BASE_ADDR 0xf1840000
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#else
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#define SC_BASE_ADDR 0x61840000
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#endif
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#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1200)
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#define SC_DPLLCTRL_SSC_EN (0x1 << 31)
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@ -55,11 +55,12 @@
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#if defined(CONFIG_MACH_PH1_PRO4)
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# define SG_PINCTRL(n) (SG_PINCTRL_BASE + (n) * 8)
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#elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
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#elif defined(CONFIG_MACH_PH1_SLD3) || defined(CONFIG_MACH_PH1_LD4) || \
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defined(CONFIG_MACH_PH1_SLD8)
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# define SG_PINCTRL(n) (SG_PINCTRL_BASE + (n) * 4)
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#endif
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#if defined(CONFIG_MACH_PH1_PRO4)
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#if defined(CONFIG_MACH_PH1_SLD3) || defined(CONFIG_MACH_PH1_PRO4)
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#define SG_PINSELBITS 4
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#elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
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#define SG_PINSELBITS 8
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@ -0,0 +1,16 @@
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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ifdef CONFIG_SPL_BUILD
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obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
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obj-y += bcu_init.o memconf.o sg_init.o pll_init.o early_clkrst_init.o \
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early_pinctrl.o pll_spectrum.o umc_init.o
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obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
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obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
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obj-$(CONFIG_SPL_DM) += platdevice.o
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else
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obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
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endif
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obj-y += boot-mode.o
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@ -0,0 +1,36 @@
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/*
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* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/io.h>
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#include <mach/bcu-regs.h>
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#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
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void bcu_init(void)
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{
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int shift;
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writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */
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writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */
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writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */
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/*
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* 0xe0000000-0xefffffff: Ex-bus
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* 0xf0000000-0xfbffffff: ASM bus
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* 0xfc000000-0xffffffff: OCM bus
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*/
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writel(0x24440000, BCSCR5);
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/* Specify DDR channel */
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shift = (CONFIG_SDRAM1_BASE - CONFIG_SDRAM0_BASE) / 0x04000000 * 4;
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writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
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shift -= 32;
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writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */
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shift -= 32;
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writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
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}
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@ -0,0 +1,97 @@
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/*
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* Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <spl.h>
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#include <linux/io.h>
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#include <mach/boot-device.h>
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#include <mach/sg-regs.h>
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#include <mach/sbc-regs.h>
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struct boot_device_info boot_device_table[] = {
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NONE, "External Master"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_MMC1, "eMMC (3.3V, Boot Oparation)"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_MMC1, "eMMC (1.8V, Boot Oparation)"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_MMC1, "eMMC (3.3V, Normal)"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_MMC1, "eMMC (1.8V, Normal)"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{BOOT_DEVICE_NONE, "Reserved"},
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{ /* sentinel */ }
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};
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int get_boot_mode_sel(void)
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{
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return readl(SG_PINMON0) & 0x3f;
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}
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u32 spl_boot_device(void)
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{
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int boot_mode;
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if (boot_is_swapped())
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return BOOT_DEVICE_NOR;
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boot_mode = get_boot_mode_sel();
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return boot_device_table[boot_mode].type;
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}
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@ -0,0 +1 @@
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#include "../ph1-pro4/clkrst_init.c"
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@ -0,0 +1 @@
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#include "../ph1-pro4/early_clkrst_init.c"
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@ -0,0 +1,23 @@
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/*
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* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <mach/sg-regs.h>
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void early_pin_init(void)
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{
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/* Comment format: PAD Name -> Function Name */
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#ifdef CONFIG_UNIPHIER_SERIAL
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sg_set_pinsel(63, 0); /* RXD0 */
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sg_set_pinsel(64, 1); /* TXD0 */
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sg_set_pinsel(65, 0); /* RXD1 */
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sg_set_pinsel(66, 1); /* TXD1 */
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sg_set_pinsel(96, 2); /* RXD2 */
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sg_set_pinsel(102, 2); /* TXD2 */
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#endif
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}
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@ -0,0 +1,31 @@
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/*
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* On-chip UART initializaion for low-level debugging
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*
|
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* Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <linux/linkage.h>
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#include <mach/bcu-regs.h>
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#include <mach/sc-regs.h>
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#include <mach/sg-regs.h>
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#include <mach/debug-uart.S>
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ENTRY(setup_lowlevel_debug)
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ldr r0, =BCSCR5
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ldr r1, =0x24440000
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str r1, [r0]
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ldr r0, =SC_CLKCTRL
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ldr r1, [r0]
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orr r1, r1, #SC_CLKCTRL_CEN_PERI
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str r1, [r0]
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init_debug_uart r0, r1, r2
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|
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set_pinsel 63, 0, r0, r1
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set_pinsel 64, 1, r0, r1
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mov pc, lr
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ENDPROC(setup_lowlevel_debug)
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|
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@ -0,0 +1,52 @@
|
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/*
|
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* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
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#include <common.h>
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#include <linux/types.h>
|
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#include <linux/sizes.h>
|
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#include <mach/sg-regs.h>
|
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|
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static inline u32 sg_memconf_val_ch2(unsigned long size, int num)
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{
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int size_mb = size / num;
|
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u32 ret;
|
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|
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switch (size_mb) {
|
||||
case SZ_64M:
|
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ret = SG_MEMCONF_CH2_SZ_64M;
|
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break;
|
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case SZ_128M:
|
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ret = SG_MEMCONF_CH2_SZ_128M;
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break;
|
||||
case SZ_256M:
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||||
ret = SG_MEMCONF_CH2_SZ_256M;
|
||||
break;
|
||||
case SZ_512M:
|
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ret = SG_MEMCONF_CH2_SZ_512M;
|
||||
break;
|
||||
default:
|
||||
BUG();
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||||
break;
|
||||
}
|
||||
|
||||
switch (num) {
|
||||
case 1:
|
||||
ret |= SG_MEMCONF_CH2_NUM_1;
|
||||
break;
|
||||
case 2:
|
||||
ret |= SG_MEMCONF_CH2_NUM_2;
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
break;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
u32 memconf_additional_val(void)
|
||||
{
|
||||
return sg_memconf_val_ch2(CONFIG_SDRAM2_SIZE, CONFIG_DDR_NUM_CH2);
|
||||
}
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <mach/sg-regs.h>
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||||
|
||||
void pin_init(void)
|
||||
{
|
||||
#ifdef CONFIG_USB_EHCI_UNIPHIER
|
||||
sg_set_pinsel(13, 0); /* USB0OC */
|
||||
sg_set_pinsel(14, 1); /* USB0VBUS */
|
||||
|
||||
sg_set_pinsel(15, 0); /* USB1OC */
|
||||
sg_set_pinsel(16, 1); /* USB1VBUS */
|
||||
|
||||
sg_set_pinsel(17, 0); /* USB2OC */
|
||||
sg_set_pinsel(18, 1); /* USB2VBUS */
|
||||
|
||||
sg_set_pinsel(19, 0); /* USB3OC */
|
||||
sg_set_pinsel(20, 1); /* USB3VBUS */
|
||||
#endif
|
||||
}
|
||||
|
|
@ -0,0 +1 @@
|
|||
#include "../ph1-ld4/platdevice.c"
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
/*
|
||||
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
void pll_init(void)
|
||||
{
|
||||
/* add pll init code here */
|
||||
}
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
/*
|
||||
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <linux/io.h>
|
||||
#include <mach/sc-regs.h>
|
||||
|
||||
void enable_dpll_ssc(void)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
tmp = readl(SC_DPLLCTRL);
|
||||
tmp |= SC_DPLLCTRL_SSC_EN;
|
||||
writel(tmp, SC_DPLLCTRL);
|
||||
}
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
/*
|
||||
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <linux/io.h>
|
||||
#include <mach/sbc-regs.h>
|
||||
#include <mach/sg-regs.h>
|
||||
|
||||
void sbc_init(void)
|
||||
{
|
||||
/* only address/data multiplex mode is supported */
|
||||
|
||||
/*
|
||||
* Only CS1 is connected to support card.
|
||||
* BKSZ[1:0] should be set to "01".
|
||||
*/
|
||||
writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10);
|
||||
writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11);
|
||||
writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12);
|
||||
|
||||
if (boot_is_swapped()) {
|
||||
/*
|
||||
* Boot Swap On: boot from external NOR/SRAM
|
||||
* 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff.
|
||||
*
|
||||
* 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank
|
||||
* 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals
|
||||
*/
|
||||
writel(0x0000bc01, SBBASE0);
|
||||
} else {
|
||||
/*
|
||||
* Boot Swap Off: boot from mask ROM
|
||||
* 0x00000000-0x01ffffff: mask ROM
|
||||
* 0x02000000-0x03efffff: memory bank (31MB)
|
||||
* 0x03f00000-0x03ffffff: peripherals (1MB)
|
||||
*/
|
||||
writel(0x0000be01, SBBASE0); /* dummy */
|
||||
writel(0x0200be01, SBBASE1);
|
||||
}
|
||||
|
||||
sg_set_pinsel(99, 1); /* GPIO26 -> EA24 */
|
||||
}
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
/*
|
||||
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <linux/io.h>
|
||||
#include <mach/sbc-regs.h>
|
||||
#include <mach/sg-regs.h>
|
||||
|
||||
void sbc_init(void)
|
||||
{
|
||||
/* only address/data multiplex mode is supported */
|
||||
|
||||
/* XECS0 : boot/sub memory (boot swap = off/on) */
|
||||
writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL00);
|
||||
writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL01);
|
||||
writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL02);
|
||||
|
||||
/* XECS1 : sub/boot memory (boot swap = off/on) */
|
||||
writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10);
|
||||
writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11);
|
||||
writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12);
|
||||
|
||||
/* XECS2 : peripherals */
|
||||
writel(SBCTRL0_ADMULTIPLX_PERI_VALUE, SBCTRL20);
|
||||
writel(SBCTRL1_ADMULTIPLX_PERI_VALUE, SBCTRL21);
|
||||
writel(SBCTRL2_ADMULTIPLX_PERI_VALUE, SBCTRL22);
|
||||
|
||||
/* base address regsiters */
|
||||
writel(0x0000bc01, SBBASE0);
|
||||
writel(0x0400bc01, SBBASE1);
|
||||
writel(0x0800bf01, SBBASE2);
|
||||
|
||||
sg_set_pinsel(99, 1); /* GPIO26 -> EA24 */
|
||||
}
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
/*
|
||||
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
void sg_init(void)
|
||||
{
|
||||
}
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
/*
|
||||
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
int umc_init(void)
|
||||
{
|
||||
/* add UMC init code here */
|
||||
printf("Implement memory init code\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -4,8 +4,6 @@ CONFIG_MACH_PH1_LD4=y
|
|||
CONFIG_PFC_MICRO_SUPPORT_CARD=y
|
||||
CONFIG_SYS_TEXT_BASE=0x84000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref"
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
# CONFIG_CMD_ENV_EXISTS is not set
|
||||
|
|
|
|||
|
|
@ -3,8 +3,6 @@ CONFIG_ARCH_UNIPHIER=y
|
|||
CONFIG_PFC_MICRO_SUPPORT_CARD=y
|
||||
CONFIG_SYS_TEXT_BASE=0x84000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref"
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
# CONFIG_CMD_ENV_EXISTS is not set
|
||||
|
|
|
|||
|
|
@ -0,0 +1,28 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_UNIPHIER=y
|
||||
CONFIG_MACH_PH1_SLD3=y
|
||||
CONFIG_PFC_MICRO_SUPPORT_CARD=y
|
||||
CONFIG_SYS_TEXT_BASE=0x84000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld3-ref"
|
||||
CONFIG_HUSH_PARSER=y
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
# CONFIG_CMD_ENV_EXISTS is not set
|
||||
CONFIG_CMD_NAND=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_FPGA is not set
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_TIME=y
|
||||
# CONFIG_CMD_MISC is not set
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_NAND_DENALI=y
|
||||
CONFIG_SYS_NAND_DENALI_64BIT=y
|
||||
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
|
||||
CONFIG_SPL_NAND_DENALI=y
|
||||
CONFIG_UNIPHIER_SERIAL=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
|
|
@ -4,8 +4,6 @@ CONFIG_MACH_PH1_SLD8=y
|
|||
CONFIG_PFC_MICRO_SUPPORT_CARD=y
|
||||
CONFIG_SYS_TEXT_BASE=0x84000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld8-ref"
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
# CONFIG_CMD_ENV_EXISTS is not set
|
||||
|
|
|
|||
|
|
@ -28,14 +28,18 @@ Tested toolchains
|
|||
Compile the source
|
||||
------------------
|
||||
|
||||
PH1-Pro4:
|
||||
$ make ph1_pro4_defconfig
|
||||
PH1-sLD3:
|
||||
$ make ph1_sld3_defconfig
|
||||
$ make CROSS_COMPILE=arm-linux-gnueabi-
|
||||
|
||||
PH1-LD4:
|
||||
$ make ph1_ld4_defconfig
|
||||
$ make CROSS_COMPILE=arm-linux-gnueabi-
|
||||
|
||||
PH1-Pro4:
|
||||
$ make ph1_pro4_defconfig
|
||||
$ make CROSS_COMPILE=arm-linux-gnueabi-
|
||||
|
||||
PH1-sLD8:
|
||||
$ make ph1_sld8_defconfig
|
||||
$ make CROSS_COMPILE=arm-linux-gnueabi-
|
||||
|
|
@ -81,6 +85,48 @@ Supported devices
|
|||
- Support card (SRAM, NOR flash, some peripherals)
|
||||
|
||||
|
||||
Micro Support Card
|
||||
------------------
|
||||
|
||||
The recommended bit switch settings are as follows:
|
||||
|
||||
SW2 OFF(1)/ON(0) Description
|
||||
------------------------------------------
|
||||
bit 1 <---- BKSZ[0]
|
||||
bit 2 ----> BKSZ[1]
|
||||
bit 3 <---- SoC Bus Width 16/32
|
||||
bit 4 <---- SERIAL_SEL[0]
|
||||
bit 5 ----> SERIAL_SEL[1]
|
||||
bit 6 ----> BOOTSWAP_EN
|
||||
bit 7 <---- CS1/CS5
|
||||
bit 8 <---- SOC_SERIAL_DISABLE
|
||||
|
||||
SW8 OFF(1)/ON(0) Description
|
||||
------------------------------------------
|
||||
bit 1 ----> CS1_SPLIT
|
||||
bit 2 <---- CASE9_ON
|
||||
bit 3 <---- CASE10_ON
|
||||
bit 4 Don't Care Reserve
|
||||
bit 5 Don't Care Reserve
|
||||
bit 6 Don't Care Reserve
|
||||
bit 7 ----> BURST_EN
|
||||
bit 8 ----> FLASHBUS32_16
|
||||
|
||||
The BKSZ[1:0] specifies the address range of memory slot and peripherals
|
||||
as follows:
|
||||
|
||||
BKSZ Description RAM slot Peripherals
|
||||
--------------------------------------------------------------------
|
||||
0b00 15MB RAM / 1MB Peri 00000000-0effffff 0f000000-0fffffff
|
||||
0b01 31MB RAM / 1MB Peri 00000000-1effffff 1f000000-1fffffff
|
||||
0b10 64MB RAM / 1MB Peri 00000000-3effffff 3f000000-3fffffff
|
||||
0b11 127MB RAM / 1MB Peri 00000000-7effffff 7f000000-7fffffff
|
||||
|
||||
Set BSKZ[1:0] to 0b01 for U-Boot.
|
||||
This mode is the most handy because EA[24] is always supported by the save pin
|
||||
mode of the system bus. On the other hand, EA[25] is not supported for some
|
||||
newer SoCs. Even if it is, EA[25] is not connected on most of the boards.
|
||||
|
||||
--
|
||||
Masahiro Yamada <yamada.m@jp.panasonic.com>
|
||||
Feb. 2015
|
||||
Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
Jul. 2015
|
||||
|
|
|
|||
|
|
@ -9,15 +9,18 @@
|
|||
#ifndef __CONFIG_UNIPHIER_COMMON_H__
|
||||
#define __CONFIG_UNIPHIER_COMMON_H__
|
||||
|
||||
#if defined(CONFIG_MACH_PH1_PRO4)
|
||||
#if defined(CONFIG_MACH_PH1_SLD3)
|
||||
#define CONFIG_DDR_NUM_CH0 2
|
||||
#define CONFIG_DDR_NUM_CH1 2
|
||||
#define CONFIG_DDR_NUM_CH1 1
|
||||
#define CONFIG_DDR_NUM_CH2 1
|
||||
|
||||
/* Physical start address of SDRAM */
|
||||
#define CONFIG_SDRAM0_BASE 0x80000000
|
||||
#define CONFIG_SDRAM0_SIZE 0x20000000
|
||||
#define CONFIG_SDRAM1_BASE 0xa0000000
|
||||
#define CONFIG_SDRAM1_BASE 0xc0000000
|
||||
#define CONFIG_SDRAM1_SIZE 0x20000000
|
||||
#define CONFIG_SDRAM2_BASE 0xc0000000
|
||||
#define CONFIG_SDRAM2_SIZE 0x10000000
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MACH_PH1_LD4)
|
||||
|
|
@ -31,6 +34,17 @@
|
|||
#define CONFIG_SDRAM1_SIZE 0x10000000
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MACH_PH1_PRO4)
|
||||
#define CONFIG_DDR_NUM_CH0 2
|
||||
#define CONFIG_DDR_NUM_CH1 2
|
||||
|
||||
/* Physical start address of SDRAM */
|
||||
#define CONFIG_SDRAM0_BASE 0x80000000
|
||||
#define CONFIG_SDRAM0_SIZE 0x20000000
|
||||
#define CONFIG_SDRAM1_BASE 0xa0000000
|
||||
#define CONFIG_SDRAM1_SIZE 0x20000000
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MACH_PH1_SLD8)
|
||||
#define CONFIG_DDR_NUM_CH0 1
|
||||
#define CONFIG_DDR_NUM_CH1 1
|
||||
|
|
@ -177,8 +191,13 @@
|
|||
|
||||
#define CONFIG_NAND_DENALI_ECC_SIZE 1024
|
||||
|
||||
#ifdef CONFIG_MACH_PH1_SLD3
|
||||
#define CONFIG_SYS_NAND_REGS_BASE 0xf8100000
|
||||
#define CONFIG_SYS_NAND_DATA_BASE 0xf8000000
|
||||
#else
|
||||
#define CONFIG_SYS_NAND_REGS_BASE 0x68100000
|
||||
#define CONFIG_SYS_NAND_DATA_BASE 0x68000000
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10)
|
||||
|
||||
|
|
@ -209,7 +228,6 @@
|
|||
|
||||
#define CONFIG_LOADADDR 0x84000000
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
#define CONFIG_BOOTFILE "fit.itb"
|
||||
|
||||
#define CONFIG_CMDLINE_EDITING /* add command line history */
|
||||
|
||||
|
|
@ -222,25 +240,61 @@
|
|||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
|
||||
"tftpboot; bootm;"
|
||||
|
||||
#define CONFIG_BOOTARGS " user_debug=0x1f init=/sbin/init"
|
||||
#define CONFIG_BOOTARGS " earlyprintk loglevel=8"
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"image_offset=0x00080000\0" \
|
||||
"image_size=0x00f00000\0" \
|
||||
"verify=n\0" \
|
||||
"nandupdate=nand erase 0 0x100000 &&" \
|
||||
"tftpboot u-boot-spl.bin &&" \
|
||||
"nand write $loadaddr 0 0x10000 &&" \
|
||||
"tftpboot u-boot-dtb.img &&" \
|
||||
"nand write $loadaddr 0x10000 0xf0000\0" \
|
||||
"norboot=run add_default_bootargs &&" \
|
||||
"bootm $image_offset\0" \
|
||||
"nandboot=run add_default_bootargs &&" \
|
||||
"nand read $loadaddr $image_offset $image_size &&" \
|
||||
"bootm\0" \
|
||||
"add_default_bootargs=setenv bootargs $bootargs" \
|
||||
" console=ttyS0,$baudrate\0" \
|
||||
#ifdef CONFIG_FIT
|
||||
#define CONFIG_BOOTFILE "fitImage"
|
||||
#define LINUXBOOT_ENV_SETTINGS \
|
||||
"fit_addr=0x00100000\0" \
|
||||
"fit_addr_r=0x84100000\0" \
|
||||
"fit_size=0x00f00000\0" \
|
||||
"norboot=run add_default_bootargs &&" \
|
||||
"bootm $fit_addr\0" \
|
||||
"nandboot=run add_default_bootargs &&" \
|
||||
"nand read $fit_addr_r $fit_addr $fit_size &&" \
|
||||
"bootm $fit_addr_r\0" \
|
||||
"tftpboot=run add_default_bootargs &&" \
|
||||
"tftpboot $fit_addr_r $bootfile &&" \
|
||||
"bootm $fit_addr_r\0"
|
||||
#else
|
||||
#define CONFIG_BOOTFILE "uImage"
|
||||
#define LINUXBOOT_ENV_SETTINGS \
|
||||
"fdt_addr=0x00100000\0" \
|
||||
"fdt_addr_r=0x84100000\0" \
|
||||
"fdt_size=0x00008000\0" \
|
||||
"fdt_file=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
|
||||
"kernel_addr=0x00200000\0" \
|
||||
"kernel_addr_r=0x84200000\0" \
|
||||
"kernel_size=0x00800000\0" \
|
||||
"ramdisk_addr=0x00a00000\0" \
|
||||
"ramdisk_addr_r=0x84a00000\0" \
|
||||
"ramdisk_size=0x00600000\0" \
|
||||
"ramdisk_file=rootfs.cpio.uboot\0" \
|
||||
"norboot=run add_default_bootargs &&" \
|
||||
"bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \
|
||||
"nandboot=run add_default_bootargs &&" \
|
||||
"nand read $kernel_addr_r $kernel_addr $kernel_size &&" \
|
||||
"nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \
|
||||
"nand read $fdt_addr_r $fdt_addr $fdt_size &&" \
|
||||
"bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
|
||||
"tftpboot=run add_default_bootargs &&" \
|
||||
"tftpboot $kernel_addr_r $bootfile &&" \
|
||||
"tftpboot $ramdisk_addr_r $ramdisk_file &&" \
|
||||
"tftpboot $fdt_addr_r $fdt_file &&" \
|
||||
"bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0"
|
||||
#endif
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"verify=n\0" \
|
||||
"nandupdate=nand erase 0 0x00100000 &&" \
|
||||
"tftpboot u-boot-spl.bin &&" \
|
||||
"nand write $loadaddr 0 0x00010000 &&" \
|
||||
"tftpboot u-boot-dtb.img &&" \
|
||||
"nand write $loadaddr 0x00010000 0x000f0000\0" \
|
||||
"add_default_bootargs=setenv bootargs $bootargs" \
|
||||
" console=ttyS0,$baudrate\0" \
|
||||
LINUXBOOT_ENV_SETTINGS
|
||||
|
||||
/* Open Firmware flat tree */
|
||||
#define CONFIG_OF_LIBFDT
|
||||
|
|
@ -259,7 +313,8 @@
|
|||
#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
|
||||
#if defined(CONFIG_MACH_PH1_SLD3) || defined(CONFIG_MACH_PH1_LD4) || \
|
||||
defined(CONFIG_MACH_PH1_SLD8)
|
||||
#define CONFIG_SPL_TEXT_BASE 0x00040000
|
||||
#endif
|
||||
#if defined(CONFIG_MACH_PH1_PRO4)
|
||||
|
|
|
|||
Loading…
Reference in New Issue