ARM: remove jadecpu board support
This is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Matthias Weisser <weisserm@arcor.de> Acked-by: Marek Vasut <marex@denx.de>utp
Masahiro Yamada
Tom Rini
parent
d648964fc2
commit
41fbbbbc71
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@ -144,10 +144,6 @@ config TARGET_DEVKIT3250
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bool "Support devkit3250"
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select CPU_ARM926EJS
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config TARGET_JADECPU
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bool "Support jadecpu"
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select CPU_ARM926EJS
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config TARGET_MX25PDK
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bool "Support mx25pdk"
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select CPU_ARM926EJS
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@ -852,7 +848,6 @@ source "board/st-ericsson/snowball/Kconfig"
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source "board/st-ericsson/u8500/Kconfig"
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source "board/st/stv0991/Kconfig"
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source "board/sunxi/Kconfig"
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source "board/syteco/jadecpu/Kconfig"
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source "board/syteco/zmx25/Kconfig"
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source "board/tbs/tbs2910/Kconfig"
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source "board/ti/am335x/Kconfig"
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@ -16,7 +16,6 @@ endif
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obj-$(CONFIG_ARMADA100) += armada100/
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obj-$(if $(filter lpc32xx,$(SOC)),y) += lpc32xx/
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obj-$(CONFIG_MB86R0x) += mb86r0x/
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obj-$(CONFIG_MX25) += mx25/
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obj-$(CONFIG_MX27) += mx27/
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obj-$(if $(filter mxs,$(SOC)),y) += mxs/
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@ -1,8 +0,0 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = clock.o reset.o timer.o
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@ -1,27 +0,0 @@
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/*
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* (C) Copyright 2010
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* Matthias Weisser <weisserm@arcor.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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/*
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* Get the peripheral bus frequency depending on pll pin settings
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*/
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ulong get_bus_freq(ulong dummy)
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{
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struct mb86r0x_crg * crg = (struct mb86r0x_crg *)
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MB86R0x_CRG_BASE;
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uint32_t pllmode;
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pllmode = readl(&crg->crpr) & MB86R0x_CRG_CRPR_PLLMODE;
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if (pllmode == MB86R0x_CRG_CRPR_PLLMODE_X20)
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return 40000000;
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return 41164767;
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}
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@ -1,24 +0,0 @@
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/*
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* (C) Copyright 2010
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* Matthias Weisser <weisserm@arcor.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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/*
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* Reset the cpu by setting software reset request bit
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*/
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void reset_cpu(ulong ignored)
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{
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struct mb86r0x_crg * crg = (struct mb86r0x_crg *)
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MB86R0x_CRG_BASE;
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writel(MB86R0x_CRSR_SWRSTREQ, &crg->crsr);
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while (1)
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/* NOP */;
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/* Never reached */
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}
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@ -1,115 +0,0 @@
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/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian@popies.net>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* (C) Copyright 2010
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* Matthias Weisser, Graf-Syteco <weisserm@arcor.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <div64.h>
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#define TIMER_LOAD_VAL 0xffffffff
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#define TIMER_FREQ (CONFIG_MB86R0x_IOCLK / 256)
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DECLARE_GLOBAL_DATA_PTR;
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#define timestamp gd->arch.tbl
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#define lastdec gd->arch.lastinc
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static inline unsigned long long tick_to_time(unsigned long long tick)
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{
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tick *= CONFIG_SYS_HZ;
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do_div(tick, TIMER_FREQ);
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return tick;
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}
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static inline unsigned long long usec_to_tick(unsigned long long usec)
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{
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usec *= TIMER_FREQ;
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do_div(usec, 1000000);
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return usec;
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}
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/* nothing really to do with interrupts, just starts up a counter. */
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int timer_init(void)
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{
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struct mb86r0x_timer * timer = (struct mb86r0x_timer *)
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MB86R0x_TIMER_BASE;
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ulong ctrl = readl(&timer->control);
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writel(TIMER_LOAD_VAL, &timer->load);
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ctrl |= MB86R0x_TIMER_ENABLE | MB86R0x_TIMER_PRS_8S |
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MB86R0x_TIMER_SIZE_32;
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writel(ctrl, &timer->control);
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/* capture current value time */
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lastdec = readl(&timer->value);
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timestamp = 0; /* start "advancing" time stamp from 0 */
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return 0;
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}
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/*
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* timer without interrupts
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*/
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unsigned long long get_ticks(void)
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{
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struct mb86r0x_timer * timer = (struct mb86r0x_timer *)
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MB86R0x_TIMER_BASE;
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ulong now = readl(&timer->value);
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if (now <= lastdec) {
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/* normal mode (non roll) */
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/* move stamp forward with absolut diff ticks */
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timestamp += lastdec - now;
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} else {
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/* we have rollover of incrementer */
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timestamp += lastdec + TIMER_LOAD_VAL - now;
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}
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lastdec = now;
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return timestamp;
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}
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ulong get_timer_masked(void)
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{
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return tick_to_time(get_ticks());
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}
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void __udelay(unsigned long usec)
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{
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unsigned long long tmp;
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ulong tmo;
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tmo = usec_to_tick(usec);
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tmp = get_ticks(); /* get current timestamp */
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while ((get_ticks() - tmp) < tmo) /* loop till event */
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/*NOP*/;
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}
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ulong get_timer(ulong base)
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{
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return get_timer_masked() - base;
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}
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/*
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* This function is derived from PowerPC code (timebase clock frequency).
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* On ARM it returns the number of timer ticks per second.
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*/
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ulong get_tbclk(void)
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{
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ulong tbclk;
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tbclk = TIMER_FREQ;
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return tbclk;
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}
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@ -1,15 +0,0 @@
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/*
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* (C) Copyright 2007
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*
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* Author : Carsten Schneider, mycable GmbH
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* <cs@mycable.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_HARDWARE_H
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#define __ASM_ARCH_HARDWARE_H
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#include <linux/sizes.h>
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#include <asm/arch/mb86r0x.h>
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#endif
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@ -1,599 +0,0 @@
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/*
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* (C) Copyright 2007
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*
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* mb86r0x definitions
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*
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* Author : Carsten Schneider, mycable GmbH
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* <cs@mycable.de>
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*
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* (C) Copyright 2010
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* Matthias Weisser <weisserm@arcor.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef MB86R0X_H
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#define MB86R0X_H
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#ifndef __ASSEMBLY__
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/* GPIO registers */
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struct mb86r0x_gpio {
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uint32_t gpdr0;
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uint32_t gpdr1;
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uint32_t gpdr2;
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uint32_t res;
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uint32_t gpddr0;
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uint32_t gpddr1;
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uint32_t gpddr2;
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};
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/* PWM registers */
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struct mb86r0x_pwm {
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uint32_t bcr;
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uint32_t tpr;
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uint32_t pr;
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uint32_t dr;
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uint32_t cr;
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uint32_t sr;
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uint32_t ccr;
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uint32_t ir;
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};
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/* The mb86r0x chip control (CCNT) register set. */
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struct mb86r0x_ccnt {
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uint32_t ccid;
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uint32_t csrst;
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uint32_t pad0[2];
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uint32_t cist;
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uint32_t cistm;
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uint32_t cgpio_ist;
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uint32_t cgpio_istm;
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uint32_t cgpio_ip;
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uint32_t cgpio_im;
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uint32_t caxi_bw;
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uint32_t caxi_ps;
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uint32_t cmux_md;
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uint32_t cex_pin_st;
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uint32_t cmlb;
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uint32_t pad1[1];
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uint32_t cusb;
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uint32_t pad2[41];
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uint32_t cbsc;
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uint32_t cdcrc;
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uint32_t cmsr0;
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uint32_t cmsr1;
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uint32_t pad3[2];
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};
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/* The mb86r0x clock reset generator */
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struct mb86r0x_crg {
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uint32_t crpr;
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uint32_t pad0;
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uint32_t crwr;
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uint32_t crsr;
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uint32_t crda;
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uint32_t crdb;
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uint32_t crha;
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uint32_t crpa;
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uint32_t crpb;
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uint32_t crhb;
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uint32_t cram;
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};
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/* The mb86r0x timer */
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struct mb86r0x_timer {
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uint32_t load;
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uint32_t value;
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uint32_t control;
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uint32_t intclr;
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uint32_t ris;
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uint32_t mis;
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uint32_t bgload;
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};
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/* mb86r0x gdc display controller */
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struct mb86r0x_gdc_dsp {
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/* Display settings */
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uint32_t dcm0;
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uint16_t pad00;
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uint16_t htp;
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uint16_t hdp;
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uint16_t hdb;
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uint16_t hsp;
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uint8_t hsw;
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uint8_t vsw;
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uint16_t pad01;
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uint16_t vtr;
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uint16_t vsp;
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uint16_t vdp;
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uint16_t wx;
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uint16_t wy;
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uint16_t ww;
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uint16_t wh;
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/* Layer 0 */
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uint32_t l0m;
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uint32_t l0oa;
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uint32_t l0da;
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uint16_t l0dx;
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uint16_t l0dy;
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/* Layer 1 */
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uint32_t l1m;
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uint32_t cbda0;
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uint32_t cbda1;
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uint32_t pad02;
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/* Layer 2 */
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uint32_t l2m;
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uint32_t l2oa0;
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uint32_t l2da0;
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uint32_t l2oa1;
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uint32_t l2da1;
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uint16_t l2dx;
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uint16_t l2dy;
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/* Layer 3 */
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uint32_t l3m;
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uint32_t l3oa0;
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uint32_t l3da0;
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uint32_t l3oa1;
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uint32_t l3da1;
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uint16_t l3dx;
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uint16_t l3dy;
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/* Layer 4 */
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uint32_t l4m;
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uint32_t l4oa0;
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uint32_t l4da0;
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uint32_t l4oa1;
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uint32_t l4da1;
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uint16_t l4dx;
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uint16_t l4dy;
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/* Layer 5 */
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uint32_t l5m;
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uint32_t l5oa0;
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uint32_t l5da0;
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uint32_t l5oa1;
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uint32_t l5da1;
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uint16_t l5dx;
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uint16_t l5dy;
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/* Cursor */
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uint16_t cutc;
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uint8_t cpm;
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uint8_t csize;
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uint32_t cuoa0;
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uint16_t cux0;
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uint16_t cuy0;
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uint32_t cuoa1;
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uint16_t cux1;
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uint16_t cuy1;
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/* Layer blending */
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uint32_t l0bld;
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uint32_t pad03;
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uint32_t l0tc;
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uint16_t l3tc;
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uint16_t l2tc;
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uint32_t pad04[15];
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/* Display settings */
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uint32_t dcm1;
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uint32_t dcm2;
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uint32_t dcm3;
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uint32_t pad05;
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/* Layer 0 extended */
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uint32_t l0em;
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uint16_t l0wx;
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uint16_t l0wy;
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uint16_t l0ww;
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uint16_t l0wh;
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uint32_t pad06;
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/* Layer 1 extended */
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uint32_t l1em;
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uint16_t l1wx;
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uint16_t l1wy;
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uint16_t l1ww;
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uint16_t l1wh;
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uint32_t pad07;
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/* Layer 2 extended */
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uint32_t l2em;
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uint16_t l2wx;
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uint16_t l2wy;
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uint16_t l2ww;
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uint16_t l2wh;
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uint32_t pad08;
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/* Layer 3 extended */
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uint32_t l3em;
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uint16_t l3wx;
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uint16_t l3wy;
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uint16_t l3ww;
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uint16_t l3wh;
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uint32_t pad09;
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/* Layer 4 extended */
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uint32_t l4em;
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uint16_t l4wx;
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uint16_t l4wy;
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uint16_t l4ww;
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uint16_t l4wh;
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uint32_t pad10;
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/* Layer 5 extended */
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uint32_t l5em;
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uint16_t l5wx;
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uint16_t l5wy;
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uint16_t l5ww;
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uint16_t l5wh;
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uint32_t pad11;
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/* Multi screen control */
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uint32_t msc;
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uint32_t pad12[3];
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uint32_t dls;
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uint32_t dbgc;
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/* Layer blending */
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uint32_t l1bld;
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uint32_t l2bld;
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uint32_t l3bld;
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uint32_t l4bld;
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uint32_t l5bld;
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uint32_t pad13;
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/* Extended transparency control */
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uint32_t l0etc;
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uint32_t l1etc;
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uint32_t l2etc;
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uint32_t l3etc;
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uint32_t l4etc;
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uint32_t l5etc;
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uint32_t pad14[10];
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/* YUV coefficients */
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uint32_t l1ycr0;
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uint32_t l1ycr1;
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uint32_t l1ycg0;
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uint32_t l1ycg1;
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uint32_t l1ycb0;
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uint32_t l1ycb1;
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uint32_t pad15[130];
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/* Layer palletes */
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uint32_t l0pal[256];
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uint32_t l1pal[256];
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uint32_t pad16[256];
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uint32_t l2pal[256];
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uint32_t l3pal[256];
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uint32_t pad17[256];
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/* PWM settings */
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uint32_t vpwmm;
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uint16_t vpwms;
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uint16_t vpwme;
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uint32_t vpwmc;
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uint32_t pad18[253];
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};
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/* mb86r0x gdc capture controller */
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struct mb86r0x_gdc_cap {
|
||||
uint32_t vcm;
|
||||
uint32_t csc;
|
||||
uint32_t vcs;
|
||||
uint32_t pad01;
|
||||
|
||||
uint32_t cbm;
|
||||
uint32_t cboa;
|
||||
uint32_t cbla;
|
||||
uint16_t cihstr;
|
||||
uint16_t civstr;
|
||||
uint16_t cihend;
|
||||
uint16_t civend;
|
||||
uint32_t pad02;
|
||||
|
||||
uint32_t chp;
|
||||
uint32_t cvp;
|
||||
uint32_t pad03[4];
|
||||
|
||||
uint32_t clpf;
|
||||
uint32_t pad04;
|
||||
uint32_t cmss;
|
||||
uint32_t cmds;
|
||||
uint32_t pad05[12];
|
||||
|
||||
uint32_t rgbhc;
|
||||
uint32_t rgbhen;
|
||||
uint32_t rgbven;
|
||||
uint32_t pad06;
|
||||
uint32_t rgbs;
|
||||
uint32_t pad07[11];
|
||||
|
||||
uint32_t rgbcmy;
|
||||
uint32_t rgbcmcb;
|
||||
uint32_t rgbcmcr;
|
||||
uint32_t rgbcmb;
|
||||
uint32_t pad08[12 + 1984];
|
||||
};
|
||||
|
||||
/* mb86r0x gdc draw */
|
||||
struct mb86r0x_gdc_draw {
|
||||
uint32_t ys;
|
||||
uint32_t xs;
|
||||
uint32_t dxdy;
|
||||
uint32_t xus;
|
||||
uint32_t dxudy;
|
||||
uint32_t xls;
|
||||
uint32_t dxldy;
|
||||
uint32_t usn;
|
||||
uint32_t lsn;
|
||||
uint32_t pad01[7];
|
||||
uint32_t rs;
|
||||
uint32_t drdx;
|
||||
uint32_t drdy;
|
||||
uint32_t gs;
|
||||
uint32_t dgdx;
|
||||
uint32_t dgdy;
|
||||
uint32_t bs;
|
||||
uint32_t dbdx;
|
||||
uint32_t dbdy;
|
||||
uint32_t pad02[7];
|
||||
uint32_t zs;
|
||||
uint32_t dzdx;
|
||||
uint32_t dzdy;
|
||||
uint32_t pad03[13];
|
||||
uint32_t ss;
|
||||
uint32_t dsdx;
|
||||
uint32_t dsdy;
|
||||
uint32_t ts;
|
||||
uint32_t dtdx;
|
||||
uint32_t dtdy;
|
||||
uint32_t qs;
|
||||
uint32_t dqdx;
|
||||
uint32_t dqdy;
|
||||
uint32_t pad04[23];
|
||||
uint32_t lpn;
|
||||
uint32_t lxs;
|
||||
uint32_t lxde;
|
||||
uint32_t lys;
|
||||
uint32_t lyde;
|
||||
uint32_t lzs;
|
||||
uint32_t lzde;
|
||||
uint32_t pad05[13];
|
||||
uint32_t pxdc;
|
||||
uint32_t pydc;
|
||||
uint32_t pzdc;
|
||||
uint32_t pad06[25];
|
||||
uint32_t rxs;
|
||||
uint32_t rys;
|
||||
uint32_t rsizex;
|
||||
uint32_t rsizey;
|
||||
uint32_t pad07[12];
|
||||
uint32_t saddr;
|
||||
uint32_t sstride;
|
||||
uint32_t srx;
|
||||
uint32_t sry;
|
||||
uint32_t daddr;
|
||||
uint32_t dstride;
|
||||
uint32_t drx;
|
||||
uint32_t dry;
|
||||
uint32_t brsizex;
|
||||
uint32_t brsizey;
|
||||
uint32_t tcolor;
|
||||
uint32_t pad08[93];
|
||||
uint32_t blpo;
|
||||
uint32_t pad09[7];
|
||||
uint32_t ctr;
|
||||
uint32_t ifsr;
|
||||
uint32_t ifcnt;
|
||||
uint32_t sst;
|
||||
uint32_t ds;
|
||||
uint32_t pst;
|
||||
uint32_t est;
|
||||
uint32_t pad10;
|
||||
uint32_t mdr0;
|
||||
uint32_t mdr1;
|
||||
uint32_t mdr2;
|
||||
uint32_t mdr3;
|
||||
uint32_t mdr4;
|
||||
uint32_t pad14[2];
|
||||
uint32_t mdr7;
|
||||
uint32_t fbr;
|
||||
uint32_t xres;
|
||||
uint32_t zbr;
|
||||
uint32_t tbr;
|
||||
uint32_t pfbr;
|
||||
uint32_t cxmin;
|
||||
uint32_t cxmax;
|
||||
uint32_t cymin;
|
||||
uint32_t cymax;
|
||||
uint32_t txs;
|
||||
uint32_t tis;
|
||||
uint32_t toa;
|
||||
uint32_t sho;
|
||||
uint32_t abr;
|
||||
uint32_t pad15[2];
|
||||
uint32_t fc;
|
||||
uint32_t bc;
|
||||
uint32_t alf;
|
||||
uint32_t blp;
|
||||
uint32_t pad16;
|
||||
uint32_t tbc;
|
||||
uint32_t pad11[42];
|
||||
uint32_t lx0dc;
|
||||
uint32_t ly0dc;
|
||||
uint32_t lx1dc;
|
||||
uint32_t ly1dc;
|
||||
uint32_t pad12[12];
|
||||
uint32_t x0dc;
|
||||
uint32_t y0dc;
|
||||
uint32_t x1dc;
|
||||
uint32_t y1dc;
|
||||
uint32_t x2dc;
|
||||
uint32_t y2dc;
|
||||
uint32_t pad13[666];
|
||||
};
|
||||
|
||||
/* mb86r0x gdc geometry engine */
|
||||
struct mb86r0x_gdc_geom {
|
||||
uint32_t gctr;
|
||||
uint32_t pad00[15];
|
||||
uint32_t gmdr0;
|
||||
uint32_t gmdr1;
|
||||
uint32_t gmdr2;
|
||||
uint32_t pad01[237];
|
||||
uint32_t dfifog;
|
||||
uint32_t pad02[767];
|
||||
};
|
||||
|
||||
/* mb86r0x gdc */
|
||||
struct mb86r0x_gdc {
|
||||
uint32_t pad00[2];
|
||||
uint32_t lts;
|
||||
uint32_t pad01;
|
||||
uint32_t lsta;
|
||||
uint32_t pad02[3];
|
||||
uint32_t ist;
|
||||
uint32_t imask;
|
||||
uint32_t pad03[6];
|
||||
uint32_t lsa;
|
||||
uint32_t lco;
|
||||
uint32_t lreq;
|
||||
|
||||
uint32_t pad04[16*1024 - 19];
|
||||
struct mb86r0x_gdc_dsp dsp0;
|
||||
struct mb86r0x_gdc_dsp dsp1;
|
||||
uint32_t pad05[4*1024 - 2];
|
||||
uint32_t vccc;
|
||||
uint32_t vcsr;
|
||||
struct mb86r0x_gdc_cap cap0;
|
||||
struct mb86r0x_gdc_cap cap1;
|
||||
uint32_t pad06[4*1024];
|
||||
uint32_t texture_base[16*1024];
|
||||
struct mb86r0x_gdc_draw draw;
|
||||
uint32_t pad07[7*1024];
|
||||
struct mb86r0x_gdc_geom geom;
|
||||
uint32_t pad08[7*1024];
|
||||
};
|
||||
|
||||
/* mb86r0x ddr2c */
|
||||
struct mb86r0x_ddr2c {
|
||||
uint16_t dric;
|
||||
uint16_t dric1;
|
||||
uint16_t dric2;
|
||||
uint16_t drca;
|
||||
uint16_t drcm;
|
||||
uint16_t drcst1;
|
||||
uint16_t drcst2;
|
||||
uint16_t drcr;
|
||||
uint16_t pad00[8];
|
||||
uint16_t drcf;
|
||||
uint16_t pad01[7];
|
||||
uint16_t drasr;
|
||||
uint16_t pad02[15];
|
||||
uint16_t drims;
|
||||
uint16_t pad03[7];
|
||||
uint16_t dros;
|
||||
uint16_t pad04;
|
||||
uint16_t dribsodt1;
|
||||
uint16_t dribsocd;
|
||||
uint16_t dribsocd2;
|
||||
uint16_t pad05[3];
|
||||
uint16_t droaba;
|
||||
uint16_t pad06[9];
|
||||
uint16_t drobs;
|
||||
uint16_t pad07[5];
|
||||
uint16_t drimr1;
|
||||
uint16_t drimr2;
|
||||
uint16_t drimr3;
|
||||
uint16_t drimr4;
|
||||
uint16_t droisr1;
|
||||
uint16_t droisr2;
|
||||
};
|
||||
|
||||
/* mb86r0x memc */
|
||||
struct mb86r0x_memc {
|
||||
uint32_t mcfmode[8];
|
||||
uint32_t mcftim[8];
|
||||
uint32_t mcfarea[8];
|
||||
};
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
/*
|
||||
* Physical Address Defines
|
||||
*/
|
||||
#define MB86R0x_DDR2_BASE 0xf3000000
|
||||
#define MB86R0x_GDC_BASE 0xf1fc0000
|
||||
#define MB86R0x_CCNT_BASE 0xfff42000
|
||||
#define MB86R0x_CAN0_BASE 0xfff54000
|
||||
#define MB86R0x_CAN1_BASE 0xfff55000
|
||||
#define MB86R0x_I2C0_BASE 0xfff56000
|
||||
#define MB86R0x_I2C1_BASE 0xfff57000
|
||||
#define MB86R0x_EHCI_BASE 0xfff80000
|
||||
#define MB86R0x_OHCI_BASE 0xfff81000
|
||||
#define MB86R0x_IRC1_BASE 0xfffb0000
|
||||
#define MB86R0x_MEMC_BASE 0xfffc0000
|
||||
#define MB86R0x_TIMER_BASE 0xfffe0000
|
||||
#define MB86R0x_UART0_BASE 0xfffe1000
|
||||
#define MB86R0x_UART1_BASE 0xfffe2000
|
||||
#define MB86R0x_IRCE_BASE 0xfffe4000
|
||||
#define MB86R0x_CRG_BASE 0xfffe7000
|
||||
#define MB86R0x_IRC0_BASE 0xfffe8000
|
||||
#define MB86R0x_GPIO_BASE 0xfffe9000
|
||||
#define MB86R0x_PWM0_BASE 0xfff41000
|
||||
#define MB86R0x_PWM1_BASE 0xfff41100
|
||||
|
||||
#define MB86R0x_CRSR_SWRSTREQ (1 << 1)
|
||||
|
||||
/*
|
||||
* Timer register bits
|
||||
*/
|
||||
#define MB86R0x_TIMER_ENABLE (1 << 7)
|
||||
#define MB86R0x_TIMER_MODE_MSK (1 << 6)
|
||||
#define MB86R0x_TIMER_MODE_FR (0 << 6)
|
||||
#define MB86R0x_TIMER_MODE_PD (1 << 6)
|
||||
|
||||
#define MB86R0x_TIMER_INT_EN (1 << 5)
|
||||
#define MB86R0x_TIMER_PRS_MSK (3 << 2)
|
||||
#define MB86R0x_TIMER_PRS_4S (1 << 2)
|
||||
#define MB86R0x_TIMER_PRS_8S (1 << 3)
|
||||
#define MB86R0x_TIMER_SIZE_32 (1 << 1)
|
||||
#define MB86R0x_TIMER_ONE_SHT (1 << 0)
|
||||
|
||||
/*
|
||||
* Clock reset generator bits
|
||||
*/
|
||||
#define MB86R0x_CRG_CRPR_PLLRDY (1 << 8)
|
||||
#define MB86R0x_CRG_CRPR_PLLMODE (0x1f << 0)
|
||||
#define MB86R0x_CRG_CRPR_PLLMODE_X49 (0 << 0)
|
||||
#define MB86R0x_CRG_CRPR_PLLMODE_X46 (1 << 0)
|
||||
#define MB86R0x_CRG_CRPR_PLLMODE_X37 (2 << 0)
|
||||
#define MB86R0x_CRG_CRPR_PLLMODE_X20 (3 << 0)
|
||||
#define MB86R0x_CRG_CRPR_PLLMODE_X47 (4 << 0)
|
||||
#define MB86R0x_CRG_CRPR_PLLMODE_X44 (5 << 0)
|
||||
#define MB86R0x_CRG_CRPR_PLLMODE_X36 (6 << 0)
|
||||
#define MB86R0x_CRG_CRPR_PLLMODE_X19 (7 << 0)
|
||||
#define MB86R0x_CRG_CRPR_PLLMODE_X39 (8 << 0)
|
||||
#define MB86R0x_CRG_CRPR_PLLMODE_X38 (9 << 0)
|
||||
#define MB86R0x_CRG_CRPR_PLLMODE_X30 (10 << 0)
|
||||
#define MB86R0x_CRG_CRPR_PLLMODE_X15 (11 << 0)
|
||||
/*
|
||||
* DDR2 controller bits
|
||||
*/
|
||||
#define MB86R0x_DDR2_DRCI_DRINI (1 << 15)
|
||||
#define MB86R0x_DDR2_DRCI_CKEN (1 << 14)
|
||||
#define MB86R0x_DDR2_DRCI_DRCMD (1 << 0)
|
||||
#define MB86R0x_DDR2_DRCI_CMD (MB86R0x_DDR2_DRCI_DRINI | \
|
||||
MB86R0x_DDR2_DRCI_CKEN | \
|
||||
MB86R0x_DDR2_DRCI_DRCMD)
|
||||
#define MB86R0x_DDR2_DRCI_INIT (MB86R0x_DDR2_DRCI_DRINI | \
|
||||
MB86R0x_DDR2_DRCI_CKEN)
|
||||
#define MB86R0x_DDR2_DRCI_NORMAL MB86R0x_DDR2_DRCI_CKEN
|
||||
#endif /* MB86R0X_H */
|
||||
|
|
@ -15,9 +15,6 @@
|
|||
#include <common.h>
|
||||
#include <linux/kbuild.h>
|
||||
|
||||
#if defined(CONFIG_MB86R0x)
|
||||
#include <asm/arch/mb86r0x.h>
|
||||
#endif
|
||||
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) \
|
||||
|| defined(CONFIG_MX51) || defined(CONFIG_MX53)
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
|
@ -27,8 +24,6 @@ int main(void)
|
|||
{
|
||||
/*
|
||||
* TODO : Check if each entry in this file is really necessary.
|
||||
* - struct mb86r0x_ddr2
|
||||
* - struct mb86r0x_memc
|
||||
* - struct esdramc_regs
|
||||
* - struct max_regs
|
||||
* - struct aips_regs
|
||||
|
|
@ -40,47 +35,6 @@ int main(void)
|
|||
* code. Is it better to define the macros directly in headers?
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_MB86R0x)
|
||||
/* ddr2 controller */
|
||||
DEFINE(DDR2_DRIC, offsetof(struct mb86r0x_ddr2c, dric));
|
||||
DEFINE(DDR2_DRIC1, offsetof(struct mb86r0x_ddr2c, dric1));
|
||||
DEFINE(DDR2_DRIC2, offsetof(struct mb86r0x_ddr2c, dric2));
|
||||
DEFINE(DDR2_DRCA, offsetof(struct mb86r0x_ddr2c, drca));
|
||||
DEFINE(DDR2_DRCM, offsetof(struct mb86r0x_ddr2c, drcm));
|
||||
DEFINE(DDR2_DRCST1, offsetof(struct mb86r0x_ddr2c, drcst1));
|
||||
DEFINE(DDR2_DRCST2, offsetof(struct mb86r0x_ddr2c, drcst2));
|
||||
DEFINE(DDR2_DRCR, offsetof(struct mb86r0x_ddr2c, drcr));
|
||||
DEFINE(DDR2_DRCF, offsetof(struct mb86r0x_ddr2c, drcf));
|
||||
DEFINE(DDR2_DRASR, offsetof(struct mb86r0x_ddr2c, drasr));
|
||||
DEFINE(DDR2_DRIMS, offsetof(struct mb86r0x_ddr2c, drims));
|
||||
DEFINE(DDR2_DROS, offsetof(struct mb86r0x_ddr2c, dros));
|
||||
DEFINE(DDR2_DRIBSODT1, offsetof(struct mb86r0x_ddr2c, dribsodt1));
|
||||
DEFINE(DDR2_DROABA, offsetof(struct mb86r0x_ddr2c, droaba));
|
||||
DEFINE(DDR2_DROBS, offsetof(struct mb86r0x_ddr2c, drobs));
|
||||
|
||||
/* clock reset generator */
|
||||
DEFINE(CRG_CRPR, offsetof(struct mb86r0x_crg, crpr));
|
||||
DEFINE(CRG_CRHA, offsetof(struct mb86r0x_crg, crha));
|
||||
DEFINE(CRG_CRPA, offsetof(struct mb86r0x_crg, crpa));
|
||||
DEFINE(CRG_CRPB, offsetof(struct mb86r0x_crg, crpb));
|
||||
DEFINE(CRG_CRHB, offsetof(struct mb86r0x_crg, crhb));
|
||||
DEFINE(CRG_CRAM, offsetof(struct mb86r0x_crg, cram));
|
||||
|
||||
/* chip control module */
|
||||
DEFINE(CCNT_CDCRC, offsetof(struct mb86r0x_ccnt, cdcrc));
|
||||
|
||||
/* external bus interface */
|
||||
DEFINE(MEMC_MCFMODE0, offsetof(struct mb86r0x_memc, mcfmode[0]));
|
||||
DEFINE(MEMC_MCFMODE2, offsetof(struct mb86r0x_memc, mcfmode[2]));
|
||||
DEFINE(MEMC_MCFMODE4, offsetof(struct mb86r0x_memc, mcfmode[4]));
|
||||
DEFINE(MEMC_MCFTIM0, offsetof(struct mb86r0x_memc, mcftim[0]));
|
||||
DEFINE(MEMC_MCFTIM2, offsetof(struct mb86r0x_memc, mcftim[2]));
|
||||
DEFINE(MEMC_MCFTIM4, offsetof(struct mb86r0x_memc, mcftim[4]));
|
||||
DEFINE(MEMC_MCFAREA0, offsetof(struct mb86r0x_memc, mcfarea[0]));
|
||||
DEFINE(MEMC_MCFAREA2, offsetof(struct mb86r0x_memc, mcfarea[2]));
|
||||
DEFINE(MEMC_MCFAREA4, offsetof(struct mb86r0x_memc, mcfarea[4]));
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MX25)
|
||||
/* Clock Control Module */
|
||||
DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl));
|
||||
|
|
|
|||
|
|
@ -1,15 +0,0 @@
|
|||
if TARGET_JADECPU
|
||||
|
||||
config SYS_BOARD
|
||||
default "jadecpu"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "syteco"
|
||||
|
||||
config SYS_SOC
|
||||
default "mb86r0x"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "jadecpu"
|
||||
|
||||
endif
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
JADECPU BOARD
|
||||
M: Matthias Weisser <weisserm@arcor.de>
|
||||
S: Maintained
|
||||
F: board/syteco/jadecpu/
|
||||
F: include/configs/jadecpu.h
|
||||
F: configs/jadecpu_defconfig
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
#
|
||||
# (C) Copyright 2003-2008
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# (C) Copyright 2008
|
||||
# Stelian Pop <stelian@popies.net>
|
||||
# Lead Tech Design <www.leadtechdesign.com>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += jadecpu.o
|
||||
obj-y += lowlevel_init.o
|
||||
|
|
@ -1,160 +0,0 @@
|
|||
/*
|
||||
* (c) 2010 Graf-Syteco, Matthias Weisser
|
||||
* <weisserm@arcor.de>
|
||||
*
|
||||
* (C) Copyright 2007, mycable GmbH
|
||||
* Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/mb86r0x.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/*
|
||||
* Miscellaneous platform dependent initialisations
|
||||
*/
|
||||
int board_init(void)
|
||||
{
|
||||
struct mb86r0x_ccnt * ccnt = (struct mb86r0x_ccnt *)
|
||||
MB86R0x_CCNT_BASE;
|
||||
|
||||
/* We select mode 0 for group 2 and mode 1 for group 4 */
|
||||
writel(0x00000010, &ccnt->cmux_md);
|
||||
|
||||
gd->flags = 0;
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM + PHYS_SDRAM_SIZE - 0x10000;
|
||||
|
||||
icache_enable();
|
||||
dcache_enable();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void setup_display_power(uint32_t pwr_bit, char *pwm_opts,
|
||||
unsigned long pwm_base)
|
||||
{
|
||||
struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *)
|
||||
MB86R0x_GPIO_BASE;
|
||||
struct mb86r0x_pwm *pwm = (struct mb86r0x_pwm *) pwm_base;
|
||||
const char *e;
|
||||
|
||||
writel(readl(&gpio->gpdr2) | pwr_bit, &gpio->gpdr2);
|
||||
|
||||
e = getenv(pwm_opts);
|
||||
if (e != NULL) {
|
||||
const char *s;
|
||||
uint32_t freq, init;
|
||||
|
||||
freq = 0;
|
||||
init = 0;
|
||||
|
||||
s = strchr(e, 'f');
|
||||
if (s != NULL)
|
||||
freq = simple_strtol(s + 2, NULL, 0);
|
||||
|
||||
s = strchr(e, 'i');
|
||||
if (s != NULL)
|
||||
init = simple_strtol(s + 2, NULL, 0);
|
||||
|
||||
if (freq > 0) {
|
||||
writel(CONFIG_MB86R0x_IOCLK / 1000 / freq,
|
||||
&pwm->bcr);
|
||||
writel(1002, &pwm->tpr);
|
||||
writel(1, &pwm->pr);
|
||||
writel(init * 10 + 1, &pwm->dr);
|
||||
writel(1, &pwm->cr);
|
||||
writel(1, &pwm->sr);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *)
|
||||
MB86R0x_GPIO_BASE;
|
||||
uint32_t in_word;
|
||||
|
||||
#ifdef CONFIG_VIDEO_MB86R0xGDC
|
||||
/* Check if we have valid display settings and turn on power if so */
|
||||
/* Display 0 */
|
||||
if (getenv("gs_dsp_0_param") || getenv("videomode"))
|
||||
setup_display_power((1 << 3), "gs_dsp_0_pwm",
|
||||
MB86R0x_PWM0_BASE);
|
||||
|
||||
/* The corresponding GPIO is always an output */
|
||||
writel(readl(&gpio->gpddr2) | (1 << 3), &gpio->gpddr2);
|
||||
|
||||
/* Display 1 */
|
||||
if (getenv("gs_dsp_1_param") || getenv("videomode1"))
|
||||
setup_display_power((1 << 4), "gs_dsp_1_pwm",
|
||||
MB86R0x_PWM1_BASE);
|
||||
|
||||
/* The corresponding GPIO is always an output */
|
||||
writel(readl(&gpio->gpddr2) | (1 << 4), &gpio->gpddr2);
|
||||
#endif /* CONFIG_VIDEO_MB86R0xGDC */
|
||||
|
||||
/* 5V enable */
|
||||
writel(readl(&gpio->gpdr1) & ~(1 << 5), &gpio->gpdr1);
|
||||
writel(readl(&gpio->gpddr1) | (1 << 5), &gpio->gpddr1);
|
||||
|
||||
/* We have special boot options if told by GPIOs */
|
||||
in_word = readl(&gpio->gpdr1);
|
||||
|
||||
if ((in_word & 0xC0) == 0xC0) {
|
||||
setenv("stdin", "serial");
|
||||
setenv("stdout", "serial");
|
||||
setenv("stderr", "serial");
|
||||
setenv("preboot", "run gs_slow_boot");
|
||||
} else if ((in_word & 0xC0) != 0) {
|
||||
setenv("stdout", "vga");
|
||||
setenv("preboot", "run gs_slow_boot");
|
||||
} else {
|
||||
setenv("stdin", "serial");
|
||||
setenv("stdout", "serial");
|
||||
setenv("stderr", "serial");
|
||||
if (getenv("gs_devel")) {
|
||||
setenv("preboot", "run gs_slow_boot");
|
||||
} else {
|
||||
setenv("preboot", "run gs_fast_boot");
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* DRAM configuration
|
||||
*/
|
||||
int dram_init(void)
|
||||
{
|
||||
/* dram_init must store complete ramsize in gd->ram_size */
|
||||
gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
|
||||
PHYS_SDRAM_SIZE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void dram_init_banksize(void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM;
|
||||
gd->bd->bi_dram[0].size = gd->ram_size;
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int rc = 0;
|
||||
#ifdef CONFIG_SMC911X
|
||||
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
|
||||
#endif
|
||||
return rc;
|
||||
}
|
||||
|
|
@ -1,249 +0,0 @@
|
|||
/*
|
||||
* Board specific setup info
|
||||
*
|
||||
* (C) Copyright 2007, mycable GmbH
|
||||
* Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de>
|
||||
*
|
||||
* (C) Copyright 2003, ARM Ltd.
|
||||
* Philippe Robin, <philippe.robin@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <version.h>
|
||||
#include <asm/macro.h>
|
||||
#include <asm/arch/mb86r0x.h>
|
||||
#include <generated/asm-offsets.h>
|
||||
|
||||
/* Set up the platform, once the cpu has been initialized */
|
||||
.globl lowlevel_init
|
||||
lowlevel_init:
|
||||
/*
|
||||
* Initialize Clock Reset Generator (CRG)
|
||||
*/
|
||||
|
||||
ldr r0, =MB86R0x_CRG_BASE
|
||||
|
||||
/* Not change the initial value that is set by external pin.*/
|
||||
WAIT_PLL:
|
||||
ldr r2, [r0, #CRG_CRPR] /* Wait for PLLREADY */
|
||||
tst r2, #MB86R0x_CRG_CRPR_PLLRDY
|
||||
beq WAIT_PLL
|
||||
|
||||
/* Set clock gate control */
|
||||
ldr r1, =CONFIG_SYS_CRG_CRHA_INIT
|
||||
str r1, [r0, #CRG_CRHA]
|
||||
ldr r1, =CONFIG_SYS_CRG_CRPA_INIT
|
||||
str r1, [r0, #CRG_CRPA]
|
||||
ldr r1, =CONFIG_SYS_CRG_CRPB_INIT
|
||||
str r1, [r0, #CRG_CRPB]
|
||||
ldr r1, =CONFIG_SYS_CRG_CRHB_INIT
|
||||
str r1, [r0, #CRG_CRHB]
|
||||
ldr r1, =CONFIG_SYS_CRG_CRAM_INIT
|
||||
str r1, [r0, #CRG_CRAM]
|
||||
|
||||
/*
|
||||
* Initialize External Bus Interface
|
||||
*/
|
||||
ldr r0, =MB86R0x_MEMC_BASE
|
||||
|
||||
ldr r1, =CONFIG_SYS_MEMC_MCFMODE0_INIT
|
||||
str r1, [r0, #MEMC_MCFMODE0]
|
||||
ldr r1, =CONFIG_SYS_MEMC_MCFMODE2_INIT
|
||||
str r1, [r0, #MEMC_MCFMODE2]
|
||||
ldr r1, =CONFIG_SYS_MEMC_MCFMODE4_INIT
|
||||
str r1, [r0, #MEMC_MCFMODE4]
|
||||
|
||||
ldr r1, =CONFIG_SYS_MEMC_MCFTIM0_INIT
|
||||
str r1, [r0, #MEMC_MCFTIM0]
|
||||
ldr r1, =CONFIG_SYS_MEMC_MCFTIM2_INIT
|
||||
str r1, [r0, #MEMC_MCFTIM2]
|
||||
ldr r1, =CONFIG_SYS_MEMC_MCFTIM4_INIT
|
||||
str r1, [r0, #MEMC_MCFTIM4]
|
||||
|
||||
ldr r1, =CONFIG_SYS_MEMC_MCFAREA0_INIT
|
||||
str r1, [r0, #MEMC_MCFAREA0]
|
||||
ldr r1, =CONFIG_SYS_MEMC_MCFAREA2_INIT
|
||||
str r1, [r0, #MEMC_MCFAREA2]
|
||||
ldr r1, =CONFIG_SYS_MEMC_MCFAREA4_INIT
|
||||
str r1, [r0, #MEMC_MCFAREA4]
|
||||
|
||||
/*
|
||||
* Initialize DDR2 Controller
|
||||
*/
|
||||
|
||||
/* Wait for PLL LOCK up time or more */
|
||||
wait_timer 20
|
||||
|
||||
/*
|
||||
* (2) Initialize DDRIF
|
||||
*/
|
||||
ldr r0, =MB86R0x_DDR2_BASE
|
||||
ldr r1, =CONFIG_SYS_DDR2_DRIMS_INIT
|
||||
strh r1, [r0, #DDR2_DRIMS]
|
||||
|
||||
/*
|
||||
* (3) Wait for 20MCKPs(120nsec) or more
|
||||
*/
|
||||
wait_timer 20
|
||||
|
||||
/*
|
||||
* (4) IRESET/IUSRRST release
|
||||
*/
|
||||
ldr r0, =MB86R0x_CCNT_BASE
|
||||
ldr r1, =CONFIG_SYS_CCNT_CDCRC_INIT_1
|
||||
str r1, [r0, #CCNT_CDCRC]
|
||||
|
||||
/*
|
||||
* (5) Wait for 20MCKPs(120nsec) or more
|
||||
*/
|
||||
wait_timer 20
|
||||
|
||||
/*
|
||||
* (6) IDLLRST release
|
||||
*/
|
||||
ldr r0, =MB86R0x_CCNT_BASE
|
||||
ldr r1, =CONFIG_SYS_CCNT_CDCRC_INIT_2
|
||||
str r1, [r0, #CCNT_CDCRC]
|
||||
|
||||
/*
|
||||
* (7+8) Wait for 200us(=200000ns) or more (DDR2 Spec)
|
||||
*/
|
||||
wait_timer 33536
|
||||
|
||||
/*
|
||||
* (9) MCKE ON
|
||||
*/
|
||||
ldr r0, =MB86R0x_DDR2_BASE
|
||||
ldr r1, =CONFIG_SYS_DDR2_DRIC1_INIT
|
||||
strh r1, [r0, #DDR2_DRIC1]
|
||||
ldr r1, =CONFIG_SYS_DDR2_DRIC2_INIT
|
||||
strh r1, [r0, #DDR2_DRIC2]
|
||||
ldr r1, =CONFIG_SYS_DDR2_DRCA_INIT
|
||||
strh r1, [r0, #DDR2_DRCA]
|
||||
ldr r1, =MB86R0x_DDR2_DRCI_INIT
|
||||
strh r1, [r0, #DDR2_DRIC]
|
||||
|
||||
/*
|
||||
* (10) Initialize SDRAM
|
||||
*/
|
||||
|
||||
ldr r1, =MB86R0x_DDR2_DRCI_CMD
|
||||
strh r1, [r0, #DDR2_DRIC]
|
||||
|
||||
wait_timer 67 /* 400ns wait */
|
||||
|
||||
ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_1
|
||||
strh r1, [r0, #DDR2_DRIC1]
|
||||
ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_1
|
||||
strh r1, [r0, #DDR2_DRIC2]
|
||||
ldr r1, =MB86R0x_DDR2_DRCI_CMD
|
||||
strh r1, [r0, #DDR2_DRIC]
|
||||
|
||||
ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_2
|
||||
strh r1, [r0, #DDR2_DRIC1]
|
||||
ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_2
|
||||
strh r1, [r0, #DDR2_DRIC2]
|
||||
ldr r1, =MB86R0x_DDR2_DRCI_CMD
|
||||
strh r1, [r0, #DDR2_DRIC]
|
||||
|
||||
ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_3
|
||||
strh r1, [r0, #DDR2_DRIC1]
|
||||
ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_3
|
||||
strh r1, [r0, #DDR2_DRIC2]
|
||||
ldr r1, =MB86R0x_DDR2_DRCI_CMD
|
||||
strh r1, [r0, #DDR2_DRIC]
|
||||
|
||||
ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_4
|
||||
strh r1, [r0, #DDR2_DRIC1]
|
||||
ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_4
|
||||
strh r1, [r0, #DDR2_DRIC2]
|
||||
ldr r1, =MB86R0x_DDR2_DRCI_CMD
|
||||
strh r1, [r0, #DDR2_DRIC]
|
||||
|
||||
ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_5
|
||||
strh r1, [r0, #DDR2_DRIC1]
|
||||
ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_5
|
||||
strh r1, [r0, #DDR2_DRIC2]
|
||||
ldr r1, =MB86R0x_DDR2_DRCI_CMD
|
||||
strh r1, [r0, #DDR2_DRIC]
|
||||
|
||||
wait_timer 200
|
||||
|
||||
ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_6
|
||||
strh r1, [r0, #DDR2_DRIC1]
|
||||
ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_6
|
||||
strh r1, [r0, #DDR2_DRIC2]
|
||||
ldr r1, =MB86R0x_DDR2_DRCI_CMD
|
||||
strh r1, [r0, #DDR2_DRIC]
|
||||
|
||||
ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_7
|
||||
strh r1, [r0, #DDR2_DRIC1]
|
||||
ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_7
|
||||
strh r1, [r0, #DDR2_DRIC2]
|
||||
ldr r1, =MB86R0x_DDR2_DRCI_CMD
|
||||
strh r1, [r0, #DDR2_DRIC]
|
||||
|
||||
wait_timer 18 /* 105ns wait */
|
||||
|
||||
ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_8
|
||||
strh r1, [r0, #DDR2_DRIC1]
|
||||
ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_8
|
||||
strh r1, [r0, #DDR2_DRIC2]
|
||||
ldr r1, =MB86R0x_DDR2_DRCI_CMD
|
||||
strh r1, [r0, #DDR2_DRIC]
|
||||
|
||||
wait_timer 200 /* MRS to OCD: 200clock */
|
||||
|
||||
ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_9
|
||||
strh r1, [r0, #DDR2_DRIC1]
|
||||
ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_9
|
||||
strh r1, [r0, #DDR2_DRIC2]
|
||||
ldr r1, =MB86R0x_DDR2_DRCI_CMD
|
||||
strh r1, [r0, #DDR2_DRIC]
|
||||
|
||||
ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_10
|
||||
strh r1, [r0, #DDR2_DRIC1]
|
||||
ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_10
|
||||
strh r1, [r0, #DDR2_DRIC2]
|
||||
ldr r1, =MB86R0x_DDR2_DRCI_CMD
|
||||
strh r1, [r0, #DDR2_DRIC]
|
||||
|
||||
ldr r1, =CONFIG_SYS_DDR2_DRCM_INIT
|
||||
strh r1, [r0, #DDR2_DRCM]
|
||||
|
||||
ldr r1, =CONFIG_SYS_DDR2_DRCST1_INIT
|
||||
strh r1, [r0, #DDR2_DRCST1]
|
||||
|
||||
ldr r1, =CONFIG_SYS_DDR2_DRCST2_INIT
|
||||
strh r1, [r0, #DDR2_DRCST2]
|
||||
|
||||
ldr r1, =CONFIG_SYS_DDR2_DRCR_INIT
|
||||
strh r1, [r0, #DDR2_DRCR]
|
||||
|
||||
ldr r1, =CONFIG_SYS_DDR2_DRCF_INIT
|
||||
strh r1, [r0, #DDR2_DRCF]
|
||||
|
||||
ldr r1, =CONFIG_SYS_DDR2_DRASR_INIT
|
||||
strh r1, [r0, #DDR2_DRASR]
|
||||
|
||||
/*
|
||||
* (11) ODT setting
|
||||
*/
|
||||
ldr r1, =CONFIG_SYS_DDR2_DROBS_INIT
|
||||
strh r1, [r0, #DDR2_DROBS]
|
||||
ldr r1, =CONFIG_SYS_DDR2_DROABA_INIT
|
||||
strh r1, [r0, #DDR2_DROABA]
|
||||
ldr r1, =CONFIG_SYS_DDR2_DRIBSODT1_INIT
|
||||
strh r1, [r0, #DDR2_DRIBSODT1]
|
||||
|
||||
/*
|
||||
* (12) Shift to ODTCONT ON (SDRAM side) and DDR2 usual operation mode
|
||||
*/
|
||||
ldr r1, =CONFIG_SYS_DDR2_DROS_INIT
|
||||
strh r1, [r0, #DDR2_DROS]
|
||||
ldr r1, =MB86R0x_DDR2_DRCI_NORMAL
|
||||
strh r1, [r0, #DDR2_DRIC]
|
||||
|
||||
mov pc, lr
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_JADECPU=y
|
||||
|
|
@ -12,23 +12,24 @@ The list should be sorted in reverse chronological order.
|
|||
|
||||
Board Arch CPU Commit Removed Last known maintainer/contact
|
||||
=================================================================================================
|
||||
icecube_5200 powerpc mpc5xxx - - Wolfgang Denk <wd@denx.de>
|
||||
Lite5200 powerpc mpc5xxx - -
|
||||
cpci5200 powerpc mpc5xxx - - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
|
||||
mecp5200 powerpc mpc5xxx - - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
|
||||
pf5200 powerpc mpc5xxx - - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
|
||||
PM520 powerpc mpc5xxx - - Josef Wagner <Wagner@Microsys.de>
|
||||
Total5200 powerpc mpc5xxx - -
|
||||
CATcenter powerpc ppc4xx - -
|
||||
PPChameleonEVB powerpc ppc4xx - - Andrea "llandre" Marson <andrea.marson@dave-tech.it>
|
||||
P2020DS powerpc mpc85xx - -
|
||||
P2020COME powerpc mpc85xx - - Ira W. Snyder <iws@ovro.caltech.edu>
|
||||
P2020RDB powerpc mpc85xx - - Poonam Aggrwal <poonam.aggrwal@freescale.com>
|
||||
P2010RDB powerpc mpc85xx - -
|
||||
P1020RDB powerpc mpc85xx - -
|
||||
P1011RDB powerpc mpc85xx - -
|
||||
MPC8360EMDS powerpc mpc83xx - - Dave Liu <daveliu@freescale.com>
|
||||
MPC8360ERDK powerpc mpc83xx - - Anton Vorontsov <avorontsov@ru.mvista.com>
|
||||
jadecpu arm arm926ejs - - Matthias Weisser <weisserm@arcor.de>
|
||||
icecube_5200 powerpc mpc5xxx 37b608a5 2015-01-23 Wolfgang Denk <wd@denx.de>
|
||||
Lite5200 powerpc mpc5xxx 37b608a5 2015-01-23
|
||||
cpci5200 powerpc mpc5xxx 37b608a5 2015-01-23 Reinhard Arlt <reinhard.arlt@esd-electronics.com>
|
||||
mecp5200 powerpc mpc5xxx 37b608a5 2015-01-23 Reinhard Arlt <reinhard.arlt@esd-electronics.com>
|
||||
pf5200 powerpc mpc5xxx 37b608a5 2015-01-23 Reinhard Arlt <reinhard.arlt@esd-electronics.com>
|
||||
PM520 powerpc mpc5xxx a258e732 2015-01-23 Josef Wagner <Wagner@Microsys.de>
|
||||
Total5200 powerpc mpc5xxx ad734f7d 2015-01-23
|
||||
CATcenter powerpc ppc4xx 5344cc1a 2015-01-23
|
||||
PPChameleonEVB powerpc ppc4xx 5344cc1a 2015-01-23 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
|
||||
P2020DS powerpc mpc85xx 168dcc6c 2015-01-23
|
||||
P2020COME powerpc mpc85xx 89123536 2015-01-23 Ira W. Snyder <iws@ovro.caltech.edu>
|
||||
P2020RDB powerpc mpc85xx 743d4815 2015-01-23 Poonam Aggrwal <poonam.aggrwal@freescale.com>
|
||||
P2010RDB powerpc mpc85xx 743d4815 2015-01-23
|
||||
P1020RDB powerpc mpc85xx 743d4815 2015-01-23
|
||||
P1011RDB powerpc mpc85xx 743d4815 2015-01-23
|
||||
MPC8360EMDS powerpc mpc83xx 8d1e3cb1 2015-01-23 Dave Liu <daveliu@freescale.com>
|
||||
MPC8360ERDK powerpc mpc83xx 8d1e3cb1 2015-01-23 Anton Vorontsov <avorontsov@ru.mvista.com>
|
||||
P3G4 powerpc 74xx_7xx d928664f 2015-01-16 Wolfgang Denk <wd@denx.de>
|
||||
ZUMA powerpc 74xx_7xx d928664f 2015-01-16 Nye Liu <nyet@zumanetworks.com>
|
||||
ppmc7xx powerpc 74xx_7xx d928664f 2015-01-16
|
||||
|
|
|
|||
|
|
@ -32,7 +32,6 @@ obj-$(CONFIG_VIDEO_IMX25LCDC) += imx25lcdc.o videomodes.o
|
|||
obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
|
||||
obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
|
||||
obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
|
||||
obj-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o
|
||||
obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
|
||||
obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
|
||||
obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o
|
||||
|
|
|
|||
|
|
@ -1,168 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2010
|
||||
* Matthias Weisser <weisserm@arcor.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/*
|
||||
* mb86r0xgdc.c - Graphic interface for Fujitsu MB86R0x integrated graphic
|
||||
* controller.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#include <malloc.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <video_fb.h>
|
||||
#include "videomodes.h"
|
||||
|
||||
/*
|
||||
* 4MB (at the end of system RAM)
|
||||
*/
|
||||
#define VIDEO_MEM_SIZE 0x400000
|
||||
|
||||
#define FB_SYNC_CLK_INV (1<<16) /* pixel clock inverted */
|
||||
|
||||
/*
|
||||
* Graphic Device
|
||||
*/
|
||||
static GraphicDevice mb86r0x;
|
||||
|
||||
static void dsp_init(struct mb86r0x_gdc_dsp *dsp, char *modestr,
|
||||
u32 *videomem)
|
||||
{
|
||||
struct ctfb_res_modes var_mode;
|
||||
u32 dcm1, dcm2, dcm3;
|
||||
u16 htp, hdp, hdb, hsp, vtr, vsp, vdp;
|
||||
u8 hsw, vsw;
|
||||
u32 l2m, l2em, l2oa0, l2da0, l2oa1, l2da1;
|
||||
u16 l2dx, l2dy, l2wx, l2wy, l2ww, l2wh;
|
||||
unsigned long div;
|
||||
int bpp;
|
||||
|
||||
bpp = video_get_params(&var_mode, modestr);
|
||||
|
||||
if (bpp == 0) {
|
||||
var_mode.xres = 640;
|
||||
var_mode.yres = 480;
|
||||
var_mode.pixclock = 39721; /* 25MHz */
|
||||
var_mode.left_margin = 48;
|
||||
var_mode.right_margin = 16;
|
||||
var_mode.upper_margin = 33;
|
||||
var_mode.lower_margin = 10;
|
||||
var_mode.hsync_len = 96;
|
||||
var_mode.vsync_len = 2;
|
||||
var_mode.sync = 0;
|
||||
var_mode.vmode = 0;
|
||||
bpp = 15;
|
||||
}
|
||||
|
||||
/* Fill memory with white */
|
||||
memset(videomem, 0xFF, var_mode.xres * var_mode.yres * 2);
|
||||
|
||||
mb86r0x.winSizeX = var_mode.xres;
|
||||
mb86r0x.winSizeY = var_mode.yres;
|
||||
|
||||
/* LCD base clock is ~ 660MHZ. We do calculations in kHz */
|
||||
div = 660000 / (1000000000L / var_mode.pixclock);
|
||||
if (div > 64)
|
||||
div = 64;
|
||||
if (0 == div)
|
||||
div = 1;
|
||||
|
||||
dcm1 = (div - 1) << 8;
|
||||
dcm2 = 0x00000000;
|
||||
if (var_mode.sync & FB_SYNC_CLK_INV)
|
||||
dcm3 = 0x00000100;
|
||||
else
|
||||
dcm3 = 0x00000000;
|
||||
|
||||
htp = var_mode.left_margin + var_mode.xres +
|
||||
var_mode.hsync_len + var_mode.right_margin;
|
||||
hdp = var_mode.xres;
|
||||
hdb = var_mode.xres;
|
||||
hsp = var_mode.xres + var_mode.right_margin;
|
||||
hsw = var_mode.hsync_len;
|
||||
|
||||
vsw = var_mode.vsync_len;
|
||||
vtr = var_mode.upper_margin + var_mode.yres +
|
||||
var_mode.vsync_len + var_mode.lower_margin;
|
||||
vsp = var_mode.yres + var_mode.lower_margin;
|
||||
vdp = var_mode.yres;
|
||||
|
||||
l2m = ((var_mode.yres - 1) << (0)) |
|
||||
(((var_mode.xres * 2) / 64) << (16)) |
|
||||
((1) << (31));
|
||||
|
||||
l2em = (1 << 0) | (1 << 1);
|
||||
|
||||
l2oa0 = mb86r0x.frameAdrs;
|
||||
l2da0 = mb86r0x.frameAdrs;
|
||||
l2oa1 = mb86r0x.frameAdrs;
|
||||
l2da1 = mb86r0x.frameAdrs;
|
||||
l2dx = 0;
|
||||
l2dy = 0;
|
||||
l2wx = 0;
|
||||
l2wy = 0;
|
||||
l2ww = var_mode.xres;
|
||||
l2wh = var_mode.yres - 1;
|
||||
|
||||
writel(dcm1, &dsp->dcm1);
|
||||
writel(dcm2, &dsp->dcm2);
|
||||
writel(dcm3, &dsp->dcm3);
|
||||
|
||||
writew(htp, &dsp->htp);
|
||||
writew(hdp, &dsp->hdp);
|
||||
writew(hdb, &dsp->hdb);
|
||||
writew(hsp, &dsp->hsp);
|
||||
writeb(hsw, &dsp->hsw);
|
||||
|
||||
writeb(vsw, &dsp->vsw);
|
||||
writew(vtr, &dsp->vtr);
|
||||
writew(vsp, &dsp->vsp);
|
||||
writew(vdp, &dsp->vdp);
|
||||
|
||||
writel(l2m, &dsp->l2m);
|
||||
writel(l2em, &dsp->l2em);
|
||||
writel(l2oa0, &dsp->l2oa0);
|
||||
writel(l2da0, &dsp->l2da0);
|
||||
writel(l2oa1, &dsp->l2oa1);
|
||||
writel(l2da1, &dsp->l2da1);
|
||||
writew(l2dx, &dsp->l2dx);
|
||||
writew(l2dy, &dsp->l2dy);
|
||||
writew(l2wx, &dsp->l2wx);
|
||||
writew(l2wy, &dsp->l2wy);
|
||||
writew(l2ww, &dsp->l2ww);
|
||||
writew(l2wh, &dsp->l2wh);
|
||||
|
||||
writel(dcm1 | (1 << 18) | (1 << 31), &dsp->dcm1);
|
||||
}
|
||||
|
||||
void *video_hw_init(void)
|
||||
{
|
||||
struct mb86r0x_gdc *gdc = (struct mb86r0x_gdc *) MB86R0x_GDC_BASE;
|
||||
GraphicDevice *pGD = &mb86r0x;
|
||||
char *s;
|
||||
u32 *vid;
|
||||
|
||||
memset(pGD, 0, sizeof(GraphicDevice));
|
||||
|
||||
pGD->gdfIndex = GDF_15BIT_555RGB;
|
||||
pGD->gdfBytesPP = 2;
|
||||
pGD->memSize = VIDEO_MEM_SIZE;
|
||||
pGD->frameAdrs = PHYS_SDRAM + PHYS_SDRAM_SIZE - VIDEO_MEM_SIZE;
|
||||
|
||||
vid = (u32 *)pGD->frameAdrs;
|
||||
|
||||
s = getenv("videomode");
|
||||
if (s != NULL)
|
||||
dsp_init(&gdc->dsp0, s, vid);
|
||||
|
||||
s = getenv("videomode1");
|
||||
if (s != NULL)
|
||||
dsp_init(&gdc->dsp1, s, vid);
|
||||
|
||||
return pGD;
|
||||
}
|
||||
|
|
@ -1,273 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2010
|
||||
* Matthias Weisser <weisserm@arcor.de>
|
||||
*
|
||||
* Configuation settings for the jadecpu board
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define CONFIG_MB86R0x
|
||||
#define CONFIG_MB86R0x_IOCLK get_bus_freq(0)
|
||||
#define CONFIG_SYS_TEXT_BASE 0x10000000
|
||||
|
||||
|
||||
#define CONFIG_USE_ARCH_MEMCPY
|
||||
#define CONFIG_USE_ARCH_MEMSET
|
||||
|
||||
#define MACH_TYPE_JADECPU 2636
|
||||
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_JADECPU
|
||||
|
||||
/*
|
||||
* Environment settings
|
||||
*/
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"gs_fast_boot=setenv bootdelay 5\0" \
|
||||
"gs_slow_boot=setenv bootdelay 10\0" \
|
||||
"bootcmd=dcache off; mw.l 0x40000000 0 1024; usb start;" \
|
||||
"fatls usb 0; fatload usb 0 0x40000000 jadecpu-init.bin;" \
|
||||
"bootelf 0x40000000\0" \
|
||||
""
|
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1
|
||||
#define CONFIG_INITRD_TAG 1
|
||||
#define CONFIG_BOARD_LATE_INIT
|
||||
|
||||
/*
|
||||
* Compressions
|
||||
*/
|
||||
#define CONFIG_LZO
|
||||
|
||||
/*
|
||||
* Hardware drivers
|
||||
*/
|
||||
|
||||
/*
|
||||
* Serial
|
||||
*/
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
|
||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
||||
#define CONFIG_SYS_NS16550_COM1 0xfffe1000 /* UART 0 */
|
||||
#define CONFIG_SYS_NS16550_COM2 0xfff50000 /* UART 2 */
|
||||
#define CONFIG_SYS_NS16550_COM3 0xfff51000 /* UART 3 */
|
||||
#define CONFIG_SYS_NS16550_COM4 0xfff43000 /* UART 4 */
|
||||
|
||||
#define CONFIG_CONS_INDEX 4
|
||||
|
||||
/*
|
||||
* Ethernet
|
||||
*/
|
||||
#define CONFIG_SMC911X
|
||||
#define CONFIG_SMC911X_BASE 0x02000000
|
||||
#define CONFIG_SMC911X_16_BIT
|
||||
|
||||
/*
|
||||
* Video
|
||||
*/
|
||||
#define CONFIG_VIDEO
|
||||
#define CONFIG_VIDEO_MB86R0xGDC
|
||||
#define CONFIG_SYS_WHITE_ON_BLACK
|
||||
#define CONFIG_CFB_CONSOLE
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
|
||||
#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
|
||||
#define CONFIG_VIDEO_LOGO
|
||||
#define CONFIG_SPLASH_SCREEN
|
||||
#define CONFIG_SPLASH_SCREEN_ALIGN
|
||||
#define CONFIG_VIDEO_BMP_LOGO
|
||||
#define CONFIG_VIDEO_BMP_GZIP
|
||||
#define CONFIG_VIDEO_BMP_RLE8
|
||||
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (800*480 + 256*4 + 10*1024)
|
||||
#define VIDEO_FB_16BPP_WORD_SWAP
|
||||
#define VIDEO_KBD_INIT_FCT 0
|
||||
#define VIDEO_TSTC_FCT serial_stub_tstc
|
||||
#define VIDEO_GETC_FCT serial_stub_getc
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE 1
|
||||
#define CONFIG_BOOTP_BOOTPATH 1
|
||||
#define CONFIG_BOOTP_GATEWAY 1
|
||||
#define CONFIG_BOOTP_HOSTNAME 1
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
#undef CONFIG_CMD_BDI
|
||||
#undef CONFIG_CMD_FPGA
|
||||
#undef CONFIG_CMD_IMLS
|
||||
#undef CONFIG_CMD_LOADS
|
||||
#undef CONFIG_CMD_SOURCE
|
||||
#undef CONFIG_CMD_NFS
|
||||
#undef CONFIG_CMD_XIMG
|
||||
|
||||
#define CONFIG_CMD_BMP
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_CMD_CACHE
|
||||
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
|
||||
/* USB */
|
||||
#define CONFIG_USB_OHCI_NEW
|
||||
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0xFFF81000
|
||||
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mb86r0x"
|
||||
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
/* SDRAM */
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM 0x40000000 /* Start address of DDRRAM */
|
||||
#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
|
||||
#define CONFIG_SYS_INIT_SP_ADDR 0x01008000
|
||||
|
||||
/*
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_BASE 0x10000000
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
||||
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
|
||||
#define CONFIG_ENV_SIZE (128 * 1024)
|
||||
|
||||
/*
|
||||
* CFI FLASH driver setup
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_CFI 1
|
||||
#define CONFIG_FLASH_CFI_DRIVER 1
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x40000000 /* load address */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM + (512*1024))
|
||||
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE)
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_SYS_PROMPT "jade> "
|
||||
#define CONFIG_SYS_CBSIZE 256
|
||||
#define CONFIG_SYS_MAXARGS 16
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
||||
sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_LONGHELP 1
|
||||
#define CONFIG_CMDLINE_EDITING 1
|
||||
|
||||
#define CONFIG_PREBOOT ""
|
||||
|
||||
#define CONFIG_BOOTDELAY 5
|
||||
#define CONFIG_AUTOBOOT_KEYED
|
||||
#define CONFIG_AUTOBOOT_PROMPT "boot in %d s\n", bootdelay
|
||||
#define CONFIG_AUTOBOOT_DELAY_STR "delaygs"
|
||||
#define CONFIG_AUTOBOOT_STOP_STR "stopgs"
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
#define CONFIG_SYS_MALLOC_LEN (10 << 20)
|
||||
#define CONFIG_SYS_MEM_TOP_HIDE (4 << 20)
|
||||
|
||||
/*
|
||||
* Clock reset generator init
|
||||
*/
|
||||
#define CONFIG_SYS_CRG_CRHA_INIT 0xffff
|
||||
#define CONFIG_SYS_CRG_CRPA_INIT 0xffff
|
||||
#define CONFIG_SYS_CRG_CRPB_INIT 0xfffe
|
||||
#define CONFIG_SYS_CRG_CRHB_INIT 0xffff
|
||||
#define CONFIG_SYS_CRG_CRAM_INIT 0xffef
|
||||
|
||||
/*
|
||||
* Memory controller settings
|
||||
*/
|
||||
#define CONFIG_SYS_MEMC_MCFMODE0_INIT 0x00000001 /* 16bit */
|
||||
#define CONFIG_SYS_MEMC_MCFMODE2_INIT 0x00000001 /* 16bit */
|
||||
#define CONFIG_SYS_MEMC_MCFMODE4_INIT 0x00000021 /* 16bit, Page*/
|
||||
#define CONFIG_SYS_MEMC_MCFTIM0_INIT 0x16191008
|
||||
#define CONFIG_SYS_MEMC_MCFTIM2_INIT 0x03061008
|
||||
#define CONFIG_SYS_MEMC_MCFTIM4_INIT 0x03061804
|
||||
#define CONFIG_SYS_MEMC_MCFAREA0_INIT 0x000000c0 /* 0x0c000000 1MB */
|
||||
#define CONFIG_SYS_MEMC_MCFAREA2_INIT 0x00000020 /* 0x02000000 1MB */
|
||||
#define CONFIG_SYS_MEMC_MCFAREA4_INIT 0x001f0000 /* 0x10000000 32 MB */
|
||||
|
||||
/*
|
||||
* DDR2 controller init settings
|
||||
*/
|
||||
#define CONFIG_SYS_DDR2_DRIMS_INIT 0x5555
|
||||
#define CONFIG_SYS_CCNT_CDCRC_INIT_1 0x00000002
|
||||
#define CONFIG_SYS_CCNT_CDCRC_INIT_2 0x00000003
|
||||
#define CONFIG_SYS_DDR2_DRIC1_INIT 0x003f
|
||||
#define CONFIG_SYS_DDR2_DRIC2_INIT 0x0000
|
||||
#define CONFIG_SYS_DDR2_DRCA_INIT 0xc124 /* 512Mbit DDR2SDRAM x 2 */
|
||||
#define CONFIG_SYS_DDR2_DRCM_INIT 0x0032
|
||||
#define CONFIG_SYS_DDR2_DRCST1_INIT 0x3418
|
||||
#define CONFIG_SYS_DDR2_DRCST2_INIT 0x6e32
|
||||
#define CONFIG_SYS_DDR2_DRCR_INIT 0x0141
|
||||
#define CONFIG_SYS_DDR2_DRCF_INIT 0x0002
|
||||
#define CONFIG_SYS_DDR2_DRASR_INIT 0x0001
|
||||
#define CONFIG_SYS_DDR2_DROBS_INIT 0x0001
|
||||
#define CONFIG_SYS_DDR2_DROABA_INIT 0x0103
|
||||
#define CONFIG_SYS_DDR2_DRIBSODT1_INIT 0x003F
|
||||
#define CONFIG_SYS_DDR2_DROS_INIT 0x0001
|
||||
|
||||
/*
|
||||
* DRAM init sequence
|
||||
*/
|
||||
|
||||
/* PALL Command */
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC1_1 0x0017
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC2_1 0x0400
|
||||
|
||||
/* EMR(2) command */
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC1_2 0x0006
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC2_2 0x0000
|
||||
|
||||
/* EMR(3) command */
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC1_3 0x0007
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC2_3 0x0000
|
||||
|
||||
/* EMR(1) command */
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC1_4 0x0005
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC2_4 0x0000
|
||||
|
||||
/* MRS command */
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC1_5 0x0004
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC2_5 0x0532
|
||||
|
||||
/* PALL command */
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC1_6 0x0017
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC2_6 0x0400
|
||||
|
||||
/* REF command 1 */
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC1_7 0x000f
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC2_7 0x0000
|
||||
|
||||
/* MRS command */
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC1_8 0x0004
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC2_8 0x0432
|
||||
|
||||
/* EMR(1) command */
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC1_9 0x0005
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC2_9 0x0380
|
||||
|
||||
/* EMR(1) command */
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC1_10 0x0005
|
||||
#define CONFIG_SYS_DDR2_INIT_DRIC2_10 0x0002
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -29,7 +29,7 @@ extern struct serial_device *default_serial_console(void);
|
|||
#if defined(CONFIG_405GP) || \
|
||||
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
|
||||
defined(CONFIG_405EX) || defined(CONFIG_440) || \
|
||||
defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) || \
|
||||
defined(CONFIG_MPC5xxx) || \
|
||||
defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
|
||||
defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) || \
|
||||
defined(CONFIG_TEGRA) || defined(CONFIG_SYS_COREBOOT) || \
|
||||
|
|
|
|||
Loading…
Reference in New Issue