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add new CONFIG_AT91_LEGACY

* add's the new temporary CONFIG_AT91_LEGACY to all board configs
 This will need for backward compatiblity, while change the SoC access
 to c structures. If CONFIG_AT91_LEGACY is defined, the deprecated
 SoC is used.

Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
utp
Jens Scharsig 2010-02-03 22:45:42 +01:00 committed by Tom Rix
parent 3a4e43921d
commit 425de62d40
22 changed files with 83 additions and 0 deletions

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@ -0,0 +1,41 @@
New C structure AT91 SoC access
=================================
The goal
--------
Currently the at91 arch uses hundreds of address defines and special
at91_xxxx_write/read functions to access the SOC.
The u-boot project perferred method is to access memory mapped hw
regisister via a c structure.
e.g. old
*AT91C_PIOA_IDR = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK;
*AT91C_PIOC_PUDR = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK;
*AT91C_PIOC_PER = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK;
*AT91C_PIOC_OER = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK;
*AT91C_PIOC_PIO = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK;
at91_sys_write(AT91_RSTC_CR,
AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
e.g new
pin = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK;
writel(pin, &pio->pioa.idr);
writel(pin, &pio->pioa.pudr);
writel(pin, &pio->pioa.per);
writel(pin, &pio->pioa.oer);
writel(pin, &pio->pioa.sodr);
writel(AT91_RSTC_KEY | AT91_RSTC_CR_PROCRST |
AT91_RSTC_CR_PERRST, &rstc->cr);
The method for updating
------------------------
1. add's the temporary CONFIG_AT91_LEGACY to all at91 board configs
2. Display a compile time warning, if the board has not been converted
3. add new structures for SoC access
4. Convert arch, driver and boards file to new SoC
5. remove legacy code, if all boards and drives are ready

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@ -26,6 +26,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_AT91_LEGACY
/* ARM asynchronous clock */
#define AT91_MAIN_CLOCK 18429952 /* from 18.432 MHz crystal */
#define CONFIG_SYS_HZ 1000

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@ -27,6 +27,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_AT91_LEGACY
/* ARM asynchronous clock */
#define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
#define CONFIG_SYS_HZ 1000

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@ -25,6 +25,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_AT91_LEGACY
/* ARM asynchronous clock */
#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
#define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */

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@ -26,6 +26,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_AT91_LEGACY
/* ARM asynchronous clock */
/*
* from 18.432 MHz crystal

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@ -27,6 +27,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_AT91_LEGACY
/* ARM asynchronous clock */
#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
#define CONFIG_SYS_HZ 1000

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@ -27,6 +27,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_AT91_LEGACY
/* ARM asynchronous clock */
#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
#define CONFIG_SYS_HZ 1000

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@ -27,6 +27,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_AT91_LEGACY
/* ARM asynchronous clock */
#define AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
#define CONFIG_SYS_HZ 1000

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@ -27,6 +27,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_AT91_LEGACY
/* ARM asynchronous clock */
#define AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
#define CONFIG_SYS_HZ 1000

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@ -27,6 +27,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_AT91_LEGACY
/* ARM asynchronous clock */
#define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
#define CONFIG_SYS_HZ 1000

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@ -25,6 +25,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_AT91_LEGACY
/* ARM asynchronous clock */
#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK/3) /* peripheral clock */

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@ -31,6 +31,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_AT91_LEGACY
#define CONFIG_DISPLAY_CPUINFO 1
#define AT91_MAIN_CLOCK 18432000

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@ -26,6 +26,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_AT91_LEGACY
#ifdef CONFIG_CPUAT91_RAM
#define CONFIG_SKIP_LOWLEVEL_INIT 1
#define CONFIG_SKIP_RELOCATE_UBOOT 1

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@ -26,6 +26,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_AT91_LEGACY
/* ARM asynchronous clock */
#define AT91C_MAIN_CLOCK 184320000 /* from 3.6864 MHz crystal (3686400 * 50) */
#define AT91C_MASTER_CLOCK 46080000 /* (AT91C_MAIN_CLOCK/4) peripheral clock */

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@ -29,6 +29,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_AT91_LEGACY
/* ARM asynchronous clock */
#define AT91C_MAIN_CLOCK 180000000 /* from 10 MHz crystal */
#define AT91C_MASTER_CLOCK 60000000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */

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@ -27,6 +27,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_AT91_LEGACY
/* ARM asynchronous clock */
/* from 18.432 MHz crystal (18432000 / 4 * 39) */
#define AT91C_MAIN_CLOCK 179712000

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@ -31,6 +31,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_AT91_LEGACY
/* Common stuff */
#define CONFIG_SYS_HZ 1000 /* decrementer freq */
#define CONFIG_MEESC 1 /* Board is esd MEESC */

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@ -28,6 +28,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_AT91_LEGACY
/* ARM asynchronous clock */
#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 45) */
#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK/3) /* peripheral clock */

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@ -28,6 +28,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_AT91_LEGACY
/* ARM asynchronous clock */
#define AT91_CPU_NAME "AT91SAM9261"

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@ -28,6 +28,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_AT91_LEGACY
/* ARM asynchronous clock */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

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@ -26,6 +26,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_AT91_LEGACY
#if defined(CONFIG_SBC35_A9G20_NANDFLASH) || defined(CONFIG_SBC35_A9G20_EEPROM)
#define CONFIG_SBC35_A9G20
#endif

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@ -30,6 +30,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_AT91_LEGACY
#if defined(CONFIG_TNY_A9260_NANDFLASH) || defined(CONFIG_TNY_A9260_EEPROM)
#define CONFIG_TNY_A9260
#elif defined(CONFIG_TNY_A9G20_NANDFLASH) || defined(CONFIG_TNY_A9G20_EEPROM)