x86: Add register dump to crash handlers
Shamelessly steal the Linux x86 crash handling code and shove it into U-Boot (cool - it fits). Be sure to include suitable attribution to Linus Signed-off-by: Graeme Russ <graeme.russ@gmail.com>utp
Graeme Russ
Wolfgang Denk
parent
64a0a4995e
commit
433ff2bdbc
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@ -5,6 +5,9 @@
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* (C) Copyright 2002
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* Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
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*
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* Portions of this file are derived from the Linux kernel source
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* Copyright (C) 1991, 1992 Linus Torvalds
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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@ -32,12 +35,112 @@
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".hidden irq_"#x"\n" \
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".type irq_"#x", @function\n" \
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"irq_"#x":\n" \
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"pushl %ebp\n" \
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"movl %esp,%ebp\n" \
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"pusha\n" \
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"pushl $"#x"\n" \
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"jmp irq_common_entry\n"
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/*
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* Volatile isn't enough to prevent the compiler from reordering the
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* read/write functions for the control registers and messing everything up.
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* A memory clobber would solve the problem, but would prevent reordering of
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* all loads stores around it, which can hurt performance. Solution is to
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* use a variable and mimic reads and writes to it to enforce serialization
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*/
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static unsigned long __force_order;
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static inline unsigned long read_cr0(void)
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{
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unsigned long val;
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asm volatile("mov %%cr0,%0\n\t" : "=r" (val), "=m" (__force_order));
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return val;
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}
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static inline unsigned long read_cr2(void)
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{
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unsigned long val;
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asm volatile("mov %%cr2,%0\n\t" : "=r" (val), "=m" (__force_order));
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return val;
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}
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static inline unsigned long read_cr3(void)
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{
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unsigned long val;
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asm volatile("mov %%cr3,%0\n\t" : "=r" (val), "=m" (__force_order));
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return val;
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}
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static inline unsigned long read_cr4(void)
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{
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unsigned long val;
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asm volatile("mov %%cr4,%0\n\t" : "=r" (val), "=m" (__force_order));
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return val;
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}
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static inline unsigned long get_debugreg(int regno)
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{
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unsigned long val = 0; /* Damn you, gcc! */
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switch (regno) {
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case 0:
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asm("mov %%db0, %0" :"=r" (val));
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break;
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case 1:
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asm("mov %%db1, %0" :"=r" (val));
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break;
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case 2:
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asm("mov %%db2, %0" :"=r" (val));
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break;
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case 3:
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asm("mov %%db3, %0" :"=r" (val));
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break;
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case 6:
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asm("mov %%db6, %0" :"=r" (val));
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break;
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case 7:
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asm("mov %%db7, %0" :"=r" (val));
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break;
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default:
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val = 0;
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}
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return val;
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}
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void dump_regs(struct pt_regs *regs)
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{
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unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
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unsigned long d0, d1, d2, d3, d6, d7;
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printf("EIP: %04x:[<%08lx>] EFLAGS: %08lx\n",
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(u16)regs->xcs, regs->eip, regs->eflags);
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printf("EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
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regs->eax, regs->ebx, regs->ecx, regs->edx);
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printf("ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
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regs->esi, regs->edi, regs->ebp, regs->esp);
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printf(" DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n",
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(u16)regs->xds, (u16)regs->xes, (u16)regs->xfs, (u16)regs->xgs, (u16)regs->xss);
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cr0 = read_cr0();
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cr2 = read_cr2();
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cr3 = read_cr3();
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cr4 = read_cr4();
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printf("CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n",
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cr0, cr2, cr3, cr4);
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d0 = get_debugreg(0);
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d1 = get_debugreg(1);
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d2 = get_debugreg(2);
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d3 = get_debugreg(3);
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printf("DR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
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d0, d1, d2, d3);
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d6 = get_debugreg(6);
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d7 = get_debugreg(7);
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printf("DR6: %08lx DR7: %08lx\n",
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d6, d7);
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}
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struct idt_entry {
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u16 base_low;
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u16 selector;
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@ -122,7 +225,7 @@ int disable_interrupts(void)
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}
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/* IRQ Low-Level Service Routine */
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__isr__ irq_llsr(int ip, int seg, int irq)
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__isr__ irq_llsr(struct pt_regs *regs)
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{
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/*
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* For detailed description of each exception, refer to:
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@ -131,73 +234,92 @@ __isr__ irq_llsr(int ip, int seg, int irq)
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* Order Number: 253665-029US, November 2008
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* Table 6-1. Exceptions and Interrupts
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*/
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switch (irq) {
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switch (regs->orig_eax) {
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case 0x00:
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printf("Divide Error (Division by zero) at %04x:%08x\n", seg, ip);
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printf("Divide Error (Division by zero)\n");
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dump_regs(regs);
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while(1);
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break;
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case 0x01:
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printf("Debug Interrupt (Single step) at %04x:%08x\n", seg, ip);
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printf("Debug Interrupt (Single step)\n");
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dump_regs(regs);
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break;
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case 0x02:
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printf("NMI Interrupt at %04x:%08x\n", seg, ip);
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printf("NMI Interrupt\n");
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dump_regs(regs);
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break;
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case 0x03:
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printf("Breakpoint at %04x:%08x\n", seg, ip);
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printf("Breakpoint\n");
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dump_regs(regs);
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break;
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case 0x04:
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printf("Overflow at %04x:%08x\n", seg, ip);
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printf("Overflow\n");
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dump_regs(regs);
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while(1);
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break;
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case 0x05:
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printf("BOUND Range Exceeded at %04x:%08x\n", seg, ip);
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printf("BOUND Range Exceeded\n");
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dump_regs(regs);
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while(1);
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break;
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case 0x06:
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printf("Invalid Opcode (UnDefined Opcode) at %04x:%08x\n", seg, ip);
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printf("Invalid Opcode (UnDefined Opcode)\n");
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dump_regs(regs);
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while(1);
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break;
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case 0x07:
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printf("Device Not Available (No Math Coprocessor) at %04x:%08x\n", seg, ip);
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printf("Device Not Available (No Math Coprocessor)\n");
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dump_regs(regs);
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while(1);
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break;
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case 0x08:
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printf("Double fault at %04x:%08x\n", seg, ip);
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printf("Double fault\n");
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dump_regs(regs);
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while(1);
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break;
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case 0x09:
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printf("Co-processor segment overrun at %04x:%08x\n", seg, ip);
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printf("Co-processor segment overrun\n");
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dump_regs(regs);
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while(1);
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break;
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case 0x0a:
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printf("Invalid TSS at %04x:%08x\n", seg, ip);
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printf("Invalid TSS\n");
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dump_regs(regs);
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break;
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case 0x0b:
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printf("Segment Not Present at %04x:%08x\n", seg, ip);
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printf("Segment Not Present\n");
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dump_regs(regs);
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while(1);
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break;
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case 0x0c:
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printf("Stack Segment Fault at %04x:%08x\n", seg, ip);
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printf("Stack Segment Fault\n");
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dump_regs(regs);
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while(1);
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break;
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case 0x0d:
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printf("General Protection at %04x:%08x\n", seg, ip);
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printf("General Protection\n");
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dump_regs(regs);
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break;
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case 0x0e:
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printf("Page fault at %04x:%08x\n", seg, ip);
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printf("Page fault\n");
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dump_regs(regs);
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while(1);
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break;
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case 0x0f:
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printf("Floating-Point Error (Math Fault) at %04x:%08x\n", seg, ip);
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printf("Floating-Point Error (Math Fault)\n");
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dump_regs(regs);
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break;
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case 0x10:
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printf("Alignment check at %04x:%08x\n", seg, ip);
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printf("Alignment check\n");
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dump_regs(regs);
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break;
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case 0x11:
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printf("Machine Check at %04x:%08x\n", seg, ip);
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printf("Machine Check\n");
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dump_regs(regs);
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break;
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case 0x12:
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printf("SIMD Floating-Point Exception at %04x:%08x\n", seg, ip);
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printf("SIMD Floating-Point Exception\n");
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dump_regs(regs);
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break;
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case 0x13:
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case 0x14:
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@ -212,12 +334,13 @@ __isr__ irq_llsr(int ip, int seg, int irq)
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case 0x1d:
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case 0x1e:
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case 0x1f:
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printf("Reserved Exception %d at %04x:%08x\n", irq, seg, ip);
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printf("Reserved Exception\n");
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dump_regs(regs);
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break;
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default:
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/* Hardware or User IRQ */
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do_irq(irq);
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do_irq(regs->orig_eax);
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}
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}
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@ -226,22 +349,45 @@ __isr__ irq_llsr(int ip, int seg, int irq)
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* fully relocatable code.
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* - The call to irq_llsr will be a relative jump
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* - The IRQ entries will be guaranteed to be in order
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* It's a bit annoying that we need to waste 3 bytes per interrupt entry
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* (total of 768 code bytes), but we MUST create a Stack Frame and this is
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* the easiest way I could do it. Maybe it can be made better later.
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* Interrupt entries are now very small (a push and a jump) but they are
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* now slower (all registers pushed on stack which provides complete
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* crash dumps in the low level handlers
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*/
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asm(".globl irq_common_entry\n" \
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".hidden irq_common_entry\n" \
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".type irq_common_entry, @function\n" \
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"irq_common_entry:\n" \
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"pushl $0\n" \
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"pushl $0\n" \
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"cld\n" \
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"pushl %gs\n" \
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"pushl %fs\n" \
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"pushl %es\n" \
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"pushl %ds\n" \
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"pushl %eax\n" \
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"pushl %ebp\n" \
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"pushl %edi\n" \
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"pushl %esi\n" \
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"pushl %edx\n" \
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"pushl %ecx\n" \
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"pushl %ebx\n" \
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"mov %esp, %eax\n" \
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"pushl %ebp\n" \
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"movl %esp,%ebp\n" \
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"pushl %eax\n" \
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"call irq_llsr\n" \
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"popl %eax\n" \
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"popl %eax\n" \
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"popl %eax\n" \
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"popa\n" \
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"leave\n"\
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"popl %ebx\n" \
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"popl %ecx\n" \
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"popl %edx\n" \
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"popl %esi\n" \
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"popl %edi\n" \
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"popl %ebp\n" \
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"popl %eax\n" \
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"popl %ds\n" \
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"popl %es\n" \
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"popl %fs\n" \
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"popl %gs\n" \
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"add $4, %esp\n" \
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"iret\n" \
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DECLARE_INTERRUPT(0) \
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DECLARE_INTERRUPT(1) \
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