Merge branch 'master' of git://www.denx.de/git/u-boot-imx
Tom Rini
commit
45043cf804
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@ -612,6 +612,7 @@ config TARGET_MX6QSABREAUTO
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config TARGET_MX6SABRESD
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bool "Support mx6sabresd"
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select CPU_V7
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select SUPPORT_SPL
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config TARGET_MX6SLEVK
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bool "Support mx6slevk"
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@ -635,6 +636,9 @@ config TARGET_KOSAGI_NOVENA
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select CPU_V7
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select SUPPORT_SPL
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config TARGET_TBS2910
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bool "Support tbs2910"
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config TARGET_TQMA6
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bool "TQ Systems TQMa6 board"
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select CPU_V7
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@ -936,6 +940,7 @@ source "board/sunxi/Kconfig"
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source "board/syteco/jadecpu/Kconfig"
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source "board/syteco/zmx25/Kconfig"
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source "board/taskit/stamp9g20/Kconfig"
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source "board/tbs/tbs2910/Kconfig"
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source "board/ti/am335x/Kconfig"
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source "board/ti/am43xx/Kconfig"
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source "board/ti/ti814x/Kconfig"
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@ -350,8 +350,8 @@ void boot_mode_apply(unsigned cfg_val)
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/*
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* cfg_val will be used for
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* Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
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* After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
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* to SBMR1, which will determine the boot device.
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* After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
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* instead of SBMR1 to determine the boot device.
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*/
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const struct boot_mode soc_boot_modes[] = {
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{"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
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@ -14,11 +14,12 @@
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#include <spl.h>
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#if defined(CONFIG_MX6)
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/* determine boot device from SRC_SBMR1 register (BOOT_CFG[4:1]) */
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/* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 register */
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u32 spl_boot_device(void)
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{
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struct src *psrc = (struct src *)SRC_BASE_ADDR;
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unsigned reg = readl(&psrc->sbmr1);
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unsigned int gpr10_boot = readl(&psrc->gpr10) & (1 << 28);
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unsigned reg = gpr10_boot ? readl(&psrc->gpr9) : readl(&psrc->sbmr1);
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/* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */
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switch ((reg & 0x000000FF) >> 4) {
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@ -11,6 +11,7 @@ int board_video_skip(void)
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int i;
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int ret;
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char const *panel = getenv("panel");
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if (!panel) {
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for (i = 0; i < display_count; i++) {
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struct display_info_t const *dev = displays+i;
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@ -31,11 +32,14 @@ int board_video_skip(void)
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break;
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}
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}
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if (i < display_count) {
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ret = ipuv3_fb_init(&displays[i].mode, 0,
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displays[i].pixfmt);
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if (!ret) {
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displays[i].enable(displays+i);
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if (displays[i].enable)
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displays[i].enable(displays + i);
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printf("Display: %s (%ux%u)\n",
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displays[i].mode.name,
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displays[i].mode.xres,
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@ -159,8 +159,8 @@ int board_mmc_getcd(struct mmc *mmc)
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gpio_direction_input(IMX_GPIO_NR(4, 5));
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ret = gpio_get_value(IMX_GPIO_NR(4, 5));
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} else {
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gpio_direction_input(IMX_GPIO_NR(1, 4));
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ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
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gpio_direction_input(IMX_GPIO_NR(1, 5));
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ret = !gpio_get_value(IMX_GPIO_NR(1, 5));
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}
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return ret;
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@ -1,7 +1,7 @@
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FREESCALE MX28EVK
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==================
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Supported hardware: only MX28EVK rev D is supported in U-boot.
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Supported hardware: MX28EVK rev C and D are supported in U-boot.
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Files of the MX28EVK port
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--------------------------
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@ -242,6 +242,8 @@ static int power_init(void)
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if (!p)
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return -ENODEV;
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setenv("fdt_file", "imx53-qsb.dtb");
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/* Set VDDA to 1.25V */
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val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
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ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
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@ -283,6 +285,8 @@ static int power_init(void)
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if (!p)
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return -ENODEV;
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setenv("fdt_file", "imx53-qsrb.dtb");
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/* Set VDDGP to 1.25V for 1GHz on SW1 */
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pmic_reg_read(p, REG_SW_0, &val);
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val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708;
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@ -46,6 +46,11 @@ DECLARE_GLOBAL_DATA_PTR;
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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PAD_CTL_ODE | PAD_CTL_SRE_FAST)
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#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
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#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
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PAD_CTL_SRE_FAST)
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#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
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int dram_init(void)
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@ -200,6 +205,63 @@ int board_mmc_init(bd_t *bis)
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}
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#endif
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#ifdef CONFIG_NAND_MXS
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static iomux_v3_cfg_t gpmi_pads[] = {
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MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0),
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MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
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MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL1),
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};
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static void setup_gpmi_nand(void)
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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/* config gpmi nand iomux */
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imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
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/* gate ENFC_CLK_ROOT clock first,before clk source switch */
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clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
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clrbits_le32(&mxc_ccm->CCGR4,
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
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/* config gpmi and bch clock to 100 MHz */
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clrsetbits_le32(&mxc_ccm->cs2cdr,
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MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
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MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
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MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
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MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
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MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
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MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
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/* enable ENFC_CLK_ROOT clock */
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setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
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/* enable gpmi and bch clock gating */
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setbits_le32(&mxc_ccm->CCGR4,
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MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
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MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
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/* enable apbh clock gating */
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setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
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}
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#endif
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int mx6_rgmii_rework(struct phy_device *phydev)
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{
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unsigned short val;
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@ -336,6 +398,10 @@ int board_early_init_f(void)
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#ifdef CONFIG_VIDEO_IPUV3
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setup_display();
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#endif
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#ifdef CONFIG_NAND_MXS
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setup_gpmi_nand();
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#endif
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return 0;
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}
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@ -27,8 +27,12 @@
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#include <i2c.h>
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#include <power/pmic.h>
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#include <power/pfuze100_pmic.h>
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#include <asm/arch/mx6-ddr.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define BOOT_CFG 0x020D8004
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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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@ -55,17 +59,16 @@ DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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iomux_v3_cfg_t const uart1_pads[] = {
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static iomux_v3_cfg_t const uart1_pads[] = {
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MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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iomux_v3_cfg_t const enet_pads[] = {
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static iomux_v3_cfg_t const enet_pads[] = {
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MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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@ -95,7 +98,7 @@ static void setup_iomux_enet(void)
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gpio_set_value(IMX_GPIO_NR(1, 25), 1);
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}
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iomux_v3_cfg_t const usdhc2_pads[] = {
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static iomux_v3_cfg_t const usdhc2_pads[] = {
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MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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@ -109,7 +112,7 @@ iomux_v3_cfg_t const usdhc2_pads[] = {
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MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
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};
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iomux_v3_cfg_t const usdhc3_pads[] = {
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static iomux_v3_cfg_t const usdhc3_pads[] = {
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MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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@ -123,7 +126,7 @@ iomux_v3_cfg_t const usdhc3_pads[] = {
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MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
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};
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iomux_v3_cfg_t const usdhc4_pads[] = {
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static iomux_v3_cfg_t const usdhc4_pads[] = {
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MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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@ -136,7 +139,7 @@ iomux_v3_cfg_t const usdhc4_pads[] = {
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MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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};
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iomux_v3_cfg_t const ecspi1_pads[] = {
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static iomux_v3_cfg_t const ecspi1_pads[] = {
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MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
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MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
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MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
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@ -253,7 +256,8 @@ int board_mmc_getcd(struct mmc *mmc)
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int board_mmc_init(bd_t *bis)
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{
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s32 status = 0;
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#ifndef CONFIG_SPL_BUILD
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int ret;
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int i;
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/*
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@ -286,13 +290,52 @@ int board_mmc_init(bd_t *bis)
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printf("Warning: you configured more USDHC controllers"
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"(%d) then supported by the board (%d)\n",
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i + 1, CONFIG_SYS_FSL_USDHC_NUM);
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return status;
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return -EINVAL;
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}
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status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
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ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
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if (ret)
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return ret;
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}
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return status;
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return 0;
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#else
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unsigned reg = readl(BOOT_CFG) >> 11;
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/*
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* Upon reading BOOT_CFG register the following map is done:
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* Bit 11 and 12 of BOOT_CFG register can determine the current
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* mmc port
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* 0x1 SD1
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* 0x2 SD2
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* 0x3 SD4
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*/
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switch (reg & 0x3) {
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case 0x1:
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imx_iomux_v3_setup_multiple_pads(
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usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
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usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
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gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
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break;
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case 0x2:
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imx_iomux_v3_setup_multiple_pads(
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usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
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usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
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break;
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case 0x3:
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imx_iomux_v3_setup_multiple_pads(
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usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
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usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
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gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
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break;
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}
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return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
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#endif
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}
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#endif
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@ -607,3 +650,144 @@ int checkboard(void)
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puts("Board: MX6-SabreSD\n");
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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#include <spl.h>
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#include <libfdt.h>
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const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
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.dram_sdclk_0 = 0x00020030,
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.dram_sdclk_1 = 0x00020030,
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.dram_cas = 0x00020030,
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.dram_ras = 0x00020030,
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.dram_reset = 0x00020030,
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.dram_sdcke0 = 0x00003000,
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.dram_sdcke1 = 0x00003000,
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.dram_sdba2 = 0x00000000,
|
||||
.dram_sdodt0 = 0x00003030,
|
||||
.dram_sdodt1 = 0x00003030,
|
||||
.dram_sdqs0 = 0x00000030,
|
||||
.dram_sdqs1 = 0x00000030,
|
||||
.dram_sdqs2 = 0x00000030,
|
||||
.dram_sdqs3 = 0x00000030,
|
||||
.dram_sdqs4 = 0x00000030,
|
||||
.dram_sdqs5 = 0x00000030,
|
||||
.dram_sdqs6 = 0x00000030,
|
||||
.dram_sdqs7 = 0x00000030,
|
||||
.dram_dqm0 = 0x00020030,
|
||||
.dram_dqm1 = 0x00020030,
|
||||
.dram_dqm2 = 0x00020030,
|
||||
.dram_dqm3 = 0x00020030,
|
||||
.dram_dqm4 = 0x00020030,
|
||||
.dram_dqm5 = 0x00020030,
|
||||
.dram_dqm6 = 0x00020030,
|
||||
.dram_dqm7 = 0x00020030,
|
||||
};
|
||||
|
||||
const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
|
||||
.grp_ddr_type = 0x000C0000,
|
||||
.grp_ddrmode_ctl = 0x00020000,
|
||||
.grp_ddrpke = 0x00000000,
|
||||
.grp_addds = 0x00000030,
|
||||
.grp_ctlds = 0x00000030,
|
||||
.grp_ddrmode = 0x00020000,
|
||||
.grp_b0ds = 0x00000030,
|
||||
.grp_b1ds = 0x00000030,
|
||||
.grp_b2ds = 0x00000030,
|
||||
.grp_b3ds = 0x00000030,
|
||||
.grp_b4ds = 0x00000030,
|
||||
.grp_b5ds = 0x00000030,
|
||||
.grp_b6ds = 0x00000030,
|
||||
.grp_b7ds = 0x00000030,
|
||||
};
|
||||
|
||||
const struct mx6_mmdc_calibration mx6_mmcd_calib = {
|
||||
.p0_mpwldectrl0 = 0x001F001F,
|
||||
.p0_mpwldectrl1 = 0x001F001F,
|
||||
.p1_mpwldectrl0 = 0x00440044,
|
||||
.p1_mpwldectrl1 = 0x00440044,
|
||||
.p0_mpdgctrl0 = 0x434B0350,
|
||||
.p0_mpdgctrl1 = 0x034C0359,
|
||||
.p1_mpdgctrl0 = 0x434B0350,
|
||||
.p1_mpdgctrl1 = 0x03650348,
|
||||
.p0_mprddlctl = 0x4436383B,
|
||||
.p1_mprddlctl = 0x39393341,
|
||||
.p0_mpwrdlctl = 0x35373933,
|
||||
.p1_mpwrdlctl = 0x48254A36,
|
||||
};
|
||||
|
||||
static struct mx6_ddr3_cfg mem_ddr = {
|
||||
.mem_speed = 1600,
|
||||
.density = 4,
|
||||
.width = 64,
|
||||
.banks = 8,
|
||||
.rowaddr = 14,
|
||||
.coladdr = 10,
|
||||
.pagesz = 2,
|
||||
.trcd = 1375,
|
||||
.trcmin = 4875,
|
||||
.trasmin = 3500,
|
||||
};
|
||||
|
||||
/*
|
||||
* This section require the differentiation
|
||||
* between iMX6 Sabre Families.
|
||||
* But for now, it will configure only for
|
||||
* SabreSD.
|
||||
*/
|
||||
static void spl_dram_init(void)
|
||||
{
|
||||
struct mx6_ddr_sysinfo sysinfo = {
|
||||
/* width of data bus:0=16,1=32,2=64 */
|
||||
.dsize = mem_ddr.width/32,
|
||||
/* config for full 4GB range so that get_mem_size() works */
|
||||
.cs_density = 32, /* 32Gb per CS */
|
||||
/* single chip select */
|
||||
.ncs = 1,
|
||||
.cs1_mirror = 0,
|
||||
.rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
|
||||
#ifdef RTT_NOM_120OHM
|
||||
.rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
|
||||
#else
|
||||
.rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
|
||||
#endif
|
||||
.walat = 1, /* Write additional latency */
|
||||
.ralat = 5, /* Read additional latency */
|
||||
.mif3_mode = 3, /* Command prediction working mode */
|
||||
.bi_on = 1, /* Bank interleaving enabled */
|
||||
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
|
||||
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
|
||||
};
|
||||
|
||||
mx6dq_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
|
||||
mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
|
||||
}
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
/* setup AIPS and disable watchdog */
|
||||
arch_cpu_init();
|
||||
|
||||
/* iomux and setup of i2c */
|
||||
board_early_init_f();
|
||||
|
||||
/* setup GP timer */
|
||||
timer_init();
|
||||
|
||||
/* UART clocks enabled and gd valid - init serial console */
|
||||
preloader_console_init();
|
||||
|
||||
/* DDR initialization */
|
||||
spl_dram_init();
|
||||
|
||||
/* Clear the BSS. */
|
||||
memset(__bss_start, 0, __bss_end - __bss_start);
|
||||
|
||||
/* load/boot image from boot device */
|
||||
board_init_r(NULL, 0);
|
||||
}
|
||||
|
||||
void reset_cpu(ulong addr)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,58 @@
|
|||
/*
|
||||
* Copyright (C) 2011 Freescale Semiconductor, Inc.
|
||||
* Jason Liu <r64343@freescale.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* Refer doc/README.imximage for more details about how-to configure
|
||||
* and create imximage boot image
|
||||
*
|
||||
* The syntax is taken as close as possible with the kwbimage
|
||||
*/
|
||||
|
||||
/* image version */
|
||||
IMAGE_VERSION 2
|
||||
|
||||
/*
|
||||
* Boot Device : one of
|
||||
* spi, sd (the board has no nand neither onenand)
|
||||
*/
|
||||
BOOT_FROM sd
|
||||
|
||||
/*
|
||||
* Device Configuration Data (DCD)
|
||||
*
|
||||
* Each entry must have the format:
|
||||
* Addr-type Address Value
|
||||
*
|
||||
* where:
|
||||
* Addr-type register length (1,2 or 4 bytes)
|
||||
* Address absolute address of the register
|
||||
* value value to be stored in the register
|
||||
*/
|
||||
|
||||
/* set the default clock gate to save power */
|
||||
DATA 4 0x020c4068 0x00C03F3F
|
||||
DATA 4 0x020c406c 0x0030FC03
|
||||
DATA 4 0x020c4070 0x0FFFC000
|
||||
DATA 4 0x020c4074 0x3FF00000
|
||||
DATA 4 0x020c4078 0x00FFF300
|
||||
DATA 4 0x020c407c 0x0F0000C3
|
||||
DATA 4 0x020c4080 0x000003FF
|
||||
|
||||
/* enable AXI cache for VDOA/VPU/IPU */
|
||||
DATA 4 0x020e0010 0xF00000CF
|
||||
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
|
||||
DATA 4 0x020e0018 0x007F007F
|
||||
DATA 4 0x020e001c 0x007F007F
|
||||
|
||||
/*
|
||||
* Setup CCM_CCOSR register as follows:
|
||||
*
|
||||
* cko1_en = 1 --> CKO1 enabled
|
||||
* cko1_div = 111 --> divide by 8
|
||||
* cko1_sel = 1011 --> ahb_clk_root
|
||||
*
|
||||
* This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
|
||||
*/
|
||||
DATA 4 0x020c4060 0x000000fb
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
if TARGET_TBS2910
|
||||
|
||||
config SYS_CPU
|
||||
string
|
||||
default "armv7"
|
||||
|
||||
config SYS_BOARD
|
||||
string
|
||||
default "tbs2910"
|
||||
|
||||
config SYS_VENDOR
|
||||
string
|
||||
default "tbs"
|
||||
|
||||
config SYS_SOC
|
||||
string
|
||||
default "mx6"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
string
|
||||
default "tbs2910"
|
||||
|
||||
endif
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
TBS2910 BOARD
|
||||
M: Soeren Moch <smoch@web.de>
|
||||
S: Maintained
|
||||
F: board/tbs/tbs2910/
|
||||
F: configs/tbs2910_defconfig
|
||||
F: include/configs/tbs2910.h
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
#
|
||||
# Copyright (C) 2014 Soeren Moch <smoch@web.de>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y := tbs2910.o
|
||||
|
|
@ -0,0 +1,398 @@
|
|||
/*
|
||||
* Copyright (C) 2014 Soeren Moch <smoch@web.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <asm/arch/mx6-pins.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/imx-common/mxc_i2c.h>
|
||||
#include <asm/imx-common/iomux-v3.h>
|
||||
#include <asm/imx-common/sata.h>
|
||||
#include <asm/imx-common/boot_mode.h>
|
||||
#include <asm/imx-common/video.h>
|
||||
#include <mmc.h>
|
||||
#include <fsl_esdhc.h>
|
||||
#include <miiphy.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/arch/mxc_hdmi.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <i2c.h>
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define WEAK_PULLUP (PAD_CTL_PUS_47K_UP | \
|
||||
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
|
||||
PAD_CTL_SRE_SLOW)
|
||||
|
||||
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
|
||||
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
|
||||
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||
|
||||
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
|
||||
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
|
||||
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||
|
||||
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
|
||||
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
|
||||
|
||||
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
|
||||
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
|
||||
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
|
||||
|
||||
#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
|
||||
|
||||
#ifdef CONFIG_SYS_I2C
|
||||
/* I2C1, SGTL5000 */
|
||||
static struct i2c_pads_info i2c_pad_info0 = {
|
||||
.scl = {
|
||||
.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
|
||||
.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
|
||||
.gp = IMX_GPIO_NR(5, 27)
|
||||
},
|
||||
.sda = {
|
||||
.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
|
||||
.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
|
||||
.gp = IMX_GPIO_NR(5, 26)
|
||||
}
|
||||
};
|
||||
|
||||
/* I2C2 HDMI */
|
||||
static struct i2c_pads_info i2c_pad_info1 = {
|
||||
.scl = {
|
||||
.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
|
||||
.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
|
||||
.gp = IMX_GPIO_NR(4, 12)
|
||||
},
|
||||
.sda = {
|
||||
.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
|
||||
.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
|
||||
.gp = IMX_GPIO_NR(4, 13)
|
||||
}
|
||||
};
|
||||
|
||||
/* I2C3, CON11, DS1307, PCIe_SMB */
|
||||
static struct i2c_pads_info i2c_pad_info2 = {
|
||||
.scl = {
|
||||
.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
|
||||
.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
|
||||
.gp = IMX_GPIO_NR(1, 3)
|
||||
},
|
||||
.sda = {
|
||||
.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
|
||||
.gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
|
||||
.gp = IMX_GPIO_NR(1, 6)
|
||||
}
|
||||
};
|
||||
#endif /* CONFIG_SYS_I2C */
|
||||
|
||||
static iomux_v3_cfg_t const uart1_pads[] = {
|
||||
MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const uart2_pads[] = {
|
||||
MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const enet_pads[] = {
|
||||
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
/* AR8035 PHY Reset */
|
||||
MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const pcie_pads[] = {
|
||||
/* W_DISABLE# */
|
||||
MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP),
|
||||
/* PERST# */
|
||||
MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->ram_size = 2048ul * 1024 * 1024;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void setup_iomux_enet(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
|
||||
|
||||
/* Reset AR8035 PHY */
|
||||
gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
|
||||
udelay(500);
|
||||
gpio_set_value(IMX_GPIO_NR(1, 25), 1);
|
||||
}
|
||||
|
||||
static void setup_pcie(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
|
||||
}
|
||||
|
||||
static void setup_iomux_uart(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
|
||||
imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
static iomux_v3_cfg_t const usdhc2_pads[] = {
|
||||
MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const usdhc3_pads[] = {
|
||||
MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const usdhc4_pads[] = {
|
||||
MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
};
|
||||
|
||||
static struct fsl_esdhc_cfg usdhc_cfg[3] = {
|
||||
{USDHC2_BASE_ADDR},
|
||||
{USDHC3_BASE_ADDR},
|
||||
{USDHC4_BASE_ADDR},
|
||||
};
|
||||
|
||||
#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
|
||||
#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
|
||||
|
||||
int board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
||||
int ret = 0;
|
||||
|
||||
switch (cfg->esdhc_base) {
|
||||
case USDHC2_BASE_ADDR:
|
||||
ret = !gpio_get_value(USDHC2_CD_GPIO);
|
||||
break;
|
||||
case USDHC3_BASE_ADDR:
|
||||
ret = !gpio_get_value(USDHC3_CD_GPIO);
|
||||
break;
|
||||
case USDHC4_BASE_ADDR:
|
||||
ret = 1; /* eMMC/uSDHC4 is always present */
|
||||
break;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
s32 status = 0;
|
||||
int i;
|
||||
|
||||
/*
|
||||
* (U-boot device node) (Physical Port)
|
||||
* mmc0 SD2
|
||||
* mmc1 SD3
|
||||
* mmc2 eMMC
|
||||
*/
|
||||
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
|
||||
switch (i) {
|
||||
case 0:
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
|
||||
gpio_direction_input(USDHC2_CD_GPIO);
|
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
||||
break;
|
||||
case 1:
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
|
||||
gpio_direction_input(USDHC3_CD_GPIO);
|
||||
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
||||
break;
|
||||
case 2:
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
|
||||
usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
|
||||
break;
|
||||
default:
|
||||
printf("Warning: you configured more USDHC controllers"
|
||||
"(%d) then supported by the board (%d)\n",
|
||||
i + 1, CONFIG_SYS_FSL_USDHC_NUM);
|
||||
return status;
|
||||
}
|
||||
|
||||
status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
|
||||
}
|
||||
return status;
|
||||
}
|
||||
#endif /* CONFIG_FSL_ESDHC */
|
||||
|
||||
#ifdef CONFIG_VIDEO_IPUV3
|
||||
static void do_enable_hdmi(struct display_info_t const *dev)
|
||||
{
|
||||
imx_enable_hdmi_phy();
|
||||
}
|
||||
|
||||
struct display_info_t const displays[] = {{
|
||||
.bus = -1,
|
||||
.addr = 0,
|
||||
.pixfmt = IPU_PIX_FMT_RGB24,
|
||||
.detect = detect_hdmi,
|
||||
.enable = do_enable_hdmi,
|
||||
.mode = {
|
||||
.name = "HDMI",
|
||||
/* 1024x768@60Hz (VESA)*/
|
||||
.refresh = 60,
|
||||
.xres = 1024,
|
||||
.yres = 768,
|
||||
.pixclock = 15384,
|
||||
.left_margin = 160,
|
||||
.right_margin = 24,
|
||||
.upper_margin = 29,
|
||||
.lower_margin = 3,
|
||||
.hsync_len = 136,
|
||||
.vsync_len = 6,
|
||||
.sync = FB_SYNC_EXT,
|
||||
.vmode = FB_VMODE_NONINTERLACED
|
||||
} } };
|
||||
size_t display_count = ARRAY_SIZE(displays);
|
||||
|
||||
static void setup_display(void)
|
||||
{
|
||||
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
int reg;
|
||||
s32 timeout = 100000;
|
||||
|
||||
enable_ipu_clock();
|
||||
imx_setup_hdmi();
|
||||
|
||||
/* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
|
||||
reg = readl(&ccm->analog_pll_video);
|
||||
reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
|
||||
writel(reg, &ccm->analog_pll_video);
|
||||
|
||||
reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
|
||||
reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
|
||||
reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
|
||||
reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
|
||||
writel(reg, &ccm->analog_pll_video);
|
||||
|
||||
writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
|
||||
writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
|
||||
|
||||
reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
|
||||
writel(reg, &ccm->analog_pll_video);
|
||||
|
||||
while (timeout--)
|
||||
if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
|
||||
break;
|
||||
if (timeout < 0)
|
||||
printf("Warning: video pll lock timeout!\n");
|
||||
|
||||
reg = readl(&ccm->analog_pll_video);
|
||||
reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
|
||||
reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
|
||||
writel(reg, &ccm->analog_pll_video);
|
||||
|
||||
/* select video pll for ldb_di0_clk */
|
||||
reg = readl(&ccm->cs2cdr);
|
||||
reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
|
||||
writel(reg, &ccm->cs2cdr);
|
||||
|
||||
/* select ldb_di0_clk / 7 for ldb_di0_ipu_clk */
|
||||
reg = readl(&ccm->cscmr2);
|
||||
reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
|
||||
writel(reg, &ccm->cscmr2);
|
||||
|
||||
/* select ldb_di0_ipu_clk for ipu1_di0_clk -> 65MHz pixclock */
|
||||
reg = readl(&ccm->chsccdr);
|
||||
reg |= (CHSCCDR_CLK_SEL_LDB_DI0
|
||||
<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
|
||||
writel(reg, &ccm->chsccdr);
|
||||
}
|
||||
#endif /* CONFIG_VIDEO_IPUV3 */
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
setup_iomux_enet();
|
||||
setup_pcie();
|
||||
return cpu_eth_init(bis);
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
setup_iomux_uart();
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
static const struct boot_mode board_boot_modes[] = {
|
||||
/* 4 bit bus width */
|
||||
{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
|
||||
{"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
|
||||
/* 8 bit bus width */
|
||||
{"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
|
||||
{NULL, 0},
|
||||
};
|
||||
#endif
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
|
||||
|
||||
#ifdef CONFIG_VIDEO_IPUV3
|
||||
setup_display();
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_I2C
|
||||
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
|
||||
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
|
||||
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
|
||||
#endif
|
||||
#ifdef CONFIG_DWC_AHSATA
|
||||
setup_sata();
|
||||
#endif
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
add_board_boot_modes(board_boot_modes);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: TBS2910 Matrix ARM mini PC\n");
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
CONFIG_SPL=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6sabresd_spl.cfg,SPL,MX6Q"
|
||||
+S:CONFIG_ARM=y
|
||||
+S:CONFIG_TARGET_MX6SABRESD=y
|
||||
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q"
|
||||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_TBS2910=y
|
||||
|
|
@ -107,7 +107,6 @@
|
|||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"script=boot.scr\0" \
|
||||
"image=zImage\0" \
|
||||
"fdt_file=imx53-qsb.dtb\0" \
|
||||
"fdt_addr=0x71000000\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"ip_dyn=yes\0" \
|
||||
|
|
|
|||
|
|
@ -48,4 +48,20 @@
|
|||
#define CONFIG_SYS_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
|
||||
/* NAND flash command */
|
||||
#define CONFIG_CMD_NAND
|
||||
#define CONFIG_CMD_NAND_TRIMFFS
|
||||
|
||||
/* NAND stuff */
|
||||
#define CONFIG_NAND_MXS
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BASE 0x40000000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
|
||||
/* DMA stuff, needed for GPMI/MXS NAND support */
|
||||
#define CONFIG_APBH_DMA
|
||||
#define CONFIG_APBH_DMA_BURST
|
||||
#define CONFIG_APBH_DMA_BURST8
|
||||
|
||||
#endif /* __MX6QSABREAUTO_CONFIG_H */
|
||||
|
|
|
|||
|
|
@ -251,7 +251,7 @@
|
|||
#define CONFIG_ENV_IS_IN_MMC
|
||||
|
||||
#if defined(CONFIG_ENV_IS_IN_MMC)
|
||||
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
|
||||
#define CONFIG_ENV_OFFSET (8 * 64 * 1024)
|
||||
#endif
|
||||
|
||||
#define CONFIG_OF_LIBFDT
|
||||
|
|
|
|||
|
|
@ -12,6 +12,12 @@
|
|||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/imx-common/gpio.h>
|
||||
|
||||
#ifdef CONFIG_SPL
|
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT
|
||||
#define CONFIG_SPL_MMC_SUPPORT
|
||||
#include "imx6_spl.h"
|
||||
#endif
|
||||
|
||||
#define CONFIG_MACH_TYPE 3980
|
||||
#define CONFIG_MXC_UART_BASE UART1_BASE
|
||||
#define CONFIG_CONSOLE_DEV "ttymxc0"
|
||||
|
|
|
|||
|
|
@ -83,6 +83,13 @@
|
|||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_BOUNCE_BUFFER
|
||||
|
||||
/* USB Configs */
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_USB_EHCI
|
||||
#define CONFIG_USB_EHCI_MX6
|
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
||||
|
||||
#ifdef CONFIG_MX6Q
|
||||
#define CONFIG_CMD_SATA
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,242 @@
|
|||
/*
|
||||
* Copyright (C) 2014 Soeren Moch <smoch@web.de>
|
||||
*
|
||||
* Configuration settings for the TBS2910 MatrixARM board.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __TBS2910_CONFIG_H
|
||||
#define __TBS2910_CONFIG_H
|
||||
|
||||
#include "mx6_common.h"
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/imx-common/gpio.h>
|
||||
|
||||
/* General configuration */
|
||||
#define CONFIG_MX6
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO_LATE
|
||||
#define CONFIG_SYS_THUMB_BUILD
|
||||
|
||||
#define CONFIG_MACH_TYPE 3980
|
||||
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_INITRD_TAG
|
||||
#define CONFIG_REVISION_TAG
|
||||
#define CONFIG_SYS_GENERIC_BOARD
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define CONFIG_MXC_GPIO
|
||||
#define CONFIG_CMD_GPIO
|
||||
|
||||
#define CONFIG_SYS_LONGHELP
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT "Matrix U-Boot> "
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
#define CONFIG_AUTO_COMPLETE
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
#define CONFIG_SYS_MAXARGS 16
|
||||
#define CONFIG_SYS_CBSIZE 1024
|
||||
#define CONFIG_SYS_PBSIZE \
|
||||
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
/* Physical Memory Map */
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
#define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
|
||||
#define CONFIG_SYS_MEMTEST_END \
|
||||
(CONFIG_SYS_MEMTEST_START + 500 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x80000000
|
||||
#define CONFIG_SYS_BOOTMAPSZ 0x6C000000
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x10800000
|
||||
|
||||
/* Serial console */
|
||||
#define CONFIG_MXC_UART
|
||||
#define CONFIG_MXC_UART_BASE UART1_BASE /* select UART1/UART2 */
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
|
||||
#define CONFIG_CONSOLE_MUX
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
|
||||
/* *** Command definition *** */
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#undef CONFIG_CMD_IMLS
|
||||
|
||||
#define CONFIG_CMD_BMODE
|
||||
#define CONFIG_CMD_SETEXPR
|
||||
#define CONFIG_CMD_MEMTEST
|
||||
#define CONFIG_CMD_TIME
|
||||
|
||||
/* Filesystems / image support */
|
||||
#define CONFIG_CMD_EXT4
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_EFI_PARTITION
|
||||
#define CONFIG_CMD_FS_GENERIC
|
||||
|
||||
#define CONFIG_OF_LIBFDT
|
||||
#define CONFIG_CMD_BOOTZ
|
||||
#define CONFIG_SUPPORT_RAW_INITRD
|
||||
#define CONFIG_FIT
|
||||
|
||||
/* MMC */
|
||||
#define CONFIG_FSL_ESDHC
|
||||
#define CONFIG_FSL_USDHC
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 3
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
|
||||
|
||||
#define CONFIG_MMC
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_BOUNCE_BUFFER
|
||||
|
||||
/* Ethernet */
|
||||
#define CONFIG_FEC_MXC
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_FEC_MXC
|
||||
#define CONFIG_MII
|
||||
#define IMX_FEC_BASE ENET_BASE_ADDR
|
||||
#define CONFIG_FEC_XCV_TYPE RGMII
|
||||
#define CONFIG_ETHPRIME "FEC"
|
||||
#define CONFIG_FEC_MXC_PHYADDR 4
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_ATHEROS
|
||||
|
||||
/* Framebuffer */
|
||||
#define CONFIG_VIDEO
|
||||
#ifdef CONFIG_VIDEO
|
||||
#define CONFIG_VIDEO_IPUV3
|
||||
#define CONFIG_IPUV3_CLK 260000000
|
||||
#define CONFIG_CFB_CONSOLE
|
||||
#define CONFIG_CFB_CONSOLE_ANSI
|
||||
#define CONFIG_VIDEO_SW_CURSOR
|
||||
#define CONFIG_VGA_AS_SINGLE_DEVICE
|
||||
#define CONFIG_VIDEO_BMP_RLE8
|
||||
#define CONFIG_IMX_HDMI
|
||||
#define CONFIG_IMX_VIDEO_SKIP
|
||||
#define CONFIG_CMD_HDMIDETECT
|
||||
#endif
|
||||
|
||||
/* PCI */
|
||||
#define CONFIG_CMD_PCI
|
||||
#ifdef CONFIG_CMD_PCI
|
||||
#define CONFIG_PCI
|
||||
#define CONFIG_PCI_PNP
|
||||
#define CONFIG_PCI_SCAN_SHOW
|
||||
#define CONFIG_PCIE_IMX
|
||||
#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
|
||||
#endif
|
||||
|
||||
/* SATA */
|
||||
#define CONFIG_CMD_SATA
|
||||
#ifdef CONFIG_CMD_SATA
|
||||
#define CONFIG_DWC_AHSATA
|
||||
#define CONFIG_SYS_SATA_MAX_DEVICE 1
|
||||
#define CONFIG_DWC_AHSATA_PORT_ID 0
|
||||
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
|
||||
#define CONFIG_LBA48
|
||||
#define CONFIG_LIBATA
|
||||
#endif
|
||||
|
||||
/* USB */
|
||||
#define CONFIG_CMD_USB
|
||||
#ifdef CONFIG_CMD_USB
|
||||
#define CONFIG_USB_EHCI
|
||||
#define CONFIG_USB_EHCI_MX6
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_USB_KEYBOARD
|
||||
#ifdef CONFIG_USB_KEYBOARD
|
||||
#define CONFIG_SYS_USB_EVENT_POLL
|
||||
#define CONFIG_SYS_STDIO_DEREGISTER
|
||||
#define CONFIG_PREBOOT "if hdmidet; then usb start; fi"
|
||||
#endif /* CONFIG_USB_KEYBOARD */
|
||||
#endif /* CONFIG_CMD_USB */
|
||||
|
||||
/* RTC */
|
||||
#define CONFIG_CMD_DATE
|
||||
#ifdef CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_RTC_DS1307
|
||||
#define CONFIG_SYS_RTC_BUS_NUM 2
|
||||
#endif
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_CMD_I2C
|
||||
#ifdef CONFIG_CMD_I2C
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_I2C_EDID
|
||||
#endif
|
||||
|
||||
/* Fuses */
|
||||
#define CONFIG_CMD_FUSE
|
||||
#ifdef CONFIG_CMD_FUSE
|
||||
#define CONFIG_MXC_OCOTP
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_DCACHE_OFF
|
||||
#define CONFIG_CMD_CACHE
|
||||
#endif
|
||||
|
||||
/* Flash and environment organization */
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
|
||||
#define CONFIG_ENV_IS_IN_MMC
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 2
|
||||
#define CONFIG_SYS_MMC_ENV_PART 1
|
||||
#define CONFIG_ENV_SIZE (8 * 1024)
|
||||
#define CONFIG_ENV_OFFSET (384 * 1024)
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"bootargs_mmc1=console=ttymxc0,115200 di0_primary console=tty1\0" \
|
||||
"bootargs_mmc2=video=mxcfb0:dev=hdmi,1920x1080M@60 " \
|
||||
"video=mxcfb1:off video=mxcfb2:off fbmem=28M\0" \
|
||||
"bootargs_mmc3=root=/dev/mmcblk0p1 rootwait consoleblank=0 quiet\0" \
|
||||
"bootargs_mmc=setenv bootargs ${bootargs_mmc1} ${bootargs_mmc2} " \
|
||||
"${bootargs_mmc3}\0" \
|
||||
"bootargs_upd=setenv bootargs console=ttymxc0,115200 " \
|
||||
"rdinit=/sbin/init enable_wait_mode=off\0" \
|
||||
"bootcmd_mmc=run bootargs_mmc; mmc dev 2; " \
|
||||
"mmc read 0x10800000 0x800 0x4000; bootm\0" \
|
||||
"bootcmd_up1=load mmc 1 0x10800000 uImage\0" \
|
||||
"bootcmd_up2=load mmc 1 0x10d00000 uramdisk.img; " \
|
||||
"run bootargs_upd; " \
|
||||
"bootm 0x10800000 0x10d00000\0" \
|
||||
"console=ttymxc0\0" \
|
||||
"fan=gpio set 92\0" \
|
||||
"stdin=serial,usbkbd\0" \
|
||||
"stdout=serial,vga\0" \
|
||||
"stderr=serial,vga\0"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"mmc rescan; " \
|
||||
"if run bootcmd_up1; then " \
|
||||
"run bootcmd_up2; " \
|
||||
"else " \
|
||||
"run bootcmd_mmc; " \
|
||||
"fi"
|
||||
|
||||
#endif /* __TBS2910_CONFIG_H * */
|
||||
Loading…
Reference in New Issue