Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx
This commit is contained in:
commit
45b728cdee
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@ -65,16 +65,16 @@ void cpu_init_f (volatile immap_t * im)
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{
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__be32 acr_mask =
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#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
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(ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) |
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ACR_PIPE_DEP |
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#endif
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#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
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(ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
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ACR_RPTCNT |
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#endif
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#ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */
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(ACR_APARK << ACR_APARK_SHIFT) |
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ACR_APARK |
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#endif
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#ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */
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(ACR_PARKM << ACR_PARKM_SHIFT) |
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ACR_PARKM |
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#endif
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0;
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__be32 acr_val =
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@ -93,16 +93,16 @@ void cpu_init_f (volatile immap_t * im)
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0;
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__be32 spcr_mask =
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#ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */
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(SPCR_OPT << SPCR_OPT_SHIFT) |
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SPCR_OPT |
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#endif
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#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
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(SPCR_TSECEP << SPCR_TSECEP_SHIFT) |
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SPCR_TSECEP |
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#endif
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#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
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(SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) |
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SPCR_TSEC1EP |
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#endif
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#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
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(SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) |
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SPCR_TSEC2EP |
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#endif
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0;
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__be32 spcr_val =
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@ -121,34 +121,34 @@ void cpu_init_f (volatile immap_t * im)
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0;
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__be32 sccr_mask =
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#ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
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(SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
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SCCR_ENCCM |
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#endif
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#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
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(SCCR_PCICM << SCCR_PCICM_SHIFT) |
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SCCR_PCICM |
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#endif
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#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
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(SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
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SCCR_TSECCM |
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#endif
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#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
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(SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
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SCCR_TSEC1CM |
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#endif
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#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
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(SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
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SCCR_TSEC2CM |
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#endif
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#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
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(SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
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SCCR_TSEC1ON |
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#endif
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#ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
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(SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
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SCCR_TSEC2ON |
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#endif
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#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
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(SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
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SCCR_USBMPHCM |
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#endif
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#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
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(SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
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SCCR_USBDRCM |
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#endif
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#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
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(SCCR_SATACM << SCCR_SATACM_SHIFT) |
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SCCR_SATACM |
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#endif
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0;
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__be32 sccr_val =
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@ -507,7 +507,7 @@ init_e300_core: /* time t 10 */
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lis r3, CONFIG_SYS_IMMR@h
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#if defined(CONFIG_WATCHDOG)
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/* Initialise the Wathcdog values and reset it (if req) */
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/* Initialise the Watchdog values and reset it (if req) */
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/*------------------------------------------------------*/
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lis r4, CONFIG_SYS_WATCHDOG_VALUE
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ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
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@ -520,7 +520,7 @@ init_e300_core: /* time t 10 */
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li r4, -0x55C7
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sth r4, SWSRR@l(r3)
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#else
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/* Disable Wathcdog */
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/* Disable Watchdog */
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/*-------------------*/
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lwz r4, SWCRR(r3)
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/* Check to see if its enabled for disabling
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