Tegra114: Dalmore: Add pad config tables/code based on pinmux code
Pad config registers exist in APB_MISC_GP space, and control slew rate, drive strengh, schmidt, high-speed, and low-power modes for all of the pingroups in Tegra30. This builds off of the pinmux way of constructing init tables to configure select pads (SDIOCFG, for instance) during pinmux_init(). Currently, no padcfg entries exist. SDIO3CFG will be added when the MMC driver is added as per the TRM to work with the SD-card slot on Dalmore E1611. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>utp
Tom Warren
parent
5647c03431
commit
477393e787
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@ -39,6 +39,19 @@ struct tegra_pingroup_desc {
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#define PMUX_IO_RESET_SHIFT 8
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#define PMUX_RCV_SEL_SHIFT 9
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#define PGRP_HSM_SHIFT 2
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#define PGRP_SCHMT_SHIFT 3
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#define PGRP_LPMD_SHIFT 4
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#define PGRP_LPMD_MASK (3 << PGRP_LPMD_SHIFT)
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#define PGRP_DRVDN_SHIFT 12
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#define PGRP_DRVDN_MASK (0x7F << PGRP_DRVDN_SHIFT)
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#define PGRP_DRVUP_SHIFT 20
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#define PGRP_DRVUP_MASK (0x7F << PGRP_DRVUP_SHIFT)
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#define PGRP_SLWR_SHIFT 28
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#define PGRP_SLWR_MASK (3 << PGRP_SLWR_SHIFT)
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#define PGRP_SLWF_SHIFT 30
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#define PGRP_SLWF_MASK (3 << PGRP_SLWF_SHIFT)
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/* Convenient macro for defining pin group properties */
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#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
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{ \
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@ -544,3 +557,184 @@ void pinmux_config_table(struct pingroup_config *config, int len)
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for (i = 0; i < len; i++)
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pinmux_config_pingroup(&config[i]);
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}
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static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad, int slwf)
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{
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struct pmux_tri_ctlr *pmt =
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(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
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u32 *pad_slwf = &pmt->pmt_drive[pad];
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u32 reg;
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/* Error check on pad and slwf */
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assert(pmux_padgrp_isvalid(pad));
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assert(pmux_pad_slw_isvalid(slwf));
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/* NONE means unspecified/do not change/use POR value */
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if (slwf == PGRP_SLWF_NONE)
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return 0;
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reg = readl(pad_slwf);
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reg &= ~PGRP_SLWF_MASK;
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reg |= (slwf << PGRP_SLWF_SHIFT);
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writel(reg, pad_slwf);
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return 0;
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}
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static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr)
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{
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struct pmux_tri_ctlr *pmt =
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(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
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u32 *pad_slwr = &pmt->pmt_drive[pad];
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u32 reg;
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/* Error check on pad and slwr */
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assert(pmux_padgrp_isvalid(pad));
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assert(pmux_pad_slw_isvalid(slwr));
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/* NONE means unspecified/do not change/use POR value */
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if (slwr == PGRP_SLWR_NONE)
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return 0;
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reg = readl(pad_slwr);
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reg &= ~PGRP_SLWR_MASK;
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reg |= (slwr << PGRP_SLWR_SHIFT);
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writel(reg, pad_slwr);
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return 0;
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}
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static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup)
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{
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struct pmux_tri_ctlr *pmt =
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(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
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u32 *pad_drvup = &pmt->pmt_drive[pad];
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u32 reg;
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/* Error check on pad and drvup */
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assert(pmux_padgrp_isvalid(pad));
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assert(pmux_pad_drv_isvalid(drvup));
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/* NONE means unspecified/do not change/use POR value */
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if (drvup == PGRP_DRVUP_NONE)
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return 0;
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reg = readl(pad_drvup);
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reg &= ~PGRP_DRVUP_MASK;
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reg |= (drvup << PGRP_DRVUP_SHIFT);
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writel(reg, pad_drvup);
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return 0;
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}
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static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn)
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{
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struct pmux_tri_ctlr *pmt =
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(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
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u32 *pad_drvdn = &pmt->pmt_drive[pad];
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u32 reg;
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/* Error check on pad and drvdn */
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assert(pmux_padgrp_isvalid(pad));
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assert(pmux_pad_drv_isvalid(drvdn));
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/* NONE means unspecified/do not change/use POR value */
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if (drvdn == PGRP_DRVDN_NONE)
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return 0;
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reg = readl(pad_drvdn);
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reg &= ~PGRP_DRVDN_MASK;
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reg |= (drvdn << PGRP_DRVDN_SHIFT);
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writel(reg, pad_drvdn);
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return 0;
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}
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static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd)
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{
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struct pmux_tri_ctlr *pmt =
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(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
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u32 *pad_lpmd = &pmt->pmt_drive[pad];
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u32 reg;
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/* Error check pad and lpmd value */
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assert(pmux_padgrp_isvalid(pad));
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assert(pmux_pad_lpmd_isvalid(lpmd));
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/* NONE means unspecified/do not change/use POR value */
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if (lpmd == PGRP_LPMD_NONE)
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return 0;
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reg = readl(pad_lpmd);
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reg &= ~PGRP_LPMD_MASK;
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reg |= (lpmd << PGRP_LPMD_SHIFT);
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writel(reg, pad_lpmd);
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return 0;
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}
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static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt)
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{
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struct pmux_tri_ctlr *pmt =
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(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
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u32 *pad_schmt = &pmt->pmt_drive[pad];
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u32 reg;
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/* Error check pad */
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assert(pmux_padgrp_isvalid(pad));
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/* NONE means unspecified/do not change/use POR value */
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if (schmt == PGRP_SCHMT_NONE)
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return 0;
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reg = readl(pad_schmt);
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reg &= ~(1 << PGRP_SCHMT_SHIFT);
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if (schmt == PGRP_SCHMT_ENABLE)
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reg |= (0x1 << PGRP_SCHMT_SHIFT);
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writel(reg, pad_schmt);
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return 0;
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}
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static int padgrp_set_hsm(enum pdrive_pingrp pad, enum pgrp_hsm hsm)
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{
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struct pmux_tri_ctlr *pmt =
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(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
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u32 *pad_hsm = &pmt->pmt_drive[pad];
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u32 reg;
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/* Error check pad */
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assert(pmux_padgrp_isvalid(pad));
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/* NONE means unspecified/do not change/use POR value */
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if (hsm == PGRP_HSM_NONE)
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return 0;
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reg = readl(pad_hsm);
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reg &= ~(1 << PGRP_HSM_SHIFT);
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if (hsm == PGRP_HSM_ENABLE)
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reg |= (0x1 << PGRP_HSM_SHIFT);
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writel(reg, pad_hsm);
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return 0;
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}
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void padctrl_config_pingroup(struct padctrl_config *config)
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{
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enum pdrive_pingrp pad = config->padgrp;
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padgrp_set_drvup_slwf(pad, config->slwf);
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padgrp_set_drvdn_slwr(pad, config->slwr);
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padgrp_set_drvup(pad, config->drvup);
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padgrp_set_drvdn(pad, config->drvdn);
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padgrp_set_lpmd(pad, config->lpmd);
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padgrp_set_schmt(pad, config->schmt);
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padgrp_set_hsm(pad, config->hsm);
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}
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void padgrp_config_table(struct padctrl_config *config, int len)
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{
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int i;
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for (i = 0; i < len; i++)
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padctrl_config_pingroup(&config[i]);
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}
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@ -215,34 +215,35 @@ enum pdrive_pingrp {
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PDRIVE_PINGROUP_AT5,
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PDRIVE_PINGROUP_CDEV1,
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PDRIVE_PINGROUP_CDEV2,
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PDRIVE_PINGROUP_CSUS,
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PDRIVE_PINGROUP_DAP1,
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PDRIVE_PINGROUP_DAP1 = 10, /* offset 0x890 */
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PDRIVE_PINGROUP_DAP2,
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PDRIVE_PINGROUP_DAP3,
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PDRIVE_PINGROUP_DAP4,
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PDRIVE_PINGROUP_DBG,
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PDRIVE_PINGROUP_SDIO3,
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PDRIVE_PINGROUP_SDIO3 = 18, /* offset 0x8B0 */
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PDRIVE_PINGROUP_SPI,
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PDRIVE_PINGROUP_UAA,
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PDRIVE_PINGROUP_UAB,
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PDRIVE_PINGROUP_UART2,
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PDRIVE_PINGROUP_UART3,
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PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8ec */
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PDRIVE_PINGROUP_CRT = 36, /* offset 0x8f8 */
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PDRIVE_PINGROUP_DDC,
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PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8EC */
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PDRIVE_PINGROUP_DDC = 37, /* offset 0x8FC */
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PDRIVE_PINGROUP_GMA,
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PDRIVE_PINGROUP_GME,
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PDRIVE_PINGROUP_GME = 42, /* offset 0x910 */
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PDRIVE_PINGROUP_GMF,
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PDRIVE_PINGROUP_GMG,
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PDRIVE_PINGROUP_GMH,
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PDRIVE_PINGROUP_OWR,
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PDRIVE_PINGROUP_UAD,
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PDRIVE_PINGROUP_GPV,
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PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */
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PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */
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PDRIVE_PINGROUP_AT6,
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PDRIVE_PINGROUP_AT6 = 75, /* offset 0x994 */
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PDRIVE_PINGROUP_DAP5,
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PDRIVE_PINGROUP_VBUS,
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PDRIVE_PINGROUP_AO3,
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PDRIVE_PINGROUP_HVC,
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PDRIVE_PINGROUP_SDIO4,
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PDRIVE_PINGROUP_AO0,
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PDRIVE_PINGROUP_COUNT,
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};
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@ -470,10 +471,73 @@ enum pmux_vddio {
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PMUX_VDDIO_NONE
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};
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/* T114 pin drive group and pin mux registers */
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#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2)
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#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
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PDRIVE_PINGROUP_COUNT)
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#define PGRP_SLWF_NONE -1
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#define PGRP_SLWF_MAX 3
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#define PGRP_SLWR_NONE PGRP_SLWF_NONE
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#define PGRP_SLWR_MAX PGRP_SLWF_MAX
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#define PGRP_DRVUP_NONE -1
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#define PGRP_DRVUP_MAX 127
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#define PGRP_DRVDN_NONE PGRP_DRVUP_NONE
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#define PGRP_DRVDN_MAX PGRP_DRVUP_MAX
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#define PGRP_SCHMT_NONE -1
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#define PGRP_HSM_NONE PGRP_SCHMT_NONE
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/* return 1 if a padgrp is in range */
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#define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT))
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/* return 1 if a slew-rate rising/falling edge value is in range */
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#define pmux_pad_slw_isvalid(slw) (((slw) == PGRP_SLWF_NONE) || \
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(((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX)))
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/* return 1 if a driver output pull-up/down strength code value is in range */
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#define pmux_pad_drv_isvalid(drv) (((drv) == PGRP_DRVUP_NONE) || \
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(((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX)))
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/* return 1 if a low-power mode value is in range */
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#define pmux_pad_lpmd_isvalid(lpm) (((lpm) == PGRP_LPMD_NONE) || \
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(((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X)))
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/* Defines a pin group cfg's low-power mode select */
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enum pgrp_lpmd {
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PGRP_LPMD_X8 = 0,
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PGRP_LPMD_X4,
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PGRP_LPMD_X2,
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PGRP_LPMD_X,
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PGRP_LPMD_NONE = -1,
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};
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/* Defines whether a pin group cfg's schmidt is enabled or not */
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enum pgrp_schmt {
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PGRP_SCHMT_DISABLE = 0,
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PGRP_SCHMT_ENABLE = 1,
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};
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/* Defines whether a pin group cfg's high-speed mode is enabled or not */
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enum pgrp_hsm {
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PGRP_HSM_DISABLE = 0,
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PGRP_HSM_ENABLE = 1,
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};
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/*
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* This defines the configuration for a pin group's pad control config
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*/
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struct padctrl_config {
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enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */
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int slwf; /* falling edge slew */
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int slwr; /* rising edge slew */
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int drvup; /* pull-up drive strength */
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int drvdn; /* pull-down drive strength */
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enum pgrp_lpmd lpmd; /* low-power mode selection */
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enum pgrp_schmt schmt; /* schmidt enable */
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enum pgrp_hsm hsm; /* high-speed mode enable */
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};
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/* t114 pin drive group and pin mux registers */
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#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2)
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#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
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PDRIVE_PINGROUP_COUNT)
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struct pmux_tri_ctlr {
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uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */
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uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */
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@ -541,4 +605,12 @@ void pinmux_config_table(struct pingroup_config *config, int len);
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/* Set a group of pins from a table */
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void pinmux_init(void);
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#endif /* _TEGRA114_PINMUX_H_ */
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/**
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* Set the GP pad configs
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*
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* @param config List of config items
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* @param len Number of config items in list
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*/
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void padgrp_config_table(struct padctrl_config *config, int len);
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#endif /* _TEGRA114_PINMUX_H_ */
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@ -79,6 +79,18 @@
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#define USB_PINMUX CEC_PINMUX
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#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
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{ \
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.padgrp = PDRIVE_PINGROUP_##_padgrp, \
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.slwf = _slwf, \
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.slwr = _slwr, \
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.drvup = _drvup, \
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.drvdn = _drvdn, \
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.lpmd = PGRP_LPMD_##_lpmd, \
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.schmt = PGRP_SCHMT_##_schmt, \
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.hsm = PGRP_HSM_##_hsm, \
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}
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static struct pingroup_config tegra114_pinmux_common[] = {
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/* EXTPERIPH1 pinmux */
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DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, OUTPUT),
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