Blackfin: add workaround for anomaly 05000242
DESCRIPTION: If the DF bit is set prior to a hardware reset, the PLL will continue to divide CLKIN by 2 after the hardware reset, but the DF bit itself will be cleared in the PLL_CTL register. WORKAROUND: Reprogram the PLL with DF cleared if the desire is to not divide CLKIN by 2 after reset. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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@ -401,7 +401,7 @@ void initcode(ADI_BOOT_DATA *bootstruct)
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/* Only reprogram when needed to avoid triggering unnecessary
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* PLL relock sequences.
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*/
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if (bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
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if (ANOMALY_05000242 || bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
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serial_putc('!');
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bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
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asm("idle;");
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