powerpc/t1024rdb: Add T1024 RDB board support
T1024RDB is a Freescale Reference Design Board that hosts the T1024 SoC. T1024RDB board Overview ----------------------- - T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz - CoreNet fabric supporting coherent and noncoherent transactions with prioritization and bandwidth allocation - 32-/64-bit DDR3L SDRAM memory controller with ECC and interleaving support - Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC - Ethernet interfaces: - Two 10M/100M/1G RGMII ports on-board - one 10Gbps XFI interface - PCIe: Three PCIe controllers: one PCIe Slot and two Mini-PCIe connectors. - SerDes: 4 lanes up to 10.3125GHz - IFC: 128MB NOR Flash, 512MB NAND Flash and CPLD - eSPI: 64MB N25Q512 SPI flash. - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - USB: Two Type-A USB2.0 ports with internal PHY - eSDHC: Support SD, SDHC, SDXC and MMC/eMMC - I2C: Four I2C controllers - UART: Two UART serial ports Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: Fix ft_board_setup() type, fix MAINTAINERS for SECURE_BOOT Fix Kconfig by adding SUPPORT_SPL] Reviewed-by: York Sun <yorksun@freescale.com>utp
Shengzhou Liu
York Sun
parent
aba8004818
commit
48c6f328f0
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@ -114,6 +114,10 @@ config TARGET_T102XQDS
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bool "Support T102xQDS"
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select SUPPORT_SPL
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config TARGET_T102XRDB
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bool "Support T102xRDB"
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select SUPPORT_SPL
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config TARGET_T1040QDS
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bool "Support T1040QDS"
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@ -188,6 +192,7 @@ source "board/freescale/p2020ds/Kconfig"
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source "board/freescale/p2041rdb/Kconfig"
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source "board/freescale/qemu-ppce500/Kconfig"
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source "board/freescale/t102xqds/Kconfig"
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source "board/freescale/t102xrdb/Kconfig"
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source "board/freescale/t1040qds/Kconfig"
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source "board/freescale/t104xrdb/Kconfig"
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source "board/freescale/t208xqds/Kconfig"
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@ -0,0 +1,12 @@
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if TARGET_T102XRDB
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config SYS_BOARD
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default "t102xrdb"
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config SYS_VENDOR
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default "freescale"
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config SYS_CONFIG_NAME
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default "T102xRDB"
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endif
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@ -0,0 +1,10 @@
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T102XRDB BOARD
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M: Shengzhou Liu <Shengzhou.Liu@freescale.com>
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S: Maintained
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F: board/freescale/t102xrdb/
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F: include/configs/T102xRDB.h
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F: configs/T1024RDB_defconfig
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F: configs/T1024RDB_NAND_defconfig
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F: configs/T1024RDB_SDCARD_defconfig
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F: configs/T1024RDB_SPIFLASH_defconfig
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F: configs/T1024RDB_SECURE_BOOT_defconfig
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@ -0,0 +1,17 @@
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#
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# Copyright 2014 Freescale Semiconductor, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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ifdef CONFIG_SPL_BUILD
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obj-y += spl.o
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else
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obj-y += t102xrdb.o
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obj-y += cpld.o
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obj-y += eth_t102xrdb.o
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obj-$(CONFIG_PCI) += pci.o
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endif
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obj-y += ddr.o
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obj-y += law.o
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obj-y += tlb.o
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@ -0,0 +1,258 @@
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T1024 SoC Overview
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------------------
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The T1024/T1023 dual core and T1014/T1013 single core QorIQ communication processor
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combines two or one 64-bit Power Architecture e5500 core respectively with high
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performance datapath acceleration logic, and network peripheral bus interfaces
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required for networking and telecommunications. This processor can be used in
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applications such as enterprise WLAN access points, routers, switches, firewall
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and other packet processing intensive small enterprise and branch office appliances,
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and general-purpose embedded computing. Its high level of integration offers
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significant performance benefits and greatly helps to simplify board design.
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The T1024 SoC includes the following function and features:
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- two e5500 cores, each with a private 256 KB L2 cache
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- Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
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- Three levels of instructions: User, supervisor, and hypervisor
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- Independent boot and reset
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- Secure boot capability
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- 256 KB shared L3 CoreNet platform cache (CPC)
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- Interconnect CoreNet platform
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- CoreNet coherency manager supporting coherent and noncoherent transactions
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with prioritization and bandwidth allocation amongst CoreNet endpoints
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- 150 Gbps coherent read bandwidth
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- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
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- Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions:
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- Packet parsing, classification, and distribution
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- Queue management for scheduling, packet sequencing, and congestion management
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- Cryptography Acceleration (SEC 5.x)
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- IEEE 1588 support
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- Hardware buffer management for buffer allocation and deallocation
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- MACSEC on DPAA-based Ethernet ports
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- Ethernet interfaces
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- Four 1 Gbps Ethernet controllers
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- Parallel Ethernet interfaces
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- Two RGMII interfaces
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- High speed peripheral interfaces
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- Three PCI Express 2.0 controllers/ports running at up to 5 GHz
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- One SATA controller supporting 1.5 and 3.0 Gb/s operation
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- One QSGMII interface
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- Four SGMII interface supporting 1000 Mbps
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- Three SGMII interfaces supporting up to 2500 Mbps
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- 10GbE XFI or 10Base-KR interface
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- Additional peripheral interfaces
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- Two USB 2.0 controllers with integrated PHY
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- SD/eSDHC/eMMC
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- eSPI controller
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- Four I2C controllers
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- Four UARTs
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- Four GPIO controllers
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- Integrated flash controller (IFC)
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- LCD interface (DIU) with 12 bit dual data rate
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- Multicore programmable interrupt controller (PIC)
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- Two 8-channel DMA engines
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- Single source clocking implementation
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- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
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- QUICC Engine block
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- 32-bit RISC controller for flexible support of the communications peripherals
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- Serial DMA channel for receive and transmit on all serial channels
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- Two universal communication controllers, supporting TDM, HDLC, and UART
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T1023 Personality
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------------------
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T1023 is a reduced personality of T1024 without QUICC Engine, DIU, and
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unavailable deep sleep. Rest of the blocks are almost same as T1024.
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Differences between T1024 and T1023
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Feature T1024 T1023
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QUICC Engine: yes no
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DIU: yes no
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Deep Sleep: yes no
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I2C controller: 4 3
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DDR: 64-bit 32-bit
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IFC: 32-bit 28-bit
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T1024RDB board Overview
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-----------------------
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- Ethernet
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- Two on-board 10M/100M/1G bps RGMII ethernet ports
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- One on-board 10G bps Base-T port.
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- DDR Memory
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- Supports 64-bit 4GB DDR3L DIMM
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- PCIe
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- One on-board PCIe slot.
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- Two on-board PCIe Mini-PCIe connectors.
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- IFC/Local Bus
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- NOR: 128MB 16-bit NOR Flash
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- NAND: 1GB 8-bit NAND flash
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- CPLD: for system controlling with programable header on-board
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- USB
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- Supports two USB 2.0 ports with integrated PHYs
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- Two type A ports with 5V@1.5A per port.
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- SDHC
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- one SD connector supporting 1.8V/3.3V via J53.
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- SPI
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- On-board 64MB SPI flash
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- Other
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- Two Serial ports
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- Four I2C ports
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Memory map on T1024RDB
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----------------------
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Start Address End Address Description Size
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0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
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0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
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0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
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0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
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0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
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0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
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0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
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0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
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0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
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0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
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0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB
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0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB
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0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB
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0x0_0000_0000 0x0_ffff_ffff DDR 4GB
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128MB NOR Flash memory Map
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--------------------------
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Start Address End Address Definition Max size
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0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB
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0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB
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0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
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0xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB
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0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
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0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
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0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
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0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
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0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB
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0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB
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0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
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0xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB
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0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
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0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
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0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
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0xE8000000 0xE801FFFF RCW (current bank) 128KB
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T1024 Clock frequency
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---------------------
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BIN Core DDR Platform FMan
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Bin1: 1400MHz 1600MT/s 400MHz 700MHz
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Bin2: 1200MHz 1600MT/s 400MHz 600MHz
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Bin3: 1000MHz 1600MT/s 400MHz 500MHz
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Software configurations and board settings
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------------------------------------------
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1. NOR boot:
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a. build NOR boot image
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$ make T1024RDB_defconfig
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$ make
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b. program u-boot.bin image to NOR flash
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=> tftp 1000000 u-boot.bin
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=> pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
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set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
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Switching between default bank0 and alternate bank4 on NOR flash
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To change boot source to vbank4:
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via software: run command 'cpld reset altbank' in u-boot.
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via DIP-switch: set SW3[5:7] = '100'
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To change boot source to vbank0:
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via software: run command 'cpld reset' in u-boot.
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via DIP-Switch: set SW3[5:7] = '000'
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2. NAND Boot:
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a. build PBL image for NAND boot
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$ make T1024RDB_NAND_defconfig
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$ make
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b. program u-boot-with-spl-pbl.bin to NAND flash
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=> tftp 1000000 u-boot-with-spl-pbl.bin
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=> nand erase 0 $filesize
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=> nand write 1000000 0 $filesize
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set SW1[1:8] = '10001000', SW2[1] = '1', SW3[4] = '1' for NAND boot
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3. SPI Boot:
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a. build PBL image for SPI boot
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$ make T1024RDB_SPIFLASH_defconfig
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$ make
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b. program u-boot-with-spl-pbl.bin to SPI flash
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=> tftp 1000000 u-boot-with-spl-pbl.bin
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=> sf probe 0
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=> sf erase 0 f0000
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=> sf write 1000000 0 $filesize
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set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
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4. SD Boot:
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a. build PBL image for SD boot
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$ make T1024RDB_SDCARD_defconfig
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$ make
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b. program u-boot-with-spl-pbl.bin to SD/MMC card
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=> tftp 1000000 u-boot-with-spl-pbl.bin
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=> mmc write 1000000 8 0x800
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=> tftp 1000000 fsl_fman_ucode_t1024_xx.bin
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=> mmc write 1000000 0x820 80
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set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
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2-stage NAND/SPI/SD boot loader
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-------------------------------
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PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
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SPL further initializes DDR using SPD and environment variables
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and copy u-boot(768 KB) from NAND/SPI/SD device to DDR.
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Finally SPL transers control to u-boot for futher booting.
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SPL has following features:
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- Executes within 256K
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- No relocation required
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Run time view of SPL framework
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-------------------------------------------------
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|Area | Address |
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-------------------------------------------------
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|SecureBoot header | 0xFFFC0000 (32KB) |
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-------------------------------------------------
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|GD, BD | 0xFFFC8000 (4KB) |
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-------------------------------------------------
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|ENV | 0xFFFC9000 (8KB) |
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-------------------------------------------------
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|HEAP | 0xFFFCB000 (30KB) |
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-------------------------------------------------
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|STACK | 0xFFFD8000 (22KB) |
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-------------------------------------------------
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|U-boot SPL | 0xFFFD8000 (160KB) |
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-------------------------------------------------
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NAND Flash memory Map on T1024RDB
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-------------------------------------------------------------
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Start End Definition Size
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0x000000 0x0FFFFF u-boot 1MB(2 block)
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0x100000 0x17FFFF u-boot env 512KB(1 block)
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0x180000 0x1FFFFF FMAN Ucode 512KB(1 block)
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0x200000 0x27FFFF QE Firmware 512KB(1 block)
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SD Card memory Map on T1024RDB
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----------------------------------------------------
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Block #blocks Definition Size
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0x008 2048 u-boot img 1MB
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0x800 0016 u-boot env 8KB
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0x820 0256 FMAN Ucode 128KB
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0x920 0256 QE Firmware 128KB
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SPI Flash memory Map on T1024RDB
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----------------------------------------------------
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Start End Definition Size
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0x000000 0x0FFFFF u-boot img 1MB
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0x100000 0x101FFF u-boot env 8KB
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0x110000 0x12FFFF FMAN Ucode 128KB
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0x130000 0x14FFFF QE Firmware 128KB
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For more details, please refer to T1024RDB Reference Manual and access
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website www.freescale.com and Freescale QorIQ SDK Infocenter document.
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@ -0,0 +1,103 @@
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/**
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* Copyright 2014 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Freescale T1024RDB board-specific CPLD controlling supports.
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*
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* The following macros need to be defined:
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/io.h>
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#include "cpld.h"
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u8 cpld_read(unsigned int reg)
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{
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void *p = (void *)CONFIG_SYS_CPLD_BASE;
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return in_8(p + reg);
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}
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void cpld_write(unsigned int reg, u8 value)
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{
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void *p = (void *)CONFIG_SYS_CPLD_BASE;
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out_8(p + reg, value);
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}
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/**
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* Set the boot bank to the alternate bank
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*/
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void cpld_set_altbank(void)
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{
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u8 reg = CPLD_READ(flash_csr);
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reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK;
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CPLD_WRITE(flash_csr, reg);
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CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
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}
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/**
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* Set the boot bank to the default bank
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*/
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void cpld_set_defbank(void)
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{
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u8 reg = CPLD_READ(flash_csr);
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reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK;
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CPLD_WRITE(flash_csr, reg);
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CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
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}
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static void cpld_dump_regs(void)
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{
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printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver));
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printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub));
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printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver));
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printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver));
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printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1));
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printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2));
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printf("int_status = 0x%02x\n", CPLD_READ(int_status));
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printf("flash_csr = 0x%02x\n", CPLD_READ(flash_csr));
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printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status));
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printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status));
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printf("sfp_ctl_status = 0x%02x\n", CPLD_READ(sfp_ctl_status));
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printf("misc_ctl_status = 0x%02x\n", CPLD_READ(misc_ctl_status));
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printf("boot_override = 0x%02x\n", CPLD_READ(boot_override));
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printf("boot_config1 = 0x%02x\n", CPLD_READ(boot_config1));
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printf("boot_config2 = 0x%02x\n", CPLD_READ(boot_config2));
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putc('\n');
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}
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int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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int rc = 0;
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if (argc <= 1)
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return cmd_usage(cmdtp);
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if (strcmp(argv[1], "reset") == 0) {
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if (strcmp(argv[2], "altbank") == 0)
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cpld_set_altbank();
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else
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cpld_set_defbank();
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} else if (strcmp(argv[1], "dump") == 0) {
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cpld_dump_regs();
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} else {
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rc = cmd_usage(cmdtp);
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}
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|
||||
return rc;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
|
||||
"Reset the board or alternate bank",
|
||||
"reset - hard reset to default bank\n"
|
||||
"cpld reset altbank - reset to alternate bank\n"
|
||||
"cpld dump - display the CPLD registers\n"
|
||||
);
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
/**
|
||||
* Copyright 2014 Freescale Semiconductor
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
*/
|
||||
|
||||
struct cpld_data {
|
||||
u8 cpld_ver; /* 0x00 - CPLD Major Revision Register */
|
||||
u8 cpld_ver_sub; /* 0x01 - CPLD Minor Revision Register */
|
||||
u8 hw_ver; /* 0x02 - Hardware Revision Register */
|
||||
u8 sw_ver; /* 0x03 - Software Revision register */
|
||||
u8 res0[12]; /* 0x04 - 0x0F - not used */
|
||||
u8 reset_ctl1; /* 0x10 - Reset control Register1 */
|
||||
u8 reset_ctl2; /* 0x11 - Reset control Register2 */
|
||||
u8 int_status; /* 0x12 - Interrupt status Register */
|
||||
u8 flash_csr; /* 0x13 - Flash control and status register */
|
||||
u8 fan_ctl_status; /* 0x14 - Fan control and status register */
|
||||
u8 led_ctl_status; /* 0x15 - LED control and status register */
|
||||
u8 sfp_ctl_status; /* 0x16 - SFP control and status register */
|
||||
u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/
|
||||
u8 boot_override; /* 0x18 - Boot override register */
|
||||
u8 boot_config1; /* 0x19 - Boot config override register*/
|
||||
u8 boot_config2; /* 0x1A - Boot config override register*/
|
||||
} cpld_data_t;
|
||||
|
||||
|
||||
/* Pointer to the CPLD register set */
|
||||
|
||||
u8 cpld_read(unsigned int reg);
|
||||
void cpld_write(unsigned int reg, u8 value);
|
||||
|
||||
#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
|
||||
#define CPLD_WRITE(reg, value)\
|
||||
cpld_write(offsetof(struct cpld_data, reg), value)
|
||||
|
||||
/* CPLD on IFC */
|
||||
#define CPLD_LBMAP_MASK 0x3F
|
||||
#define CPLD_BANK_SEL_MASK 0x07
|
||||
#define CPLD_BANK_OVERRIDE 0x40
|
||||
#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
|
||||
#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK 0 */
|
||||
#define CPLD_LBMAP_RESET 0xFF
|
||||
#define CPLD_LBMAP_SHIFT 0x03
|
||||
#define CPLD_BOOT_SEL 0x80
|
||||
|
|
@ -0,0 +1,154 @@
|
|||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#include <hwconfig.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <fsl_ddr_sdram.h>
|
||||
#include <fsl_ddr_dimm_params.h>
|
||||
#include <asm/fsl_law.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
struct board_specific_parameters {
|
||||
u32 n_ranks;
|
||||
u32 datarate_mhz_high;
|
||||
u32 rank_gb;
|
||||
u32 clk_adjust;
|
||||
u32 wrlvl_start;
|
||||
u32 wrlvl_ctl_2;
|
||||
u32 wrlvl_ctl_3;
|
||||
};
|
||||
|
||||
/*
|
||||
* datarate_mhz_high values need to be in ascending order
|
||||
*/
|
||||
static const struct board_specific_parameters udimm0[] = {
|
||||
/*
|
||||
* memory controller 0
|
||||
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
|
||||
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
|
||||
*/
|
||||
{2, 833, 0, 4, 6, 0x06060607, 0x08080807,},
|
||||
{2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
|
||||
{2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
|
||||
{1, 833, 0, 4, 6, 0x06060607, 0x08080807,},
|
||||
{1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
|
||||
{1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
|
||||
{}
|
||||
};
|
||||
|
||||
static const struct board_specific_parameters *udimms[] = {
|
||||
udimm0,
|
||||
};
|
||||
|
||||
void fsl_ddr_board_options(memctl_options_t *popts,
|
||||
dimm_params_t *pdimm,
|
||||
unsigned int ctrl_num)
|
||||
{
|
||||
const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
|
||||
ulong ddr_freq;
|
||||
struct cpu_type *cpu = gd->arch.cpu;
|
||||
|
||||
if (ctrl_num > 1) {
|
||||
printf("Not supported controller number %d\n", ctrl_num);
|
||||
return;
|
||||
}
|
||||
if (!pdimm->n_ranks)
|
||||
return;
|
||||
|
||||
pbsp = udimms[0];
|
||||
|
||||
/* Get clk_adjust according to the board ddr freqency and n_banks
|
||||
* specified in board_specific_parameters table.
|
||||
*/
|
||||
ddr_freq = get_ddr_freq(0) / 1000000;
|
||||
while (pbsp->datarate_mhz_high) {
|
||||
if (pbsp->n_ranks == pdimm->n_ranks &&
|
||||
(pdimm->rank_density >> 30) >= pbsp->rank_gb) {
|
||||
if (ddr_freq <= pbsp->datarate_mhz_high) {
|
||||
popts->clk_adjust = pbsp->clk_adjust;
|
||||
popts->wrlvl_start = pbsp->wrlvl_start;
|
||||
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
|
||||
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
|
||||
goto found;
|
||||
}
|
||||
pbsp_highest = pbsp;
|
||||
}
|
||||
pbsp++;
|
||||
}
|
||||
|
||||
if (pbsp_highest) {
|
||||
printf("Error: board specific timing not found\n");
|
||||
printf("for data rate %lu MT/s\n", ddr_freq);
|
||||
printf("Trying to use the highest speed (%u) parameters\n",
|
||||
pbsp_highest->datarate_mhz_high);
|
||||
popts->clk_adjust = pbsp_highest->clk_adjust;
|
||||
popts->wrlvl_start = pbsp_highest->wrlvl_start;
|
||||
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
|
||||
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
|
||||
} else {
|
||||
panic("DIMM is not supported by this board");
|
||||
}
|
||||
found:
|
||||
debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
|
||||
pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
|
||||
debug("\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, ",
|
||||
pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2);
|
||||
debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3);
|
||||
|
||||
/*
|
||||
* Factors to consider for half-strength driver enable:
|
||||
* - number of DIMMs installed
|
||||
*/
|
||||
popts->half_strength_driver_enable = 0;
|
||||
/*
|
||||
* Write leveling override
|
||||
*/
|
||||
popts->wrlvl_override = 1;
|
||||
popts->wrlvl_sample = 0xf;
|
||||
|
||||
/*
|
||||
* rtt and rtt_wr override
|
||||
*/
|
||||
popts->rtt_override = 0;
|
||||
|
||||
/* Enable ZQ calibration */
|
||||
popts->zq_en = 1;
|
||||
|
||||
/* DHC_EN =1, ODT = 75 Ohm */
|
||||
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_OFF);
|
||||
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF);
|
||||
|
||||
/* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit,
|
||||
* force DDR bus width to 32bit for T1023
|
||||
*/
|
||||
if (cpu->soc_ver == SVR_T1023)
|
||||
popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
|
||||
|
||||
#ifdef CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32
|
||||
/* for DDR bus 32bit test on T1024 */
|
||||
popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
|
||||
#endif
|
||||
}
|
||||
|
||||
phys_size_t initdram(int board_type)
|
||||
{
|
||||
phys_size_t dram_size;
|
||||
|
||||
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
|
||||
puts("Initializing....using SPD\n");
|
||||
|
||||
dram_size = fsl_ddr_sdram();
|
||||
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
|
||||
dram_size *= 0x100000;
|
||||
#else
|
||||
/* DDR has been initialised by first stage boot loader */
|
||||
dram_size = fsl_ddr_sdram_size();
|
||||
#endif
|
||||
return dram_size;
|
||||
}
|
||||
|
|
@ -0,0 +1,100 @@
|
|||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/immap_85xx.h>
|
||||
#include <asm/fsl_law.h>
|
||||
#include <asm/fsl_serdes.h>
|
||||
#include <asm/fsl_portals.h>
|
||||
#include <asm/fsl_liodn.h>
|
||||
#include <malloc.h>
|
||||
#include <fm_eth.h>
|
||||
#include <fsl_mdio.h>
|
||||
#include <miiphy.h>
|
||||
#include <phy.h>
|
||||
#include <asm/fsl_dtsec.h>
|
||||
#include <asm/fsl_serdes.h>
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
#if defined(CONFIG_FMAN_ENET)
|
||||
int i, interface;
|
||||
struct memac_mdio_info dtsec_mdio_info;
|
||||
struct memac_mdio_info tgec_mdio_info;
|
||||
struct mii_dev *dev;
|
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
u32 srds_s1;
|
||||
|
||||
srds_s1 = in_be32(&gur->rcwsr[4]) &
|
||||
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
|
||||
srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
|
||||
|
||||
dtsec_mdio_info.regs =
|
||||
(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
|
||||
|
||||
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
|
||||
|
||||
/* Register the 1G MDIO bus */
|
||||
fm_memac_mdio_init(bis, &dtsec_mdio_info);
|
||||
|
||||
tgec_mdio_info.regs =
|
||||
(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
|
||||
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
|
||||
|
||||
/* Register the 10G MDIO bus */
|
||||
fm_memac_mdio_init(bis, &tgec_mdio_info);
|
||||
|
||||
/* Set the two on-board RGMII PHY address */
|
||||
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
|
||||
fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
|
||||
|
||||
switch (srds_s1) {
|
||||
case 0x95:
|
||||
/* 10G XFI with Aquantia PHY */
|
||||
fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
|
||||
break;
|
||||
default:
|
||||
printf("SerDes protocol 0x%x is not supported on T102xRDB\n",
|
||||
srds_s1);
|
||||
break;
|
||||
}
|
||||
|
||||
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
|
||||
interface = fm_info_get_enet_if(i);
|
||||
switch (interface) {
|
||||
case PHY_INTERFACE_MODE_RGMII:
|
||||
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
|
||||
fm_info_set_mdio(i, dev);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
|
||||
switch (fm_info_get_enet_if(i)) {
|
||||
case PHY_INTERFACE_MODE_XGMII:
|
||||
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
|
||||
fm_info_set_mdio(i, dev);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
cpu_eth_init(bis);
|
||||
#endif /* CONFIG_FMAN_ENET */
|
||||
|
||||
return pci_eth_init(bis);
|
||||
}
|
||||
|
||||
void fdt_fixup_board_enet(void *fdt)
|
||||
{
|
||||
}
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fsl_law.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
struct law_entry law_table[] = {
|
||||
#ifndef CONFIG_SYS_NO_FLASH
|
||||
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_BMAN_MEM_PHYS
|
||||
SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_QMAN_MEM_PHYS
|
||||
SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_CPLD_BASE_PHYS
|
||||
SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_DCSRBAR_PHYS
|
||||
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_NAND_BASE_PHYS
|
||||
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
|
||||
#endif
|
||||
};
|
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table);
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* Copyright 2007-2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <pci.h>
|
||||
#include <asm/fsl_pci.h>
|
||||
#include <libfdt.h>
|
||||
#include <fdt_support.h>
|
||||
#include <asm/fsl_serdes.h>
|
||||
|
||||
void pci_init_board(void)
|
||||
{
|
||||
fsl_pcie_init_board(0);
|
||||
}
|
||||
|
||||
void pci_of_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
FT_FSL_PCI_SETUP;
|
||||
}
|
||||
|
|
@ -0,0 +1,107 @@
|
|||
/* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <malloc.h>
|
||||
#include <ns16550.h>
|
||||
#include <nand.h>
|
||||
#include <i2c.h>
|
||||
#include <mmc.h>
|
||||
#include <fsl_esdhc.h>
|
||||
#include <spi_flash.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
phys_size_t get_effective_memsize(void)
|
||||
{
|
||||
return CONFIG_SYS_L3_SIZE;
|
||||
}
|
||||
|
||||
unsigned long get_board_sys_clk(void)
|
||||
{
|
||||
return CONFIG_SYS_CLK_FREQ;
|
||||
}
|
||||
|
||||
unsigned long get_board_ddr_clk(void)
|
||||
{
|
||||
return CONFIG_DDR_CLK_FREQ;
|
||||
}
|
||||
|
||||
void board_init_f(ulong bootflag)
|
||||
{
|
||||
u32 plat_ratio, sys_clk, ccb_clk;
|
||||
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
|
||||
|
||||
/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
|
||||
memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
|
||||
|
||||
/* Update GD pointer */
|
||||
gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
|
||||
|
||||
console_init_f();
|
||||
|
||||
/* initialize selected port with appropriate baud rate */
|
||||
sys_clk = get_board_sys_clk();
|
||||
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
|
||||
ccb_clk = sys_clk * plat_ratio / 2;
|
||||
|
||||
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
|
||||
ccb_clk / 16 / CONFIG_BAUDRATE);
|
||||
|
||||
#if defined(CONFIG_SPL_MMC_BOOT)
|
||||
puts("\nSD boot...\n");
|
||||
#elif defined(CONFIG_SPL_SPI_BOOT)
|
||||
puts("\nSPI boot...\n");
|
||||
#elif defined(CONFIG_SPL_NAND_BOOT)
|
||||
puts("\nNAND boot...\n");
|
||||
#endif
|
||||
|
||||
relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
|
||||
}
|
||||
|
||||
void board_init_r(gd_t *gd, ulong dest_addr)
|
||||
{
|
||||
bd_t *bd;
|
||||
|
||||
bd = (bd_t *)(gd + sizeof(gd_t));
|
||||
memset(bd, 0, sizeof(bd_t));
|
||||
gd->bd = bd;
|
||||
bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
|
||||
bd->bi_memsize = CONFIG_SYS_L3_SIZE;
|
||||
|
||||
probecpu();
|
||||
get_clocks();
|
||||
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
|
||||
CONFIG_SPL_RELOC_MALLOC_SIZE);
|
||||
|
||||
#ifdef CONFIG_SPL_NAND_BOOT
|
||||
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
|
||||
(uchar *)CONFIG_ENV_ADDR);
|
||||
#endif
|
||||
#ifdef CONFIG_SPL_MMC_BOOT
|
||||
mmc_initialize(bd);
|
||||
mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
|
||||
(uchar *)CONFIG_ENV_ADDR);
|
||||
#endif
|
||||
#ifdef CONFIG_SPL_SPI_BOOT
|
||||
spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
|
||||
(uchar *)CONFIG_ENV_ADDR);
|
||||
#endif
|
||||
|
||||
gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
|
||||
gd->env_valid = 1;
|
||||
|
||||
i2c_init_all();
|
||||
|
||||
gd->ram_size = initdram(0);
|
||||
|
||||
#ifdef CONFIG_SPL_MMC_BOOT
|
||||
mmc_boot();
|
||||
#elif defined(CONFIG_SPL_SPI_BOOT)
|
||||
spi_boot();
|
||||
#elif defined(CONFIG_SPL_NAND_BOOT)
|
||||
nand_boot();
|
||||
#endif
|
||||
}
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
#PBI commands
|
||||
#Initialize CPC1
|
||||
09010000 00200400
|
||||
09138000 00000000
|
||||
091380c0 00000100
|
||||
#Configure CPC1 as 256KB SRAM
|
||||
09010100 00000000
|
||||
09010104 fffc0007
|
||||
09010f00 08000000
|
||||
09010000 80000000
|
||||
#Configure LAW for CPC1
|
||||
09000cd0 00000000
|
||||
09000cd4 fffc0000
|
||||
09000cd8 81000011
|
||||
#Configure alternate space
|
||||
09000010 00000000
|
||||
09000014 ff000000
|
||||
09000018 81000000
|
||||
#Configure SPI controller
|
||||
09110000 80000403
|
||||
09110020 2d170008
|
||||
09110024 00100008
|
||||
09110028 00100008
|
||||
0911002c 00100008
|
||||
#Flush PBL data
|
||||
091380c0 000FFFFF
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
#PBL preamble and RCW header for T1024RDB
|
||||
aa55aa55 010e0100
|
||||
#SerDes Protocol: 0x95
|
||||
#Core/DDR: 1400Mhz/1600MT/s with single source clock
|
||||
0810000c 00000000 00000000 00000000
|
||||
4a800003 80000012 ec027000 21000000
|
||||
00000000 00000000 00000000 00030810
|
||||
00000000 0b005a08 00000000 00000006
|
||||
|
|
@ -0,0 +1,144 @@
|
|||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <i2c.h>
|
||||
#include <netdev.h>
|
||||
#include <linux/compiler.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/immap_85xx.h>
|
||||
#include <asm/fsl_law.h>
|
||||
#include <asm/fsl_serdes.h>
|
||||
#include <asm/fsl_portals.h>
|
||||
#include <asm/fsl_liodn.h>
|
||||
#include <asm/mpc85xx_gpio.h>
|
||||
#include <fm_eth.h>
|
||||
#include "t102xrdb.h"
|
||||
#include "cpld.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
struct cpu_type *cpu = gd->arch.cpu;
|
||||
static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
|
||||
|
||||
printf("Board: %sRDB, ", cpu->name);
|
||||
printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ",
|
||||
CPLD_READ(hw_ver), CPLD_READ(sw_ver));
|
||||
|
||||
#ifdef CONFIG_SDCARD
|
||||
puts("SD/MMC\n");
|
||||
#elif CONFIG_SPIFLASH
|
||||
puts("SPI\n");
|
||||
#else
|
||||
u8 reg;
|
||||
|
||||
reg = CPLD_READ(flash_csr);
|
||||
|
||||
if (reg & CPLD_BOOT_SEL) {
|
||||
puts("NAND\n");
|
||||
} else {
|
||||
reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
|
||||
printf("NOR vBank%d\n", reg);
|
||||
}
|
||||
#endif
|
||||
|
||||
puts("SERDES Reference Clocks:\n");
|
||||
printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_early_init_r(void)
|
||||
{
|
||||
#ifdef CONFIG_SYS_FLASH_BASE
|
||||
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
|
||||
int flash_esel = find_tlb_idx((void *)flashbase, 1);
|
||||
/*
|
||||
* Remap Boot flash region to caching-inhibited
|
||||
* so that flash can be erased properly.
|
||||
*/
|
||||
|
||||
/* Flush d-cache and invalidate i-cache of any FLASH data */
|
||||
flush_dcache();
|
||||
invalidate_icache();
|
||||
if (flash_esel == -1) {
|
||||
/* very unlikely unless something is messed up */
|
||||
puts("Error: Could not find TLB for FLASH BASE\n");
|
||||
flash_esel = 2; /* give our best effort to continue */
|
||||
} else {
|
||||
/* invalidate existing TLB entry for flash + promjet */
|
||||
disable_tlb(flash_esel);
|
||||
}
|
||||
|
||||
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, flash_esel, BOOKE_PAGESZ_256M, 1);
|
||||
#endif
|
||||
|
||||
set_liodns();
|
||||
#ifdef CONFIG_SYS_DPAA_QBMAN
|
||||
setup_portals();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned long get_board_sys_clk(void)
|
||||
{
|
||||
return CONFIG_SYS_CLK_FREQ;
|
||||
}
|
||||
|
||||
unsigned long get_board_ddr_clk(void)
|
||||
{
|
||||
return CONFIG_DDR_CLK_FREQ;
|
||||
}
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
phys_addr_t base;
|
||||
phys_size_t size;
|
||||
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
base = getenv_bootm_low();
|
||||
size = getenv_bootm_size();
|
||||
|
||||
fdt_fixup_memory(blob, (u64)base, (u64)size);
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
pci_of_setup(blob, bd);
|
||||
#endif
|
||||
|
||||
fdt_fixup_liodn(blob);
|
||||
fdt_fixup_dr_usb(blob, bd);
|
||||
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN
|
||||
fdt_fixup_fman_ethernet(blob);
|
||||
fdt_fixup_board_enet(blob);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DEEP_SLEEP
|
||||
void board_mem_sleep_setup(void)
|
||||
{
|
||||
/* does not provide HW signals for power management */
|
||||
CPLD_WRITE(misc_ctl_status, (CPLD_READ(misc_ctl_status) & ~0x40));
|
||||
/* Disable MCKE isolation */
|
||||
gpio_set_value(2, 0);
|
||||
udelay(1);
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __T1024_RDB_H__
|
||||
#define __T1024_RDB_H__
|
||||
|
||||
void fdt_fixup_board_enet(void *blob);
|
||||
void pci_of_setup(void *blob, bd_t *bd);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,117 @@
|
|||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = {
|
||||
/* TLB 0 - for temp stack in cache */
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
|
||||
/* TLB 1 */
|
||||
/* *I*** - Covers boot page */
|
||||
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
|
||||
/*
|
||||
* *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
|
||||
* SRAM is at 0xfffc0000, it covered the 0xfffff000.
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 0, BOOKE_PAGESZ_256K, 1),
|
||||
#else
|
||||
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 0, BOOKE_PAGESZ_4K, 1),
|
||||
#endif
|
||||
|
||||
/* *I*G* - CCSRBAR */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 1, BOOKE_PAGESZ_16M, 1),
|
||||
|
||||
/* *I*G* - Flash, localbus */
|
||||
/* This will be changed to *I*G* after relocation to RAM. */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
|
||||
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
|
||||
0, 2, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
/* *I*G* - PCI */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 3, BOOKE_PAGESZ_1G, 1),
|
||||
|
||||
/* *I*G* - PCI I/O */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 4, BOOKE_PAGESZ_256K, 1),
|
||||
|
||||
/* Bman/Qman */
|
||||
#ifdef CONFIG_SYS_BMAN_MEM_PHYS
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 5, BOOKE_PAGESZ_16M, 1),
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
|
||||
CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 6, BOOKE_PAGESZ_16M, 1),
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_QMAN_MEM_PHYS
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 7, BOOKE_PAGESZ_16M, 1),
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
|
||||
CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 8, BOOKE_PAGESZ_16M, 1),
|
||||
#endif
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_DCSRBAR_PHYS
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 9, BOOKE_PAGESZ_4M, 1),
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_NAND_BASE
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 10, BOOKE_PAGESZ_64K, 1),
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_CPLD_BASE
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 11, BOOKE_PAGESZ_256K, 1),
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 12, BOOKE_PAGESZ_1G, 1),
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
|
||||
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 13, BOOKE_PAGESZ_1G, 1)
|
||||
#endif
|
||||
/* entry 14 and 15 has been used hard coded, they will be disabled
|
||||
* in cpu_init_f, so if needed more, will use entry 16 later.
|
||||
*/
|
||||
};
|
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table);
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
CONFIG_SPL=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
|
||||
+S:CONFIG_PPC=y
|
||||
+S:CONFIG_MPC85xx=y
|
||||
+S:CONFIG_TARGET_T102XRDB=y
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
CONFIG_SPL=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
|
||||
+S:CONFIG_PPC=y
|
||||
+S:CONFIG_MPC85xx=y
|
||||
+S:CONFIG_TARGET_T102XRDB=y
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SECURE_BOOT"
|
||||
CONFIG_PPC=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T102XRDB=y
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
CONFIG_SPL=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
|
||||
+S:CONFIG_PPC=y
|
||||
+S:CONFIG_MPC85xx=y
|
||||
+S:CONFIG_TARGET_T102XRDB=y
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024"
|
||||
CONFIG_PPC=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T102XRDB=y
|
||||
|
|
@ -0,0 +1,896 @@
|
|||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/*
|
||||
* T1024/T1023 RDB board configuration file
|
||||
*/
|
||||
|
||||
#ifndef __T1024RDB_H
|
||||
#define __T1024RDB_H
|
||||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_SYS_GENERIC_BOARD
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
#define CONFIG_BOOKE
|
||||
#define CONFIG_E500 /* BOOKE e500 family */
|
||||
#define CONFIG_E500MC /* BOOKE e500mc family */
|
||||
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
|
||||
#define CONFIG_MP /* support multiple processors */
|
||||
#define CONFIG_PHYS_64BIT
|
||||
#define CONFIG_ENABLE_36BIT_PHYS
|
||||
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_ADDR_MAP 1
|
||||
#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
|
||||
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
|
||||
#define CONFIG_FSL_IFC /* Enable IFC Support */
|
||||
|
||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/* support deep sleep */
|
||||
#define CONFIG_DEEP_SLEEP
|
||||
#define CONFIG_SILENT_CONSOLE
|
||||
|
||||
#ifdef CONFIG_RAMBOOT_PBL
|
||||
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
|
||||
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_rcw.cfg
|
||||
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
|
||||
#define CONFIG_SPL_ENV_SUPPORT
|
||||
#define CONFIG_SPL_SERIAL_SUPPORT
|
||||
#define CONFIG_SPL_FLUSH_IMAGE
|
||||
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
|
||||
#define CONFIG_SPL_LIBGENERIC_SUPPORT
|
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT
|
||||
#define CONFIG_SPL_I2C_SUPPORT
|
||||
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
|
||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
||||
#define CONFIG_SYS_TEXT_BASE 0x00201000
|
||||
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
|
||||
#define CONFIG_SPL_PAD_TO 0x40000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x28000
|
||||
#define RESET_VECTOR_OFFSET 0x27FFC
|
||||
#define BOOT_PAGE_OFFSET 0x27000
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SPL_SKIP_RELOCATE
|
||||
#define CONFIG_SPL_COMMON_INIT_DDR
|
||||
#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_NAND
|
||||
#define CONFIG_SPL_NAND_SUPPORT
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
|
||||
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
|
||||
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
|
||||
#define CONFIG_SPL_NAND_BOOT
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPIFLASH
|
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
|
||||
#define CONFIG_SPL_SPI_SUPPORT
|
||||
#define CONFIG_SPL_SPI_FLASH_SUPPORT
|
||||
#define CONFIG_SPL_SPI_FLASH_MINIMAL
|
||||
#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
|
||||
#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
|
||||
#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
|
||||
#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
|
||||
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
|
||||
#endif
|
||||
#define CONFIG_SPL_SPI_BOOT
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SDCARD
|
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
|
||||
#define CONFIG_SPL_MMC_SUPPORT
|
||||
#define CONFIG_SPL_MMC_MINIMAL
|
||||
#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
|
||||
#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
|
||||
#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
|
||||
#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
|
||||
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
|
||||
#endif
|
||||
#define CONFIG_SPL_MMC_BOOT
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_RAMBOOT_PBL */
|
||||
|
||||
#ifndef CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_TEXT_BASE 0xeff40000
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RESET_VECTOR_ADDRESS
|
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_NO_FLASH
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
|
||||
#endif
|
||||
|
||||
/* PCIe Boot - Master */
|
||||
#define CONFIG_SRIO_PCIE_BOOT_MASTER
|
||||
/*
|
||||
* for slave u-boot IMAGE instored in master memory space,
|
||||
* PHYS must be aligned based on the SIZE
|
||||
*/
|
||||
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
|
||||
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
|
||||
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
|
||||
#else
|
||||
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
|
||||
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
|
||||
#endif
|
||||
/*
|
||||
* for slave UCODE and ENV instored in master memory space,
|
||||
* PHYS must be aligned based on the SIZE
|
||||
*/
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
|
||||
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
|
||||
#else
|
||||
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
|
||||
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
|
||||
#endif
|
||||
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
|
||||
/* slave core release by master*/
|
||||
#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
|
||||
#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
|
||||
|
||||
/* PCIe Boot - Slave */
|
||||
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
|
||||
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
|
||||
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
|
||||
(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
|
||||
/* Set 1M boot space for PCIe boot */
|
||||
#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
|
||||
#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
|
||||
(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
|
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPIFLASH)
|
||||
#define CONFIG_SYS_EXTRA_ENV_RELOC
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
#define CONFIG_ENV_SPI_BUS 0
|
||||
#define CONFIG_ENV_SPI_CS 0
|
||||
#define CONFIG_ENV_SPI_MAX_HZ 10000000
|
||||
#define CONFIG_ENV_SPI_MODE 0
|
||||
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
|
||||
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
|
||||
#define CONFIG_ENV_SECT_SIZE 0x10000
|
||||
#elif defined(CONFIG_SDCARD)
|
||||
#define CONFIG_SYS_EXTRA_ENV_RELOC
|
||||
#define CONFIG_ENV_IS_IN_MMC
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#define CONFIG_ENV_OFFSET (512 * 0x800)
|
||||
#elif defined(CONFIG_NAND)
|
||||
#define CONFIG_SYS_EXTRA_ENV_RELOC
|
||||
#define CONFIG_ENV_IS_IN_NAND
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
|
||||
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
|
||||
#define CONFIG_ENV_IS_IN_REMOTE
|
||||
#define CONFIG_ENV_ADDR 0xffe20000
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#elif defined(CONFIG_ENV_IS_NOWHERE)
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#else
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
unsigned long get_board_sys_clk(void);
|
||||
unsigned long get_board_ddr_clk(void);
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 100000000
|
||||
#define CONFIG_DDR_CLK_FREQ 66660000
|
||||
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default.
|
||||
*/
|
||||
#define CONFIG_SYS_CACHE_STASHING
|
||||
#define CONFIG_BACKSIDE_L2_CACHE
|
||||
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
|
||||
#define CONFIG_BTB /* toggle branch predition */
|
||||
#define CONFIG_DDR_ECC
|
||||
#ifdef CONFIG_DDR_ECC
|
||||
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
|
||||
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x00400000
|
||||
#define CONFIG_SYS_ALT_MEMTEST
|
||||
#define CONFIG_PANIC_HANG /* do not reset board on panic */
|
||||
|
||||
/*
|
||||
* Config the L3 Cache as L3 SRAM
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
|
||||
#define CONFIG_SYS_L3_SIZE (256 << 10)
|
||||
#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
|
||||
#ifdef CONFIG_RAMBOOT_PBL
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
|
||||
#endif
|
||||
#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
|
||||
#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
|
||||
#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
|
||||
#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
|
||||
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_DCSRBAR 0xf0000000
|
||||
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
|
||||
#endif
|
||||
|
||||
/* EEPROM */
|
||||
#define CONFIG_ID_EEPROM
|
||||
#define CONFIG_SYS_I2C_EEPROM_NXID
|
||||
#define CONFIG_SYS_EEPROM_BUS_NUM 0
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
|
||||
|
||||
/*
|
||||
* DDR Setup
|
||||
*/
|
||||
#define CONFIG_VERY_BIG_RAM
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
|
||||
#define CONFIG_DDR_SPD
|
||||
#define CONFIG_SYS_FSL_DDR3
|
||||
|
||||
#define CONFIG_SYS_SPD_BUS_NUM 0
|
||||
#define SPD_EEPROM_ADDRESS 0x51
|
||||
|
||||
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
|
||||
|
||||
/*
|
||||
* IFC Definitions
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_BASE 0xe8000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
|
||||
#else
|
||||
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
|
||||
#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
|
||||
CSPR_PORT_SIZE_16 | \
|
||||
CSPR_MSEL_NOR | \
|
||||
CSPR_V)
|
||||
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
|
||||
|
||||
/* NOR Flash Timing Params */
|
||||
#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
|
||||
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
|
||||
FTIM0_NOR_TEADC(0x5) | \
|
||||
FTIM0_NOR_TEAHC(0x5))
|
||||
#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
|
||||
FTIM1_NOR_TRAD_NOR(0x1A) |\
|
||||
FTIM1_NOR_TSEQRAD_NOR(0x13))
|
||||
#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
|
||||
FTIM2_NOR_TCH(0x4) | \
|
||||
FTIM2_NOR_TWPH(0x0E) | \
|
||||
FTIM2_NOR_TWP(0x1c))
|
||||
#define CONFIG_SYS_NOR_FTIM3 0x0
|
||||
|
||||
#define CONFIG_SYS_FLASH_QUIET_TEST
|
||||
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
|
||||
|
||||
/* CPLD on IFC */
|
||||
#define CONFIG_SYS_CPLD_BASE 0xffdf0000
|
||||
#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
|
||||
#define CONFIG_SYS_CSPR2_EXT (0xf)
|
||||
#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
|
||||
| CSPR_PORT_SIZE_8 \
|
||||
| CSPR_MSEL_GPCM \
|
||||
| CSPR_V)
|
||||
#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
|
||||
#define CONFIG_SYS_CSOR2 0x0
|
||||
|
||||
/* CPLD Timing parameters for IFC CS2 */
|
||||
#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
|
||||
FTIM0_GPCM_TEADC(0x0e) | \
|
||||
FTIM0_GPCM_TEAHC(0x0e))
|
||||
#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
|
||||
FTIM1_GPCM_TRAD(0x1f))
|
||||
#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
|
||||
FTIM2_GPCM_TCH(0x8) | \
|
||||
FTIM2_GPCM_TWP(0x1f))
|
||||
#define CONFIG_SYS_CS2_FTIM3 0x0
|
||||
|
||||
/* NAND Flash on IFC */
|
||||
#define CONFIG_NAND_FSL_IFC
|
||||
#define CONFIG_SYS_NAND_BASE 0xff800000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
|
||||
#else
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
|
||||
#endif
|
||||
#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
|
||||
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
|
||||
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
|
||||
| CSPR_MSEL_NAND /* MSEL = NAND */ \
|
||||
| CSPR_V)
|
||||
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
|
||||
|
||||
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
|
||||
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
|
||||
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
|
||||
| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
|
||||
| CSOR_NAND_PGS_4K /* Page Size = 4K */ \
|
||||
| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
|
||||
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
|
||||
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
|
||||
/* ONFI NAND Flash mode0 Timing Params */
|
||||
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
|
||||
FTIM0_NAND_TWP(0x18) | \
|
||||
FTIM0_NAND_TWCHT(0x07) | \
|
||||
FTIM0_NAND_TWH(0x0a))
|
||||
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
|
||||
FTIM1_NAND_TWBE(0x39) | \
|
||||
FTIM1_NAND_TRR(0x0e) | \
|
||||
FTIM1_NAND_TRP(0x18))
|
||||
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
|
||||
FTIM2_NAND_TREH(0x0a) | \
|
||||
FTIM2_NAND_TWHRE(0x1e))
|
||||
#define CONFIG_SYS_NAND_FTIM3 0x0
|
||||
|
||||
#define CONFIG_SYS_NAND_DDR_LAW 11
|
||||
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_MTD_NAND_VERIFY_WRITE
|
||||
#define CONFIG_CMD_NAND
|
||||
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
|
||||
|
||||
#if defined(CONFIG_NAND)
|
||||
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
|
||||
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
|
||||
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
|
||||
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
|
||||
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
|
||||
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
|
||||
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
|
||||
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
|
||||
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
|
||||
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
|
||||
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
|
||||
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
|
||||
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
|
||||
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
|
||||
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
|
||||
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
|
||||
#else
|
||||
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
|
||||
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
|
||||
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
|
||||
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
|
||||
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
|
||||
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
|
||||
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
|
||||
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
|
||||
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
|
||||
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
|
||||
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
|
||||
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
|
||||
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
|
||||
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
|
||||
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
|
||||
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
|
||||
#else
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_RAMBOOT_PBL)
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_R
|
||||
#define CONFIG_MISC_INIT_R
|
||||
|
||||
#define CONFIG_HWCONFIG
|
||||
|
||||
/* define to use L1 as initial stack */
|
||||
#define CONFIG_L1_INIT_RAM
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
|
||||
/* The assembler doesn't like typecast */
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
|
||||
((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
|
||||
#else
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
|
||||
#endif
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
|
||||
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
|
||||
|
||||
/* Serial Port */
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
|
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
|
||||
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
|
||||
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
|
||||
|
||||
/* Use the HUSH parser */
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
|
||||
/* Video */
|
||||
#undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */
|
||||
#ifdef CONFIG_FSL_DIU_FB
|
||||
#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
|
||||
#define CONFIG_VIDEO
|
||||
#define CONFIG_CMD_BMP
|
||||
#define CONFIG_CFB_CONSOLE
|
||||
#define CONFIG_VIDEO_SW_CURSOR
|
||||
#define CONFIG_VGA_AS_SINGLE_DEVICE
|
||||
#define CONFIG_VIDEO_LOGO
|
||||
#define CONFIG_VIDEO_BMP_LOGO
|
||||
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
|
||||
/*
|
||||
* With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
|
||||
* disable empty flash sector detection, which is I/O-intensive.
|
||||
*/
|
||||
#undef CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
#endif
|
||||
|
||||
/* pass open firmware flat tree */
|
||||
#define CONFIG_OF_LIBFDT
|
||||
#define CONFIG_OF_BOARD_SETUP
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS
|
||||
|
||||
/* new uImage format support */
|
||||
#define CONFIG_FIT
|
||||
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
|
||||
|
||||
#define I2C_MUX_PCA_ADDR 0x77
|
||||
#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
|
||||
|
||||
|
||||
/* I2C bus multiplexer */
|
||||
#define I2C_MUX_CH_DEFAULT 0x8
|
||||
|
||||
/*
|
||||
* RTC configuration
|
||||
*/
|
||||
#define RTC
|
||||
#define CONFIG_RTC_DS1337 1
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
|
||||
|
||||
/*
|
||||
* eSPI - Enhanced SPI
|
||||
*/
|
||||
#define CONFIG_FSL_ESPI
|
||||
#define CONFIG_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH_STMICRO
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_SPI_FLASH_BAR
|
||||
#define CONFIG_SF_DEFAULT_SPEED 10000000
|
||||
#define CONFIG_SF_DEFAULT_MODE 0
|
||||
|
||||
/*
|
||||
* General PCIe
|
||||
* Memory space is mapped 1-1, but I/O space must start from 0.
|
||||
*/
|
||||
#define CONFIG_PCI /* Enable PCI/PCIE */
|
||||
#define CONFIG_PCIE1 /* PCIE controler 1 */
|
||||
#define CONFIG_PCIE2 /* PCIE controler 2 */
|
||||
#define CONFIG_PCIE3 /* PCIE controler 3 */
|
||||
#ifdef CONFIG_PPC_T1040
|
||||
#define CONFIG_PCIE4 /* PCIE controler 4 */
|
||||
#endif
|
||||
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
|
||||
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
||||
#define CONFIG_PCI_INDIRECT_BRIDGE
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
|
||||
#ifdef CONFIG_PCIE1
|
||||
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
|
||||
#else
|
||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
|
||||
#endif
|
||||
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
|
||||
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
|
||||
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
|
||||
#else
|
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
|
||||
#endif
|
||||
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
|
||||
#endif
|
||||
|
||||
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
|
||||
#ifdef CONFIG_PCIE2
|
||||
#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
|
||||
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
|
||||
#else
|
||||
#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
|
||||
#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
|
||||
#endif
|
||||
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
|
||||
#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
|
||||
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
|
||||
#else
|
||||
#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
|
||||
#endif
|
||||
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
|
||||
#endif
|
||||
|
||||
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
|
||||
#ifdef CONFIG_PCIE3
|
||||
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
|
||||
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
|
||||
#else
|
||||
#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
|
||||
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
|
||||
#endif
|
||||
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
|
||||
#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
|
||||
#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
|
||||
#else
|
||||
#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
|
||||
#endif
|
||||
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
|
||||
#endif
|
||||
|
||||
/* controller 4, Base address 203000, to be removed */
|
||||
#ifdef CONFIG_PCIE4
|
||||
#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
|
||||
#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
|
||||
#else
|
||||
#define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000
|
||||
#define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000
|
||||
#endif
|
||||
#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
|
||||
#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
|
||||
#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
|
||||
#else
|
||||
#define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000
|
||||
#endif
|
||||
#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
|
||||
#endif
|
||||
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
#define CONFIG_E1000
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
/*
|
||||
* USB
|
||||
*/
|
||||
#define CONFIG_HAS_FSL_DR_USB
|
||||
|
||||
#ifdef CONFIG_HAS_FSL_DR_USB
|
||||
#define CONFIG_USB_EHCI
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_USB_EHCI_FSL
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
#define CONFIG_CMD_EXT2
|
||||
#endif
|
||||
|
||||
/*
|
||||
* SDHC
|
||||
*/
|
||||
#define CONFIG_MMC
|
||||
#ifdef CONFIG_MMC
|
||||
#define CONFIG_FSL_ESDHC
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#endif
|
||||
|
||||
/* Qman/Bman */
|
||||
#ifndef CONFIG_NOBQFMAN
|
||||
#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
|
||||
#define CONFIG_SYS_BMAN_NUM_PORTALS 25
|
||||
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
|
||||
#else
|
||||
#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
|
||||
#endif
|
||||
#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
|
||||
#define CONFIG_SYS_QMAN_NUM_PORTALS 25
|
||||
#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
|
||||
#else
|
||||
#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
|
||||
#endif
|
||||
#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
|
||||
|
||||
#define CONFIG_SYS_DPAA_FMAN
|
||||
|
||||
#define CONFIG_QE
|
||||
#define CONFIG_U_QE
|
||||
/* Default address of microcode for the Linux FMan driver */
|
||||
#if defined(CONFIG_SPIFLASH)
|
||||
/*
|
||||
* env is stored at 0x100000, sector size is 0x10000, ucode is stored after
|
||||
* env, so we got 0x110000.
|
||||
*/
|
||||
#define CONFIG_SYS_QE_FW_IN_SPIFLASH
|
||||
#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
|
||||
#define CONFIG_SYS_QE_FW_ADDR 0x130000
|
||||
#elif defined(CONFIG_SDCARD)
|
||||
/*
|
||||
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
|
||||
* about 1MB (2048 blocks), Env is stored after the image, and the env size is
|
||||
* 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
|
||||
*/
|
||||
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
|
||||
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
|
||||
#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
|
||||
#elif defined(CONFIG_NAND)
|
||||
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
|
||||
#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
|
||||
#define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
|
||||
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
|
||||
/*
|
||||
* Slave has no ucode locally, it can fetch this from remote. When implementing
|
||||
* in two corenet boards, slave's ucode could be stored in master's memory
|
||||
* space, the address can be mapped from slave TLB->slave LAW->
|
||||
* slave SRIO or PCIE outbound window->master inbound window->
|
||||
* master LAW->the ucode address in master's memory space.
|
||||
*/
|
||||
#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
|
||||
#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
|
||||
#else
|
||||
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
|
||||
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
|
||||
#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
|
||||
#endif
|
||||
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
|
||||
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
|
||||
#endif /* CONFIG_NOBQFMAN */
|
||||
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN
|
||||
#define CONFIG_FMAN_ENET
|
||||
#define CONFIG_PHYLIB_10G
|
||||
#define CONFIG_PHY_REALTEK
|
||||
#define RGMII_PHY1_ADDR 0x2
|
||||
#define RGMII_PHY2_ADDR 0x6
|
||||
#define FM1_10GEC1_PHY_ADDR 0x1
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FMAN_ENET
|
||||
#define CONFIG_MII /* MII PHY management */
|
||||
#define CONFIG_ETHPRIME "FM1@DTSEC4"
|
||||
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Dynamic MTD Partition support with mtdparts
|
||||
*/
|
||||
#ifndef CONFIG_SYS_NO_FLASH
|
||||
#define CONFIG_MTD_DEVICE
|
||||
#define CONFIG_MTD_PARTITIONS
|
||||
#define CONFIG_CMD_MTDPARTS
|
||||
#define CONFIG_FLASH_CFI_MTD
|
||||
#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
|
||||
"spi0=spife110000.1"
|
||||
#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
|
||||
"128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
|
||||
"5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \
|
||||
"1m(uboot),5m(kernel),128k(dtb),-(user)"
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#define CONFIG_LOADS_ECHO /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_ERRATA
|
||||
#define CONFIG_CMD_GREPENV
|
||||
#define CONFIG_CMD_IRQ
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_ECHO
|
||||
#define CONFIG_CMD_REGINFO
|
||||
#define CONFIG_CMD_SETEXPR
|
||||
#define CONFIG_CMD_BDI
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_NET
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
|
||||
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#ifdef CONFIG_CMD_KGDB
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 64 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
|
||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
|
||||
|
||||
#ifdef CONFIG_CMD_KGDB
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Environment Configuration
|
||||
*/
|
||||
#define CONFIG_ROOTPATH "/opt/nfsroot"
|
||||
#define CONFIG_BOOTFILE "uImage"
|
||||
#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
|
||||
#define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */
|
||||
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define __USB_PHY_TYPE utmi
|
||||
|
||||
#ifdef CONFIG_PPC_T1024
|
||||
#define CONFIG_BOARDNAME "t1024rdb"
|
||||
#else
|
||||
#define CONFIG_BOARDNAME "t1023rdb"
|
||||
#endif
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
|
||||
"bank_intlv=cs0_cs1\0" \
|
||||
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
|
||||
"ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
|
||||
"fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \
|
||||
__stringify(CONFIG_BOARDNAME) ".dtb\0" \
|
||||
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
|
||||
"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
|
||||
"bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
|
||||
"netdev=eth0\0" \
|
||||
"tftpflash=tftpboot $loadaddr $uboot && " \
|
||||
"protect off $ubootaddr +$filesize && " \
|
||||
"erase $ubootaddr +$filesize && " \
|
||||
"cp.b $loadaddr $ubootaddr $filesize && " \
|
||||
"protect on $ubootaddr +$filesize && " \
|
||||
"cmp.b $loadaddr $ubootaddr $filesize\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"ramdiskaddr=2000000\0" \
|
||||
"fdtaddr=c00000\0" \
|
||||
"bdev=sda3\0"
|
||||
|
||||
#define CONFIG_LINUX \
|
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"setenv ramdiskaddr 0x02000000;" \
|
||||
"setenv fdtaddr 0x00c00000;" \
|
||||
"setenv loadaddr 0x1000000;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_LINUX
|
||||
|
||||
#ifdef CONFIG_SECURE_BOOT
|
||||
#include <asm/fsl_secure_boot.h>
|
||||
#endif
|
||||
|
||||
#endif /* __T1024RDB_H */
|
||||
Loading…
Reference in New Issue