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ppc4xx: Cleanup Boot/FLASH TLB reassignment for PPC440/460

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Background Info:
Some PPC440/460 boards have caches enabled in the Boot/FLASH TLB (via
init.S) to speed up the boot process. In relocate_code (start.S) the
cache inhibit attribute for this TLB is set to disable cache. This is
needed for the CFI FLASH driver.

This patch now cleans this code up:
- CONFIG_SYS_TLB_FOR_BOOT_FLASH is defined to 0 (default TLB) if not
  defined in the top of this file. This way, we can remove an ugly
  #ifdef in this code.
- Replace complex "#if defined(CONFIG_440EP) || defined(CONFIG_GR)..."
  statement with "#if defined(CONFIG_440)".
- Remove unnecessary cache invalidate calls resulting in faster bootup.

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2010-05-27 16:45:20 +02:00
parent 2909ac03f4
commit 4978e60584
1 changed files with 6 additions and 15 deletions
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21
arch/powerpc/cpu/ppc4xx/start.S
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@ -207,6 +207,10 @@
(0x00000000) (0x00000000)
#endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */ #endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */
#if !defined(CONFIG_SYS_TLB_FOR_BOOT_FLASH)
#define CONFIG_SYS_TLB_FOR_BOOT_FLASH 0 /* use TLB 0 as default */
#endif
#define function_prolog(func_name) .text; \ #define function_prolog(func_name) .text; \
.align 2; \ .align 2; \
.globl func_name; \ .globl func_name; \
@ -1457,34 +1461,21 @@ relocate_code:
isync isync
#endif /* CONFIG_SYS_INIT_RAM_DCACHE */ #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_460SX)
/* /*
* On some 440er platforms the cache is enabled in the first TLB (Boot-CS) * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
* to speed up the boot process. Now this cache needs to be disabled. * to speed up the boot process. Now this cache needs to be disabled.
*/ */
iccci 0,0 /* Invalidate inst cache */ #if defined(CONFIG_440)
dccci 0,0 /* Invalidate data cache, now no longer our stack */
sync
isync
/* Clear all potential pending exceptions */ /* Clear all potential pending exceptions */
mfspr r1,SPRN_MCSR mfspr r1,SPRN_MCSR
mtspr SPRN_MCSR,r1 mtspr SPRN_MCSR,r1
#ifdef CONFIG_SYS_TLB_FOR_BOOT_FLASH
addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */ addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */
#else
addi r1,r0,0x0000 /* Default TLB entry is #0 */
#endif /* CONFIG_SYS_TLB_FOR_BOOT_FLASH */
tlbre r0,r1,0x0002 /* Read contents */ tlbre r0,r1,0x0002 /* Read contents */
ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */ ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
tlbwe r0,r1,0x0002 /* Save it out */ tlbwe r0,r1,0x0002 /* Save it out */
sync sync
isync isync
#endif /* defined(CONFIG_440EP) || ... || defined(CONFIG_460GT) */ #endif /* defined(CONFIG_440) */
mr r1, r3 /* Set new stack pointer */ mr r1, r3 /* Set new stack pointer */
mr r9, r4 /* Save copy of Init Data pointer */ mr r9, r4 /* Save copy of Init Data pointer */
mr r10, r5 /* Save copy of Destination Address */ mr r10, r5 /* Save copy of Destination Address */