powerpc: ep8248: remove orphan board
This board has been orphan for a while. (Emails to its maintainer have been bouncing.) Because MPC82xx family is old enough, nobody would pick up the maintainership on it. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denx <wd@denx.de>utp
Masahiro Yamada
Tom Rini
parent
80bae39aa3
commit
49ad566dfa
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@ -1,8 +0,0 @@
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#
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# (C) Copyright 2001-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := ep8248.o
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@ -1,254 +0,0 @@
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/*
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* Copyright (C) 2004 Arabella Software Ltd.
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* Yuli Barcohen <yuli@arabellasw.com>
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*
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* Support for Embedded Planet EP8248 boards.
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* Tested on EP8248E.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <mpc8260.h>
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#include <ioports.h>
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/*
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* I/O Port configuration table
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*
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* if conf is 1, then that port pin will be configured at boot time
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* according to the five values podr/pdir/ppar/psor/pdat for that entry
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*/
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#define CONFIG_SYS_FCC1 (CONFIG_ETHER_ON_FCC1 == 1)
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#define CONFIG_SYS_FCC2 (CONFIG_ETHER_ON_FCC2 == 1)
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const iop_conf_t iop_conf_tab[4][32] = {
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/* Port A */
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{ /* conf ppar psor pdir podr pdat */
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/* PA31 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
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/* PA30 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
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/* PA29 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
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/* PA28 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
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/* PA27 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
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/* PA26 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
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/* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
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/* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
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/* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
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/* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
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/* PA21 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
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/* PA20 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
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/* PA19 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
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/* PA18 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
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/* PA17 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
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/* PA16 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
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/* PA15 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
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/* PA14 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
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/* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
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/* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
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/* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
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/* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
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/* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TxD */
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/* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RxD */
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/* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
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/* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
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/* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
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/* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
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/* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
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/* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
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/* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
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/* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */
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},
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/* Port B */
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{ /* conf ppar psor pdir podr pdat */
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/* PB31 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
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/* PB30 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
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/* PB29 */ { CONFIG_SYS_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
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/* PB28 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
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/* PB27 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
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/* PB26 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
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/* PB25 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
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/* PB24 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
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/* PB23 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
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/* PB22 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
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/* PB21 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
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/* PB20 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
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/* PB19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
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/* PB18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
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/* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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/* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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/* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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/* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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/* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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/* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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/* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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/* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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/* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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/* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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/* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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/* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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/* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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/* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
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},
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/* Port C */
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{ /* conf ppar psor pdir podr pdat */
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/* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
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/* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
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/* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
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/* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
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/* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
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/* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
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/* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
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/* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
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/* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
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/* PC22 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 RxClk (CLK10) */
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/* PC21 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 TxClk (CLK11) */
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/* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
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/* PC19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 RxClk (CLK13) */
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/* PC18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 TxClk (CLK14) */
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/* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
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/* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
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/* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
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/* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
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/* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
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/* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
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/* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
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/* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
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/* PC9 */ { 1, 0, 0, 1, 0, 1 }, /* MDIO */
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/* PC8 */ { 1, 0, 0, 1, 0, 1 }, /* MDC */
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/* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
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/* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
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/* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TxD */
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/* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RxD */
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/* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
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/* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
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/* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
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/* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
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},
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/* Port D */
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{ /* conf ppar psor pdir podr pdat */
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/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RxD */
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/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TxD */
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/* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
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/* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
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/* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
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/* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */
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/* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
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/* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
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/* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
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/* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */
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/* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */
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/* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */
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/* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
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/* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
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/* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
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/* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
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/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
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/* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
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/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
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/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
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/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
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/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
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/* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */
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/* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */
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/* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
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/* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
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/* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
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/* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
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/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
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/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
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}
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};
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int board_early_init_f (void)
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{
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vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
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bcsr[4] |= 0x30; /* Turn the LEDs off */
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#if defined(CONFIG_CONS_ON_SMC) || defined(CONFIG_KGDB_ON_SMC)
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bcsr[6] |= 0x10;
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#endif
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#if defined(CONFIG_CONS_ON_SCC) || defined(CONFIG_KGDB_ON_SCC)
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bcsr[7] |= 0x10;
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#endif
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#if CONFIG_SYS_FCC1
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bcsr[8] |= 0xC0;
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#endif /* CONFIG_SYS_FCC1 */
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#if CONFIG_SYS_FCC2
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bcsr[8] |= 0x30;
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#endif /* CONFIG_SYS_FCC2 */
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return 0;
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}
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phys_size_t initdram(int board_type)
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{
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vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
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long int msize = 16L << (bcsr[2] & 3);
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#ifndef CONFIG_SYS_RAMBOOT
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile memctl8260_t *memctl = &immap->im_memctl;
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vu_char *ramaddr = (vu_char *)CONFIG_SYS_SDRAM_BASE;
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uchar c = 0xFF;
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uint psdmr = CONFIG_SYS_PSDMR;
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int i;
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immap->im_siu_conf.sc_ppc_acr = 0x02;
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immap->im_siu_conf.sc_ppc_alrh = 0x30126745;
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immap->im_siu_conf.sc_tescr1 = 0x00004000;
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memctl->memc_mptpr = CONFIG_SYS_MPTPR;
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/* Initialise 60x bus SDRAM */
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memctl->memc_psrt = CONFIG_SYS_PSRT;
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memctl->memc_or1 = CONFIG_SYS_SDRAM_OR;
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memctl->memc_br1 = CONFIG_SYS_SDRAM_BR;
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memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
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*ramaddr = c;
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memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
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for (i = 0; i < 8; i++)
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*ramaddr = c;
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memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */
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*ramaddr = c;
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memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */
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*ramaddr = c;
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#endif /* !CONFIG_SYS_RAMBOOT */
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/* Return total 60x bus SDRAM size */
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return msize * 1024 * 1024;
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}
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int checkboard(void)
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{
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vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
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puts("Board: ");
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switch (bcsr[0]) {
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case 0x0C:
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printf("EP8248E 1.0 CPLD revision %d\n", bcsr[1]);
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break;
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default:
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printf("unknown: ID=%02X\n", bcsr[0]);
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}
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return 0;
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}
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#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup( blob, bd);
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}
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#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
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@ -1242,7 +1242,6 @@ Orphan powerpc mpc5xxx - matrix_vision mvsmr
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Orphan powerpc mpc824x - - hidden_dragon HIDDEN_DRAGON - Yusdi Santoso <yusdi_santoso@adaptec.com>
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Orphan powerpc mpc824x - etin - debris - Sangmoon Kim <dogoil@etinsys.com>
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Orphan powerpc mpc824x - etin - kvme080 - Sangmoon Kim <dogoil@etinsys.com>
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Orphan powerpc mpc8260 - - ep8248 ep8248 - Yuli Barcohen <yuli@arabellasw.com>
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Orphan powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK - Anton Vorontsov <avorontsov@ru.mvista.com>
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Orphan powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK_33 MPC8360ERDK:CLKIN_33MHZ Anton Vorontsov <avorontsov@ru.mvista.com>
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Orphan powerpc mpc83xx - matrix_vision mergerbox MERGERBOX - Andre Schwarz <andre.schwarz@matrix-vision.de>
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@ -11,6 +11,7 @@ easily if here is something they might want to dig for...
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Board Arch CPU Commit Removed Last known maintainer/contact
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=================================================================================================
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ep8248 powerpc mpc8260 - - Yuli Barcohen <yuli@arabellasw.com>
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ispan powerpc mpc8260 - - Yuli Barcohen <yuli@arabellasw.com>
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rattler powerpc mpc8260 - - Yuli Barcohen <yuli@arabellasw.com>
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zpc1900 powerpc mpc8260 - - Yuli Barcohen <yuli@arabellasw.com>
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@ -54,8 +54,6 @@ typedef volatile unsigned char vu_char;
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#include <asm/immap_512x.h>
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#elif defined(CONFIG_MPC8260)
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#if defined(CONFIG_MPC8247) \
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|| defined(CONFIG_MPC8248) \
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|| defined(CONFIG_MPC8271) \
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|| defined(CONFIG_MPC8272)
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#define CONFIG_MPC8272_FAMILY 1
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#endif
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@ -1,253 +0,0 @@
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/*
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* Copyright (C) 2004 Arabella Software Ltd.
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* Yuli Barcohen <yuli@arabellasw.com>
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*
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* U-Boot configuration for Embedded Planet EP8248 boards.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_MPC8248
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#define CPU_ID_STR "MPC8248"
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#define CONFIG_EP8248 /* Embedded Planet EP8248 board */
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#define CONFIG_SYS_TEXT_BASE 0xFFF00000
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
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#define CONFIG_ENV_OVERWRITE
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/*
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* Select serial console configuration
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*
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* If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
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* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
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* for SCC).
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*/
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#define CONFIG_CONS_ON_SMC /* Console is on SMC */
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||||
#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
|
||||
#undef CONFIG_CONS_NONE /* It's not on external UART */
|
||||
#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
|
||||
|
||||
#define CONFIG_SYS_BCSR 0xFA000000
|
||||
|
||||
/* Pass open firmware flat device tree */
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
#define CONFIG_OF_BOARD_SETUP 1
|
||||
|
||||
#define OF_TBCLK (bd->bi_busfreq / 4)
|
||||
#define OF_STDOUT_PATH "/soc/cpm/serial <at> 11a80"
|
||||
|
||||
/* Select ethernet configuration */
|
||||
#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
|
||||
#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
|
||||
#undef CONFIG_ETHER_NONE /* No external Ethernet */
|
||||
|
||||
#define CONFIG_SYS_CPMFCR_RAMTYPE 0
|
||||
#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
|
||||
|
||||
#define CONFIG_HAS_ETH0
|
||||
#define CONFIG_ETHER_ON_FCC1 1
|
||||
/* - Rx clock is CLK10
|
||||
* - Tx clock is CLK11
|
||||
* - BDs/buffers on 60x bus
|
||||
* - Full duplex
|
||||
*/
|
||||
#define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
|
||||
#define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK10 | CMXFCR_TF1CS_CLK11)
|
||||
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_ETHER_ON_FCC2 1
|
||||
/* - Rx clock is CLK13
|
||||
* - Tx clock is CLK14
|
||||
* - BDs/buffers on 60x bus
|
||||
* - Full duplex
|
||||
*/
|
||||
#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
|
||||
#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
|
||||
|
||||
#define CONFIG_MII /* MII PHY management */
|
||||
#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
|
||||
/*
|
||||
* GPIO pins used for bit-banged MII communications
|
||||
*/
|
||||
#define MDIO_PORT 0 /* Not used - implemented in BCSR */
|
||||
|
||||
#define MDIO_ACTIVE (*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFB)
|
||||
#define MDIO_TRISTATE (*(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x04)
|
||||
#define MDIO_READ (*(vu_char *)(CONFIG_SYS_BCSR + 8) & 1)
|
||||
|
||||
#define MDIO(bit) if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x01; \
|
||||
else *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFE
|
||||
|
||||
#define MDC(bit) if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x02; \
|
||||
else *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFD
|
||||
|
||||
#define MIIDELAY udelay(1)
|
||||
|
||||
#ifndef CONFIG_8260_CLKIN
|
||||
#define CONFIG_8260_CLKIN 66000000 /* in Hz */
|
||||
#endif
|
||||
|
||||
#define CONFIG_BAUDRATE 38400
|
||||
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_ECHO
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_IMMAP
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_PING
|
||||
|
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
#define CONFIG_BOOTCOMMAND "bootm FF860000" /* autoboot command */
|
||||
#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=phys:7M(root),-(root)ro"
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
|
||||
#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
|
||||
#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
|
||||
#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */
|
||||
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
|
||||
#endif
|
||||
|
||||
#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
|
||||
#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
|
||||
|
||||
#define CONFIG_SYS_FLASH_BASE 0xFF800000
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
|
||||
|
||||
#define CONFIG_SYS_DIRECT_FLASH_TFTP
|
||||
|
||||
#if defined(CONFIG_CMD_JFFS2)
|
||||
#define CONFIG_SYS_JFFS2_FIRST_BANK 0
|
||||
#define CONFIG_SYS_JFFS2_NUM_BANKS CONFIG_SYS_MAX_FLASH_BANKS
|
||||
#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0
|
||||
#define CONFIG_SYS_JFFS2_LAST_SECTOR 62
|
||||
#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
|
||||
#define CONFIG_SYS_JFFS_CUSTOM_PART
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CMD_I2C)
|
||||
#define CONFIG_HARD_I2C 1 /* To enable I2C support */
|
||||
#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */
|
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
|
||||
#endif /* CONFIG_ENV_IS_IN_FLASH */
|
||||
|
||||
#define CONFIG_SYS_DEFAULT_IMMR 0x00010000
|
||||
|
||||
#define CONFIG_SYS_IMMR 0xF0000000
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
/* Hard reset configuration word */
|
||||
#define CONFIG_SYS_HRCW_MASTER 0x0C40025A /* Not used - provided by FPGA */
|
||||
/* No slaves */
|
||||
#define CONFIG_SYS_HRCW_SLAVE1 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE2 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE3 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE4 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE5 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE6 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE7 0
|
||||
|
||||
#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_HID0_INIT 0
|
||||
#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
|
||||
|
||||
#define CONFIG_SYS_HID2 0
|
||||
|
||||
#define CONFIG_SYS_SIUMCR 0x01240200
|
||||
#define CONFIG_SYS_SYPCR 0xFFFF0683
|
||||
#define CONFIG_SYS_BCR 0x00000000
|
||||
#define CONFIG_SYS_SCCR SCCR_DFBRG01
|
||||
|
||||
#define CONFIG_SYS_RMR RMR_CSRE
|
||||
#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
|
||||
#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
|
||||
#define CONFIG_SYS_RCCR 0
|
||||
|
||||
#define CONFIG_SYS_MPTPR 0x1300
|
||||
#define CONFIG_SYS_PSDMR 0x82672522
|
||||
#define CONFIG_SYS_PSRT 0x4B
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_SDRAM_BR (CONFIG_SYS_SDRAM_BASE | 0x00001841)
|
||||
#define CONFIG_SYS_SDRAM_OR 0xFF0030C0
|
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001801)
|
||||
#define CONFIG_SYS_OR0_PRELIM 0xFF8008C2
|
||||
#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_BCSR | 0x00000801)
|
||||
#define CONFIG_SYS_OR2_PRELIM 0xFFF00864
|
||||
|
||||
#define CONFIG_SYS_RESET_ADDRESS 0xC0000000
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -21,10 +21,6 @@
|
|||
#if defined(CONFIG_MPC8272_FAMILY)
|
||||
#ifdef CONFIG_MPC8247
|
||||
#define CPU_ID_STR "MPC8247"
|
||||
#elif defined CONFIG_MPC8248
|
||||
#define CPU_ID_STR "MPC8248"
|
||||
#elif defined CONFIG_MPC8271
|
||||
#define CPU_ID_STR "MPC8271"
|
||||
#else
|
||||
#define CPU_ID_STR "MPC8272"
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue