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arm: socfpga: sockit: Use more relaxed DRAM timings 

The currently present DRAM timings generated from GHRD 14.0 did
not work on SoCkit rev. D because they were too tight. Load the
DRAM timings from GHRD 13.0 which are more relaxed and work with
SoCkit rev. D.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
utp
Marek Vasut 2016-03-20 18:02:44 +01:00
parent 5f79d00840
commit 4d74c02724
3 changed files with 80 additions and 80 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

116
board/terasic/sockit/qts/iocsr_config.h
View File

@ -181,17 +181,17 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x00001000, 0x00001000,
0xA0000034, 0xA0000034,
0x0D000001, 0x0D000001,
0x40680208, 0xE0680B2C,
0x41034051, 0x20834038,
0x12481A00, 0x11441A00,
0x802080D0, 0x80B2C0D0,
0x34051406, 0x34038E06,
0x01A02490, 0x01A00208,
0x080D0000, 0x2C0D0000,
0x51406802, 0x38E0680B,
0x02490340, 0x00208340,
0xD000001A, 0xD000001A,
0x0680A280, 0x0680B2C0,
0x10040000, 0x10040000,
0x00200000, 0x00200000,
0x10040000, 0x10040000,
@ -255,17 +255,17 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x00001000, 0x00001000,
0xA0000034, 0xA0000034,
0x0D000001, 0x0D000001,
0x40680208, 0xE0680B2C,
0x49034051, 0x20834038,
0x12481A02, 0x11441A00,
0x80A280D0, 0x80B2C0D0,
0x34030C06, 0x34038E06,
0x01A00040, 0x01A00040,
0x280D0002, 0x2C0D0002,
0x5140680A, 0x38E0680B,
0x02490340, 0x00208340,
0xD012481A, 0xD001041A,
0x0680A280, 0x0680B2C0,
0x10040000, 0x10040000,
0x00200000, 0x00200000,
0x10040000, 0x10040000,
@ -330,18 +330,18 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x14F3690D, 0x14F3690D,
0x1A041414, 0x1A041414,
0x00D00000, 0x00D00000,
0x04864000, 0x18864000,
0x59647A01, 0x49247A06,
0xD32CA3DE, 0xABCF23D7,
0xF551451E, 0xF7DE791E,
0x034CD348, 0x0356E388,
0x821A0000, 0x821A0000,
0x0000D000, 0x0000D000,
0x05140680, 0x05960680,
0xD669A47A, 0xD749247A,
0x1ED32CA3, 0x1EABCF23,
0x48F55E79, 0x88F7DE79,
0x00034C92, 0x000356E3,
0x00080200, 0x00080200,
0x00001000, 0x00001000,
0x00080200, 0x00080200,
@ -404,18 +404,18 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x14F3690D, 0x14F3690D,
0x1A041414, 0x1A041414,
0x00D00000, 0x00D00000,
0x14864000, 0x18864000,
0x59647A05, 0x49247A06,
0x9228A3DE, 0xABCF23D7,
0xF65E791E, 0xF7DE791E,
0x034CD348, 0x0356E388,
0x821A0186, 0x821A01C7,
0x0000D000, 0x0000D000,
0x00000680, 0x00000680,
0xD669A47A, 0xD749247A,
0x1E9228A3, 0x1EABCF23,
0x48F65E79, 0x88F7DE79,
0x00034CD3, 0x000356E3,
0x00080200, 0x00080200,
0x00001000, 0x00001000,
0x00080200, 0x00080200,
@ -478,18 +478,18 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x14F3690D, 0x14F3690D,
0x1A041414, 0x1A041414,
0x00D00000, 0x00D00000,
0x0C864000, 0x18864000,
0x79E47A03, 0x49247A06,
0xB2AAA3D1, 0xABCF23D7,
0xF551451E, 0xF7DE791E,
0x035CD348, 0x0356E388,
0x821A0000, 0x821A0000,
0x0000D000, 0x0000D000,
0x00000680, 0x00000680,
0xD159647A, 0xD749247A,
0x1ED32CA3, 0x1EABCF23,
0x48F55145, 0x88F7DE79,
0x00035CD3, 0x000356E3,
0x00080200, 0x00080200,
0x00001000, 0x00001000,
0x00080200, 0x00080200,
@ -552,18 +552,18 @@ const unsigned long iocsr_scan_chain3_table[] = {
0x14F1690D, 0x14F1690D,
0x1A041414, 0x1A041414,
0x00D00000, 0x00D00000,
0x04864000, 0x18864000,
0x69A47A01, 0x49247A06,
0x9228A3D6, 0xABCF23D7,
0xF65E791E, 0xF7DE791E,
0x034C9248, 0x0356E388,
0x821A0000, 0x821A0000,
0x0000D000, 0x0000D000,
0x00000680, 0x00000680,
0xDE59647A, 0xD749247A,
0x1ED32CA3, 0x1EABCF23,
0x48F55E79, 0x88F7DE79,
0x00034CD3, 0x000356E3,
0x00080200, 0x00080200,
0x00001000, 0x00001000,
0x00080200, 0x00080200,

14
board/terasic/sockit/qts/pll_config.h
View File

@ -10,13 +10,13 @@
#define CONFIG_HPS_DBCTRL_STAYOSC1 1 #define CONFIG_HPS_DBCTRL_STAYOSC1 1
#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 #define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 73 #define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4 #define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14 #define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
@ -61,7 +61,7 @@
#define CONFIG_HPS_CLK_OSC2_HZ 25000000 #define CONFIG_HPS_CLK_OSC2_HZ 25000000
#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 #define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 #define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
#define CONFIG_HPS_CLK_MAINVCO_HZ 1850000000 #define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 #define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 #define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
#define CONFIG_HPS_CLK_EMAC0_HZ 1953125 #define CONFIG_HPS_CLK_EMAC0_HZ 1953125
@ -69,7 +69,7 @@
#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 #define CONFIG_HPS_CLK_USBCLK_HZ 200000000
#define CONFIG_HPS_CLK_NAND_HZ 50000000 #define CONFIG_HPS_CLK_NAND_HZ 50000000
#define CONFIG_HPS_CLK_SDMMC_HZ 200000000 #define CONFIG_HPS_CLK_SDMMC_HZ 200000000
#define CONFIG_HPS_CLK_QSPI_HZ 370000000 #define CONFIG_HPS_CLK_QSPI_HZ 400000000
#define CONFIG_HPS_CLK_SPIM_HZ 200000000 #define CONFIG_HPS_CLK_SPIM_HZ 200000000
#define CONFIG_HPS_CLK_CAN0_HZ 12500000 #define CONFIG_HPS_CLK_CAN0_HZ 12500000
#define CONFIG_HPS_CLK_CAN1_HZ 12500000 #define CONFIG_HPS_CLK_CAN1_HZ 12500000
@ -78,8 +78,8 @@
#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 #define CONFIG_HPS_CLK_L4_SP_HZ 100000000
#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 #define CONFIG_HPS_ALTERAGRP_MPUCLK 1
#define CONFIG_HPS_ALTERAGRP_MAINCLK 4 #define CONFIG_HPS_ALTERAGRP_MAINCLK 3
#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4 #define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */ #endif /* __SOCFPGA_PLL_CONFIG_H__ */

30
board/terasic/sockit/qts/sdram_config.h
View File

@ -32,11 +32,11 @@
#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 11
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 8
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 12 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 12
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
@ -46,7 +46,7 @@
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
@ -127,8 +127,8 @@
/* Sequencer defines configuration */ /* Sequencer defines configuration */
#define AFI_RATE_RATIO 1 #define AFI_RATE_RATIO 1
#define CALIB_LFIFO_OFFSET 8 #define CALIB_LFIFO_OFFSET 12
#define CALIB_VFIFO_OFFSET 6 #define CALIB_VFIFO_OFFSET 10
#define ENABLE_SUPER_QUICK_CALIBRATION 0 #define ENABLE_SUPER_QUICK_CALIBRATION 0
#define IO_DELAY_PER_DCHAIN_TAP 25 #define IO_DELAY_PER_DCHAIN_TAP 25
#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 #define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
@ -147,7 +147,7 @@
#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 #define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
#define MAX_LATENCY_COUNT_WIDTH 5 #define MAX_LATENCY_COUNT_WIDTH 5
#define READ_VALID_FIFO_SIZE 16 #define READ_VALID_FIFO_SIZE 16
#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048d #define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c
#define RW_MGR_MEM_ADDRESS_MIRRORING 0 #define RW_MGR_MEM_ADDRESS_MIRRORING 0
#define RW_MGR_MEM_DATA_MASK_WIDTH 4 #define RW_MGR_MEM_DATA_MASK_WIDTH 4
#define RW_MGR_MEM_DATA_WIDTH 32 #define RW_MGR_MEM_DATA_WIDTH 32
@ -171,16 +171,16 @@
const u32 ac_rom_init[] = { const u32 ac_rom_init[] = {
0x20700000, 0x20700000,
0x20780000, 0x20780000,
0x10080431, 0x10080471,
0x10080530, 0x10080570,
0x10090044, 0x10090006,
0x100a0008, 0x100a0218,
0x100b0000, 0x100b0000,
0x10380400, 0x10380400,
0x10080449, 0x10080469,
0x100804c8, 0x100804e8,
0x100a0024, 0x100a0006,
0x10090010, 0x10090218,
0x100b0000, 0x100b0000,
0x30780000, 0x30780000,
0x38780000, 0x38780000,