Update DCD based on calculations in DDR calculation spreadsheet
Martin T. H. Sandsmark
Martin T. H. Sandsmark
parent
87e4148ec8
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4ed481c16a
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@ -1,7 +1,7 @@
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/*
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* Copyright (C) 2013 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Refer docs/README.imxmage for more details about how-to configure
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* and create imximage boot image
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@ -18,7 +18,7 @@ IMAGE_VERSION 2
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* spi, sd (the board has no nand neither onenand)
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*/
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BOOT_FROM sd
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BOOT_FROM sd
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/*
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* Device Configuration Data (DCD)
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@ -27,12 +27,15 @@ BOOT_FROM sd
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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DATA 4 0x020c4018 0x00260324
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/* ============================================================================= */
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/* Enable all clocks (they are disabled by ROM code) */
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/* Full speed until we get calibrations */
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/* ============================================================================= */
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DATA 4 0x020c4068 0xffffffff
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DATA 4 0x020c406c 0xffffffff
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DATA 4 0x020c4070 0xffffffff
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@ -40,76 +43,117 @@ DATA 4 0x020c4074 0xffffffff
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DATA 4 0x020c4078 0xffffffff
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DATA 4 0x020c407c 0xffffffff
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DATA 4 0x020c4080 0xffffffff
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DATA 4 0x020c4084 0xffffffff
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DATA 4 0x020e0344 0x00003030
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DATA 4 0x020e0348 0x00003030
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DATA 4 0x020e034c 0x00003030
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DATA 4 0x020e0350 0x00003030
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DATA 4 0x020e030c 0x00000030
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DATA 4 0x020e0310 0x00000030
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DATA 4 0x020e0314 0x00000030
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DATA 4 0x020e0318 0x00000030
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DATA 4 0x020e0300 0x00000030
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DATA 4 0x020e031c 0x00000030
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DATA 4 0x020e0338 0x00000028
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DATA 4 0x020e0320 0x00000030
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DATA 4 0x020e032c 0x00000000
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DATA 4 0x020e033c 0x00000008
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DATA 4 0x020e0340 0x00000008
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DATA 4 0x020e05c4 0x00000030
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DATA 4 0x020e05cc 0x00000030
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DATA 4 0x020e05d4 0x00000030
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DATA 4 0x020e05d8 0x00000030
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DATA 4 0x020e05ac 0x00000030
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DATA 4 0x020e05c8 0x00000030
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DATA 4 0x020e05b0 0x00020000
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DATA 4 0x020e05b4 0x00000000
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DATA 4 0x020e05c0 0x00020000
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DATA 4 0x020e05d0 0x00080000
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/* ============================================================================= */
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/* IOMUX */
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/* ============================================================================= */
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/* DDR IO TYPE: */
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DATA 4 0x020e0774 0x000C0000 /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
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DATA 4 0x020e0754 0x00000000 /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
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/* CLOCK: */
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DATA 4 0x020e04ac 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */
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DATA 4 0x020e04b0 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 */
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/* ADDRESS: */
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DATA 4 0x020e0464 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
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DATA 4 0x020e0490 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
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DATA 4 0x020e074c 0x00000028 /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
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/* Control: */
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DATA 4 0x020e0494 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
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DATA 4 0x020e04a0 0x00000000 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS */
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DATA 4 0x020e04b4 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */
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DATA 4 0x020e04b8 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */
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DATA 4 0x020e076c 0x00000028 /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
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/* Data Strobes: */
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DATA 4 0x020e0750 0x00020000 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
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DATA 4 0x020e04bc 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */
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DATA 4 0x020e04c0 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */
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DATA 4 0x020e04c4 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 */
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DATA 4 0x020e04c8 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 */
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/* DATA 4 0x020e04cc 0x00000028 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 */
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/* DATA 4 0x020e04d0 0x00000028 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 */
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/* DATA 4 0x020e04d4 0x00000028 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 */
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/* DATA 4 0x020e04d8 0x00000028 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 */
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/* Data: */
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DATA 4 0x020e0760 0x00020000 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
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DATA 4 0x020e0764 0x00000028 /* IOMUXC_SW_PAD_CTL_GRP_B0DS */
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DATA 4 0x020e0770 0x00000028 /* IOMUXC_SW_PAD_CTL_GRP_B1DS */
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DATA 4 0x020e0778 0x00000028 /* IOMUXC_SW_PAD_CTL_GRP_B2DS */
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DATA 4 0x020e077c 0x00000028 /* IOMUXC_SW_PAD_CTL_GRP_B3DS */
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/* DATA 4 0x020e0780 0x00000028 # IOMUXC_SW_PAD_CTL_GRP_B4DS */
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/* DATA 4 0x020e0784 0x00000028 # IOMUXC_SW_PAD_CTL_GRP_B5DS */
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/* DATA 4 0x020e078c 0x00000028 # IOMUXC_SW_PAD_CTL_GRP_B6DS */
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/* DATA 4 0x020e0748 0x00000028 # IOMUXC_SW_PAD_CTL_GRP_B7DS */
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DATA 4 0x020e0470 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
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DATA 4 0x020e0474 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
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DATA 4 0x020e0478 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 */
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DATA 4 0x020e047c 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 */
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/* DATA 4 0x020e0480 0x00000028 # IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 */
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/* DATA 4 0x020e0484 0x00000028 # IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 */
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/* DATA 4 0x020e0488 0x00000028 # IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 */
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/* DATA 4 0x020e048c 0x00000028 # IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 */
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/* ============================================================================= */
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/* DDR Controller Registers */
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/* ============================================================================= */
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/* Manufacturer: Micron */
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/* Device Part Number: MT41K128M16JT-125 */
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/* Clock Freq.: 400MHz */
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/* Density per CS in Gb: 4 */
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/* Chip Selects used: 1 */
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/* Number of Banks: 8 */
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/* Row address: 14 */
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/* Column address: 10 */
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/* Data bus width 32 */
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/* ============================================================================= */
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DATA 4 0x021b001c 0x00008000 /* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */
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/* MMDC init: */
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DATA 4 0x021b0004 0x0002002D /* MMDC0_MDPDC */
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DATA 4 0x021b0008 0x00333040 /* MMDC0_MDOTC */
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DATA 4 0x021b000c 0x3F4352F3 /* MMDC0_MDCFG0 */
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DATA 4 0x021b0010 0xB66D8B63 /* MMDC0_MDCFG1 */
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DATA 4 0x021b0014 0x01FF00DB /* MMDC0_MDCFG2 */
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/* MDMISC: RALAT kept to the high level of 5. */
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/* MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits: */
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/* a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3 */
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/* b. Small performence improvment */
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DATA 4 0x021b0018 0x00011740 /* MMDC0_MDMISC */
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DATA 4 0x021b001c 0x00008000 /* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */
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DATA 4 0x021b002c 0x000026D2 /* MMDC0_MDRWD */
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DATA 4 0x021b0030 0x00431023 /* MMDC0_MDOR */
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DATA 4 0x021b0040 0x00000017 /* Chan0 CS0_END */
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DATA 4 0x021b0000 0x83190000 /* MMDC0_MDCTL */
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/* Mode register writes */
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DATA 4 0x021b001c 0x02008032 /* MMDC0_MDSCR, MR2 write, CS0 */
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DATA 4 0x021b001c 0x00008033 /* MMDC0_MDSCR, MR3 write, CS0 */
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DATA 4 0x021b001c 0x00048031 /* MMDC0_MDSCR, MR1 write, CS0 */
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DATA 4 0x021b001c 0x15208030 /* MMDC0_MDSCR, MR0write, CS0 */
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DATA 4 0x021b001c 0x04008040 /* MMDC0_MDSCR, ZQ calibration command sent to device on CS0 */
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/* DATA 4 0x021b001c 0x0200803A # MMDC0_MDSCR, MR2 write, CS1 */
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/* DATA 4 0x021b001c 0x0000803B # MMDC0_MDSCR, MR3 write, CS1 */
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/* DATA 4 0x021b001c 0x00048039 # MMDC0_MDSCR, MR1 write, CS1 */
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/* DATA 4 0x021b001c 0x15208038 # MMDC0_MDSCR, MR0write, CS1 */
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/* DATA 4 0x021b001c 0x04008048 # MMDC0_MDSCR, ZQ calibration command sent to device on CS1 */
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DATA 4 0x021b0020 0x00007800 /* MMDC0_MDREF */
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DATA 4 0x021b0818 0x00022227 /* DDR_PHY_P0_MPODTCTRL */
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/* DATA 4 0x021b4818 0x00022227 # DDR_PHY_P1_MPODTCTRL */
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DATA 4 0x021b0004 0x0002556D /* MMDC0_MDPDC now SDCTL power down enabled */
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DATA 4 0x021b0404 0x00011006 /* MMDC0_MAPSR ADOPT power down enabled, MMDC will enter automatically to self-refresh while the number of idle cycle reached. */
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DATA 4 0x021b001c 0x00000000 /* MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete) */
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DATA 4 0x021b001c 0x00008000
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DATA 4 0x021b085c 0x1b4700c7
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DATA 4 0x021b0800 0xa1390003
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DATA 4 0x021b0890 0x00400000
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DATA 4 0x021b08b8 0x00000800
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DATA 4 0x021b081c 0x33333333
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DATA 4 0x021b0820 0x33333333
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DATA 4 0x021b0824 0x33333333
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DATA 4 0x021b0828 0x33333333
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DATA 4 0x021b082c 0xf3333333
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DATA 4 0x021b0830 0xf3333333
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DATA 4 0x021b0834 0xf3333333
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DATA 4 0x021b0838 0xf3333333
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DATA 4 0x021b0848 0x4241444a
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DATA 4 0x021b0850 0x3030312b
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DATA 4 0x021b083c 0x20000000
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DATA 4 0x021b0840 0x00000000
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DATA 4 0x021b08c0 0x24911492
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DATA 4 0x021b08b8 0x00000800
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DATA 4 0x021b000c 0x33374133
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DATA 4 0x021b0004 0x00020024
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DATA 4 0x021b0010 0x00100A82
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DATA 4 0x021b0014 0x00000093
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DATA 4 0x021b0018 0x00001688
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DATA 4 0x021b002c 0x0f9f26d2
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DATA 4 0x021b0030 0x009f0e10
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DATA 4 0x021b0038 0x00190778
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DATA 4 0x021b0008 0x00000000
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DATA 4 0x021b0040 0x0000004f
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DATA 4 0x021b0000 0xc3110000
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DATA 4 0x021b001c 0x003f8030
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DATA 4 0x021b001c 0xff0a8030
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DATA 4 0x021b001c 0x82018030
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DATA 4 0x021b001c 0x04028030
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DATA 4 0x021b001c 0x02038030
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DATA 4 0x021b001c 0xff0a8038
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DATA 4 0x021b001c 0x82018038
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DATA 4 0x021b001c 0x04028038
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DATA 4 0x021b001c 0x02038038
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DATA 4 0x021b0800 0xa1310003
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DATA 4 0x021b0020 0x00001800
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DATA 4 0x021b0818 0x00000000
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DATA 4 0x021b08b8 0x00000800
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DATA 4 0x021b0004 0x00025564
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DATA 4 0x021b0404 0x00011006
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DATA 4 0x021b001c 0x00000000
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