mpc83xx: Fix config of Arbiter, System Priority, and Clock Mode
The config value for: * CFG_ACR_PIPE_DEP * CFG_ACR_RPTCNT * CFG_SPCR_TSEC1EP * CFG_SPCR_TSEC2EP * CFG_SCCR_TSEC1CM * CFG_SCCR_TSEC2CM Were not being used when setting the appropriate register Added: * CFG_SCCR_USBMPHCM * CFG_SCCR_USBDRCM * CFG_SCCR_PCICM * CFG_SCCR_ENCCM To allow full config of the SCCR. Also removed random CFG_SCCR settings in MPC8349EMDS, TQM834x, and sbc8349 that were just bogus. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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@ -69,31 +69,53 @@ void cpu_init_f (volatile immap_t * im)
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#ifdef CFG_ACR_PIPE_DEP
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/* Arbiter pipeline depth */
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im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | (3 << ACR_PIPE_DEP_SHIFT);
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im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
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(CFG_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
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#endif
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#ifdef CFG_SPCR_TSEC1EP
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/* TSEC1 Emergency priority */
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im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) | (3 << SPCR_TSEC1EP_SHIFT);
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im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) | (CFG_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT);
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#endif
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#ifdef CFG_SPCR_TSEC2EP
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/* TSEC2 Emergency priority */
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im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | (3 << SPCR_TSEC2EP_SHIFT);
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im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | (CFG_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT);
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#endif
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#ifdef CONFIG_MPC834X
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#ifdef CFG_SCCR_TSEC1CM
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/* TSEC1 clock mode */
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im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | (1 << SCCR_TSEC1CM_SHIFT);
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im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | (CFG_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT);
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#endif
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#ifdef CFG_SCCR_TSEC2CM
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/* TSEC2 & I2C1 clock mode */
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im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | (1 << SCCR_TSEC2CM_SHIFT);
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im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | (CFG_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT);
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#endif
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#ifdef CFG_SCCR_USBMPHCM
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/* USB MPH clock mode */
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im->clk.sccr = (im->clk.sccr & ~SCCR_USBMPHCM) | (CFG_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT);
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#endif
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#endif /* CONFIG_MPC834X */
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#ifdef CFG_SCCR_PCICM
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/* PCI & DMA clock mode */
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im->clk.sccr = (im->clk.sccr & ~SCCR_PCICM) | (CFG_SCCR_PCICM << SCCR_PCICM_SHIFT);
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#endif
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#ifdef CFG_SCCR_USBDRCM
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/* USB DR clock mode */
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im->clk.sccr = (im->clk.sccr & ~SCCR_USBDRCM) | (CFG_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT);
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#endif
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#ifdef CFG_SCCR_ENCCM
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/* Encryption clock mode */
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im->clk.sccr = (im->clk.sccr & ~SCCR_ENCCM) | (CFG_SCCR_ENCCM << SCCR_PCICM_SHIFT);
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#endif
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#ifdef CFG_ACR_RPTCNT
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/* Arbiter repeat count */
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im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) | (3 << ACR_RPTCNT_SHIFT));
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im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) | (CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT));
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#endif
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/* RSR - Reset Status Register - clear all status (4.6.1.3) */
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@ -60,17 +60,6 @@
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#endif
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#endif
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#define CFG_SCCR_INIT (SCCR_DEFAULT & (~SCCR_CLK_MASK))
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#define CFG_SCCR_TSEC1CM SCCR_TSEC1CM_1 /* TSEC1 clock setting */
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#define CFG_SCCR_TSEC2CM SCCR_TSEC2CM_1 /* TSEC2 clock setting */
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#define CFG_SCCR_ENCCM SCCR_ENCCM_3 /* ENC clock setting */
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#define CFG_SCCR_USBCM SCCR_USBCM_3 /* USB clock setting */
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#define CFG_SCCR_VAL ( CFG_SCCR_INIT \
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| CFG_SCCR_TSEC1CM \
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| CFG_SCCR_TSEC2CM \
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| CFG_SCCR_ENCCM \
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| CFG_SCCR_USBCM )
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#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
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#define CFG_IMMR 0xE0000000
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@ -57,17 +57,6 @@
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*/
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#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8)
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#define CFG_SCCR_INIT (SCCR_DEFAULT & (~SCCR_CLK_MASK))
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#define CFG_SCCR_TSEC1CM SCCR_TSEC1CM_1 /* TSEC1 clock setting */
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#define CFG_SCCR_TSEC2CM SCCR_TSEC2CM_1 /* TSEC2 clock setting */
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#define CFG_SCCR_ENCCM SCCR_ENCCM_3 /* ENC clock setting */
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#define CFG_SCCR_USBCM SCCR_USBCM_3 /* USB clock setting */
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#define CFG_SCCR_VAL ( CFG_SCCR_INIT \
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| CFG_SCCR_TSEC1CM \
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| CFG_SCCR_TSEC2CM \
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| CFG_SCCR_ENCCM \
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| CFG_SCCR_USBCM )
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/* board pre init: do not call, nothing to do */
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#undef CONFIG_BOARD_EARLY_INIT_F
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@ -63,17 +63,6 @@
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#endif
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#endif
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#define CFG_SCCR_INIT (SCCR_DEFAULT & (~SCCR_CLK_MASK))
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#define CFG_SCCR_TSEC1CM SCCR_TSEC1CM_1 /* TSEC1 clock setting */
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#define CFG_SCCR_TSEC2CM SCCR_TSEC2CM_1 /* TSEC2 clock setting */
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#define CFG_SCCR_ENCCM SCCR_ENCCM_3 /* ENC clock setting */
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#define CFG_SCCR_USBCM SCCR_USBCM_3 /* USB clock setting */
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#define CFG_SCCR_VAL ( CFG_SCCR_INIT \
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| CFG_SCCR_TSEC1CM \
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| CFG_SCCR_TSEC2CM \
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| CFG_SCCR_ENCCM \
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| CFG_SCCR_USBCM )
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#undef CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
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#define CFG_IMMR 0xE0000000
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@ -509,6 +509,7 @@
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#define SCCR_PCICM_SHIFT 16
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/* SCCR bits - MPC8349 specific */
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#ifdef CONFIG_MPC834X
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#define SCCR_TSEC1CM 0xc0000000
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#define SCCR_TSEC1CM_SHIFT 30
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#define SCCR_TSEC1CM_0 0x00000000
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@ -522,6 +523,7 @@
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#define SCCR_TSEC2CM_1 0x10000000
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#define SCCR_TSEC2CM_2 0x20000000
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#define SCCR_TSEC2CM_3 0x30000000
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#endif
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#define SCCR_USBMPHCM 0x00c00000
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#define SCCR_USBMPHCM_SHIFT 22
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@ -533,13 +535,6 @@
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#define SCCR_USBCM_2 0x00A00000
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#define SCCR_USBCM_3 0x00F00000
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#define SCCR_CLK_MASK ( SCCR_TSEC1CM_3 \
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| SCCR_TSEC2CM_3 \
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| SCCR_ENCCM_3 \
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| SCCR_USBCM_3 )
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#define SCCR_DEFAULT 0xFFFFFFFF
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/* CSn_BDNS - Chip Select memory Bounds Register
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*/
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#define CSBNDS_SA 0x00FF0000
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