Blackfin: unify cache handling code
Signed-off-by: Mike Frysinger <vapier@gentoo.org>utp
parent
3c87989834
commit
50f0d21191
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@ -14,46 +14,11 @@
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#include <asm/blackfin.h>
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#include <asm/blackfin.h>
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#include <asm/cplb.h>
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#include <asm/cplb.h>
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#include <asm/mach-common/bits/core.h>
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#include <asm/mach-common/bits/core.h>
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#include <asm/mach-common/bits/mpu.h>
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#include <asm/mach-common/bits/trace.h>
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#include <asm/mach-common/bits/trace.h>
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#include "cpu.h"
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#include "cpu.h"
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#include "serial.h"
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#include "serial.h"
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void icache_enable(void)
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{
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bfin_write_IMEM_CONTROL(bfin_read_IMEM_CONTROL() | (IMC | ENICPLB));
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SSYNC();
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}
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void icache_disable(void)
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{
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bfin_write_IMEM_CONTROL(bfin_read_IMEM_CONTROL() & ~(IMC | ENICPLB));
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SSYNC();
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}
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int icache_status(void)
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{
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return bfin_read_IMEM_CONTROL() & ENICPLB;
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}
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void dcache_enable(void)
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{
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bfin_write_DMEM_CONTROL(bfin_read_DMEM_CONTROL() | (ACACHE_BCACHE | ENDCPLB | PORT_PREF0));
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SSYNC();
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}
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void dcache_disable(void)
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{
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bfin_write_DMEM_CONTROL(bfin_read_DMEM_CONTROL() & ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0));
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SSYNC();
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}
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int dcache_status(void)
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{
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return bfin_read_DMEM_CONTROL() & ENDCPLB;
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}
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__attribute__ ((__noreturn__))
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__attribute__ ((__noreturn__))
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void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
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void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
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{
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{
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@ -11,6 +11,7 @@
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#include <common.h>
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#include <common.h>
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#include <asm/blackfin.h>
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#include <asm/blackfin.h>
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#include <asm/mach-common/bits/mpu.h>
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void flush_cache(unsigned long addr, unsigned long size)
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void flush_cache(unsigned long addr, unsigned long size)
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{
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{
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@ -24,3 +25,37 @@ void flush_cache(unsigned long addr, unsigned long size)
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if (dcache_status())
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if (dcache_status())
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blackfin_dcache_flush_range((void *)addr, (void *)(addr + size));
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blackfin_dcache_flush_range((void *)addr, (void *)(addr + size));
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}
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}
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void icache_enable(void)
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{
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bfin_write_IMEM_CONTROL(IMC | ENICPLB);
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SSYNC();
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}
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void icache_disable(void)
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{
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bfin_write_IMEM_CONTROL(0);
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SSYNC();
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}
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int icache_status(void)
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{
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return bfin_read_IMEM_CONTROL() & ENICPLB;
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}
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void dcache_enable(void)
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{
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bfin_write_DMEM_CONTROL(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
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SSYNC();
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}
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void dcache_disable(void)
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{
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bfin_write_DMEM_CONTROL(0);
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SSYNC();
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}
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int dcache_status(void)
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{
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return bfin_read_DMEM_CONTROL() & ENDCPLB;
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}
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