KARO TX25: Fix NAND Flash R/W cycle times
The NAND Flash of the KARO TX25 board is a Samsung K9F1G08U0B with 25-ns R/W cycle times. However, the NFC clock for this board was set to 66.5 MHz, so using the NFC driver in symmetric mode (i.e. 1 NFC clock cycle = 1 NF R/W cycle) resulted in NF R/W cycle times of 15 ns, hence corrupted NF accesses. This patch fixes this issue by setting the NFC clock to the highest frequency complying to the 25-ns NF R/W cycle times specification, i.e. 33.25 MHz. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: John Rigby <jcrigby@gmail.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Daniel Gachet <Daniel.Gachet@hefr.ch> Acked-by: Stefano Babic <sbabic@denx.de>
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@ -66,6 +66,14 @@
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write32 0x53f80064, 0x45600000
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write32 0x53f80008, 0x20034000
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/*
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* PCDR2: NFC = 33.25 MHz
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* This is required for the NAND Flash of this board, which is a Samsung
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* K9F1G08U0B with 25-ns R/W cycle times, in order to make it work with
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* the NFC driver in symmetric (i.e. one-cycle) mode.
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*/
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write32 0x53f80020, 0x01010103
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/*
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* enable all implemented clocks in all three
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* clock control registers
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