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remarkable-uboot
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Merge branch 'master' of git://git.denx.de/u-boot-arm

utp
Tom Rini 2014-06-08 07:58:41 -04:00
parent 3e1fa221f9 5ed28948a3
commit 55e8250bd3
108 changed files with 1920 additions and 765 deletions
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20
arch/arm/cpu/armv7/am33xx/board.c
View File

@ -143,6 +143,19 @@ int arch_misc_init(void)
}
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
/*
* In the case of non-SPL based booting we'll want to call these
* functions a tiny bit later as it will require gd to be set and cleared
* and that's not true in s_init in this case so we cannot do it there.
*/
int board_early_init_f(void)
{
prcm_init();
set_mux_conf_regs();
return 0;
}
/*
* This function is the place to do per-board things such as ramp up the
* MPU clock frequency.
@ -224,7 +237,7 @@ void s_init(void)
set_uart_mux_conf();
setup_clocks_for_console();
uart_soft_reset();
#ifdef CONFIG_NOR_BOOT
#if defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT)
gd->baudrate = CONFIG_BAUDRATE;
serial_init();
gd->have_console = 1;
@ -232,13 +245,14 @@ void s_init(void)
gd = &gdata;
preloader_console_init();
#endif
prcm_init();
set_mux_conf_regs();
#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
/* Enable RTC32K clock */
rtc32k_enable();
#endif
#ifdef CONFIG_SPL_BUILD
board_early_init_f();
sdram_init();
#endif
}
#endif

11
arch/arm/cpu/armv7/am33xx/clock.c
View File

@ -170,8 +170,19 @@ void do_enable_clocks(u32 *const *clk_domains,
};
}
/*
* Before scaling up the clocks we need to have the PMIC scale up the
* voltages first. This will be dependent on which PMIC is in use
* and in some cases we may not be scaling things up at all and thus not
* need to do anything here.
*/
__weak void scale_vcores(void)
{
}
void prcm_init()
{
enable_basic_clocks();
scale_vcores();
setup_dplls();
}

9
arch/arm/cpu/armv7/am33xx/clock_am43xx.c
View File

@ -53,6 +53,8 @@ const struct dpll_regs dpll_ddr_regs = {
void setup_clocks_for_console(void)
{
u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
/* Do not add any spl_debug prints in this function */
clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
@ -63,6 +65,13 @@ void setup_clocks_for_console(void)
MODULE_CLKCTRL_MODULEMODE_MASK,
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
(idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
clkctrl = readl(&cmwkup->wkup_uart0ctrl);
idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
MODULE_CLKCTRL_IDLEST_SHIFT;
}
}
void enable_basic_clocks(void)

4
arch/arm/cpu/armv7/am33xx/emif4.c
View File

@ -21,6 +21,10 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
sdram_init();
#endif
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size(
(void *)CONFIG_SYS_SDRAM_BASE,

45
arch/arm/cpu/armv7/exynos/clock.c
View File

@ -869,7 +869,7 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
{
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
unsigned int addr;
unsigned int addr, clear_bit, set_bit;
/*
* CLK_DIV_FSYS1
@ -877,44 +877,26 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
* CLK_DIV_FSYS2
* MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
* CLK_DIV_FSYS3
* MMC4_PRE_RATIO [15:8]
* MMC4_RATIO [3:0]
*/
if (dev_index < 2) {
addr = (unsigned int)&clk->div_fsys1;
} else if (dev_index == 4) {
clear_bit = MASK_PRE_RATIO(dev_index);
set_bit = SET_PRE_RATIO(dev_index, div);
} else if (dev_index == 4) {
addr = (unsigned int)&clk->div_fsys3;
dev_index -= 4;
/* MMC4 is controlled with the MMC4_RATIO value */
clear_bit = MASK_RATIO(dev_index);
set_bit = SET_RATIO(dev_index, div);
} else {
addr = (unsigned int)&clk->div_fsys2;
dev_index -= 2;
clear_bit = MASK_PRE_RATIO(dev_index);
set_bit = SET_PRE_RATIO(dev_index, div);
}
clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
(div & 0xff) << ((dev_index << 4) + 8));
}
/* exynos4x12: set the mmc clock */
static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
{
struct exynos4x12_clock *clk =
(struct exynos4x12_clock *)samsung_get_base_clock();
unsigned int addr;
/*
* CLK_DIV_FSYS1
* MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
* CLK_DIV_FSYS2
* MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
*/
if (dev_index < 2) {
addr = (unsigned int)&clk->div_fsys1;
} else {
addr = (unsigned int)&clk->div_fsys2;
dev_index -= 2;
}
clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
(div & 0xff) << ((dev_index << 4) + 8));
clrsetbits_le32(addr, clear_bit, set_bit);
}
/* exynos5: set the mmc clock */
@ -1612,10 +1594,7 @@ void set_mmc_clk(int dev_index, unsigned int div)
else
exynos5_set_mmc_clk(dev_index, div);
} else {
if (proid_is_exynos4412())
exynos4x12_set_mmc_clk(dev_index, div);
else
exynos4_set_mmc_clk(dev_index, div);
exynos4_set_mmc_clk(dev_index, div);
}
}

8
arch/arm/cpu/armv7/exynos/lowlevel_init.c
View File

@ -39,6 +39,7 @@ enum {
DO_CLOCKS = 1 << 1,
DO_MEM_RESET = 1 << 2,
DO_UART = 1 << 3,
DO_POWER = 1 << 4,
};
int do_lowlevel_init(void)
@ -48,6 +49,8 @@ int do_lowlevel_init(void)
arch_cpu_init();
set_ps_hold_ctrl();
reset_status = get_reset_status();
switch (reset_status) {
@ -60,9 +63,12 @@ int do_lowlevel_init(void)
break;
default:
/* This is a normal boot (not a wake from sleep) */
actions = DO_CLOCKS | DO_MEM_RESET;
actions = DO_CLOCKS | DO_MEM_RESET | DO_POWER;
}
if (actions & DO_POWER)
set_ps_hold_ctrl();
if (actions & DO_CLOCKS) {
system_clock_init();
mem_ctrl_init(actions & DO_MEM_RESET);

35
arch/arm/cpu/armv7/exynos/pinmux.c
View File

@ -573,15 +573,26 @@ static void exynos4_i2c_config(int peripheral, int flags)
static int exynos4_mmc_config(int peripheral, int flags)
{
int i, start = 0, start_ext = 0;
unsigned int func, ext_func;
switch (peripheral) {
case PERIPH_ID_SDMMC0:
start = EXYNOS4_GPIO_K00;
start_ext = EXYNOS4_GPIO_K13;
func = S5P_GPIO_FUNC(0x2);
ext_func = S5P_GPIO_FUNC(0x3);
break;
case PERIPH_ID_SDMMC2:
start = EXYNOS4_GPIO_K20;
start_ext = EXYNOS4_GPIO_K33;
func = S5P_GPIO_FUNC(0x2);
ext_func = S5P_GPIO_FUNC(0x3);
break;
case PERIPH_ID_SDMMC4:
start = EXYNOS4_GPIO_K00;
start_ext = EXYNOS4_GPIO_K13;
func = S5P_GPIO_FUNC(0x3);
ext_func = S5P_GPIO_FUNC(0x4);
break;
default:
return -1;
@ -589,13 +600,14 @@ static int exynos4_mmc_config(int peripheral, int flags)
for (i = start; i < (start + 7); i++) {
if (i == (start + 2))
continue;
gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(i, func);
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
/* SDMMC2 do not use 8bit mode at exynos4 */
if (flags & PINMUX_FLAG_8BIT_MODE) {
for (i = start_ext; i < (start_ext + 4); i++) {
gpio_cfg_pin(i, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(i, ext_func);
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
@ -676,15 +688,26 @@ static void exynos4x12_i2c_config(int peripheral, int flags)
static int exynos4x12_mmc_config(int peripheral, int flags)
{
int i, start = 0, start_ext = 0;
unsigned int func, ext_func;
switch (peripheral) {
case PERIPH_ID_SDMMC0:
start = EXYNOS4X12_GPIO_K00;
start_ext = EXYNOS4X12_GPIO_K13;
func = S5P_GPIO_FUNC(0x2);
ext_func = S5P_GPIO_FUNC(0x3);
break;
case PERIPH_ID_SDMMC2:
start = EXYNOS4X12_GPIO_K20;
start_ext = EXYNOS4X12_GPIO_K33;
func = S5P_GPIO_FUNC(0x2);
ext_func = S5P_GPIO_FUNC(0x3);
break;
case PERIPH_ID_SDMMC4:
start = EXYNOS4_GPIO_K00;
start_ext = EXYNOS4_GPIO_K13;
func = S5P_GPIO_FUNC(0x3);
ext_func = S5P_GPIO_FUNC(0x4);
break;
default:
return -1;
@ -692,13 +715,13 @@ static int exynos4x12_mmc_config(int peripheral, int flags)
for (i = start; i < (start + 7); i++) {
if (i == (start + 2))
continue;
gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(i, func);
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
if (flags & PINMUX_FLAG_8BIT_MODE) {
for (i = start_ext; i < (start_ext + 4); i++) {
gpio_cfg_pin(i, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(i, ext_func);
gpio_set_pull(i, S5P_GPIO_PULL_NONE);
gpio_set_drv(i, S5P_GPIO_DRV_4X);
}
@ -759,10 +782,10 @@ static int exynos4_pinmux_config(int peripheral, int flags)
break;
case PERIPH_ID_SDMMC0:
case PERIPH_ID_SDMMC2:
case PERIPH_ID_SDMMC4:
return exynos4_mmc_config(peripheral, flags);
case PERIPH_ID_SDMMC1:
case PERIPH_ID_SDMMC3:
case PERIPH_ID_SDMMC4:
debug("SDMMC device %d not implemented\n", peripheral);
return -1;
default:
@ -794,10 +817,10 @@ static int exynos4x12_pinmux_config(int peripheral, int flags)
break;
case PERIPH_ID_SDMMC0:
case PERIPH_ID_SDMMC2:
case PERIPH_ID_SDMMC4:
return exynos4x12_mmc_config(peripheral, flags);
case PERIPH_ID_SDMMC1:
case PERIPH_ID_SDMMC3:
case PERIPH_ID_SDMMC4:
debug("SDMMC device %d not implemented\n", peripheral);
return -1;
default:

6
arch/arm/cpu/armv7/exynos/power.c
View File

@ -112,6 +112,12 @@ static void exynos5_set_ps_hold_ctrl(void)
EXYNOS_PS_HOLD_CONTROL_DATA_HIGH);
}
/*
* Set ps_hold data driving value high
* This enables the machine to stay powered on
* after the initial power-on condition goes away
* (e.g. power button).
*/
void set_ps_hold_ctrl(void)
{
if (cpu_is_exynos5())

9
arch/arm/cpu/armv7/keystone/init.c
View File

@ -8,6 +8,7 @@
*/
#include <common.h>
#include <ns16550.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
@ -30,6 +31,14 @@ int arch_cpu_init(void)
share_all_segments(11); /* PCIE */
#endif
/*
* just initialise the COM2 port so that TI specific
* UART register PWREMU_MGMT is initialized. Linux UART
* driver doesn't handle this.
*/
NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM2),
CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
return 0;
}

12
arch/arm/cpu/armv7/omap3/mem.c
View File

@ -21,17 +21,6 @@
struct gpmc *gpmc_cfg;
#if defined(CONFIG_CMD_NAND)
#if defined(GPMC_NAND_ECC_SP_x8_LAYOUT) || defined(GPMC_NAND_ECC_LP_x8_LAYOUT)
static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
SMNAND_GPMC_CONFIG1,
SMNAND_GPMC_CONFIG2,
SMNAND_GPMC_CONFIG3,
SMNAND_GPMC_CONFIG4,
SMNAND_GPMC_CONFIG5,
SMNAND_GPMC_CONFIG6,
0,
};
#else
static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
M_NAND_GPMC_CONFIG1,
M_NAND_GPMC_CONFIG2,
@ -40,7 +29,6 @@ static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
M_NAND_GPMC_CONFIG5,
M_NAND_GPMC_CONFIG6, 0
};
#endif
#endif /* CONFIG_CMD_NAND */
#if defined(CONFIG_CMD_ONENAND)

8
arch/arm/dts/exynos4.dtsi
View File

@ -128,6 +128,14 @@
interrupts = <0 78 0>;
};
dwmmc@12550000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,exynos-dwmmc";
reg = <0x12550000 0x1000>;
interrupts = <0 131 0>;
};
gpio: gpio {
gpio-controller;
#gpio-cells = <2>;

12
arch/arm/dts/exynos4412-trats2.dts
View File

@ -31,6 +31,7 @@
console = "/serial@13820000";
mmc0 = "sdhci@12510000";
mmc2 = "sdhci@12530000";
mmc4 = "dwmmc@12550000";
};
i2c@138d0000 {
@ -416,6 +417,7 @@
samsung,bus-width = <8>;
samsung,timing = <1 3 3>;
pwr-gpios = <&gpio 0xB2 0>;
status = "disabled";
};
sdhci@12520000 {
@ -431,4 +433,14 @@
sdhci@12540000 {
status = "disabled";
};
dwmmc@12550000 {
samsung,bus-width = <8>;
samsung,timing = <2 1 0>;
pwr-gpios = <&gpio 0xB2 0>;
fifoth_val = <0x203f0040>;
bus_hz = <400000000>;
div = <0x3>;
index = <4>;
};
};

8
arch/arm/dts/exynos5.dtsi
View File

@ -136,7 +136,7 @@
mmc@12200000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,exynos5250-dwmmc";
compatible = "samsung,exynos-dwmmc";
reg = <0x12200000 0x1000>;
interrupts = <0 75 0>;
};
@ -144,7 +144,7 @@
mmc@12210000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,exynos5250-dwmmc";
compatible = "samsung,exynos-dwmmc";
reg = <0x12210000 0x1000>;
interrupts = <0 76 0>;
};
@ -152,7 +152,7 @@
mmc@12220000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,exynos5250-dwmmc";
compatible = "samsung,exynos-dwmmc";
reg = <0x12220000 0x1000>;
interrupts = <0 77 0>;
};
@ -160,7 +160,7 @@
mmc@12230000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,exynos5250-dwmmc";
compatible = "samsung,exynos-dwmmc";
reg = <0x12230000 0x1000>;
interrupts = <0 78 0>;
};

61
arch/arm/dts/exynos5250-snow.dts
View File

@ -44,7 +44,7 @@
reg = <0x1e>;
compatible = "google,cros-ec";
i2c-max-frequency = <100000>;
ec-interrupt = <&gpio 782 1>;
ec-interrupt = <&gpio 182 1>;
};
power-regulator@48 {
@ -60,7 +60,7 @@
reg = <0>;
compatible = "google,cros-ec";
spi-max-frequency = <5000000>;
ec-interrupt = <&gpio 782 1>;
ec-interrupt = <&gpio 182 1>;
optimise-flash-write;
status = "disabled";
};
@ -80,6 +80,19 @@
reg = <0x22>;
compatible = "maxim,max98095-codec";
};
ptn3460-bridge@20 {
compatible = "nxp,ptn3460";
reg = <0x20>;
/*
* TODO(sjg@chromium.org): Use GPIOs here
* powerdown-gpio = <&gpy2 5 0>;
* reset-gpio = <&gpx1 5 0>;
* edid-emulation = <5>;
* pinctrl-names = "default";
* pinctrl-0 = <&ptn3460_gpios>;
*/
};
};
i2c@12c60000 {
@ -184,4 +197,48 @@
/* UP LEFT */
0x070b0067 0x070c0069>;
};
fimd@14400000 {
samsung,vl-freq = <60>;
samsung,vl-col = <1366>;
samsung,vl-row = <768>;
samsung,vl-width = <1366>;
samsung,vl-height = <768>;
samsung,vl-clkp;
samsung,vl-dp;
samsung,vl-hsp;
samsung,vl-vsp;
samsung,vl-bpix = <4>;
samsung,vl-hspw = <32>;
samsung,vl-hbpd = <80>;
samsung,vl-hfpd = <48>;
samsung,vl-vspw = <5>;
samsung,vl-vbpd = <14>;
samsung,vl-vfpd = <3>;
samsung,vl-cmd-allow-len = <0xf>;
samsung,winid = <0>;
samsung,interface-mode = <1>;
samsung,dp-enabled = <1>;
samsung,dual-lcd-enabled = <0>;
};
dp@145b0000 {
samsung,lt-status = <0>;
samsung,master-mode = <0>;
samsung,bist-mode = <0>;
samsung,bist-pattern = <0>;
samsung,h-sync-polarity = <0>;
samsung,v-sync-polarity = <0>;
samsung,interlaced = <0>;
samsung,color-space = <0>;
samsung,dynamic-range = <0>;
samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>;
};
};

9
arch/arm/dts/tegra124-jetson-tk1.dts
View File

@ -17,7 +17,8 @@
sdhci1 = "/sdhci@700b0400";
spi0 = "/spi@7000d400";
spi1 = "/spi@7000da00";
usb0 = "/usb@7d008000";
usb0 = "/usb@7d000000";
usb1 = "/usb@7d008000";
};
memory {
@ -77,6 +78,12 @@
bus-width = <8>;
};
usb@7d000000 {
status = "okay";
dr_mode = "otg";
nvidia,vbus-gpio = <&gpio 108 0>; /* gpio PN4, USB_VBUS_EN0 */
};
usb@7d008000 {
status = "okay";
nvidia,vbus-gpio = <&gpio 109 0>; /* gpio PN5, USB_VBUS_EN1 */

9
arch/arm/dts/tegra124-venice2.dts
View File

@ -17,7 +17,8 @@
sdhci1 = "/sdhci@700b0400";
spi0 = "/spi@7000d400";
spi1 = "/spi@7000da00";
usb0 = "/usb@7d008000";
usb0 = "/usb@7d000000";
usb1 = "/usb@7d008000";
};
memory {
@ -77,6 +78,12 @@
bus-width = <8>;
};
usb@7d000000 {
status = "okay";
dr_mode = "otg";
nvidia,vbus-gpio = <&gpio 108 0>; /* gpio PN4, USB_VBUS_EN0 */
};
usb@7d008000 {
status = "okay";
nvidia,vbus-gpio = <&gpio 109 0>; /* gpio PN5, USB_VBUS_EN1 */

9
arch/arm/dts/tegra30-beaver.dts
View File

@ -14,7 +14,8 @@
i2c4 = "/i2c@7000c700";
sdhci0 = "/sdhci@78000600";
sdhci1 = "/sdhci@78000000";
usb0 = "/usb@7d008000";
usb0 = "/usb@7d000000";
usb1 = "/usb@7d008000";
};
memory {
@ -70,6 +71,12 @@
bus-width = <8>;
};
usb@7d000000 {
status = "okay";
dr_mode = "otg";
nvidia,vbus-gpio = <&gpio 238 0>; /* gpio DD6, PEX_L1_CLKREQ */
};
usb@7d008000 {
nvidia,vbus-gpio = <&gpio 236 0>; /* PDD4 */
status = "okay";

1
arch/arm/include/asm/arch-am33xx/clock.h
View File

@ -107,6 +107,7 @@ const struct dpll_params *get_dpll_mpu_params(void);
const struct dpll_params *get_dpll_core_params(void);
const struct dpll_params *get_dpll_per_params(void);
const struct dpll_params *get_dpll_ddr_params(void);
void scale_vcores(void);
void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *);
void prcm_init(void);
void enable_basic_clocks(void);

33
arch/arm/include/asm/arch-am33xx/cpu.h
View File

@ -26,7 +26,17 @@
#define TCLR_PRE BIT(5) /* Pre-scaler enable */
#define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */
#define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */
#define TCLR_CE BIT(6) /* compare mode enable */
#define TCLR_SCPWM BIT(7) /* pwm outpin behaviour */
#define TCLR_TCM BIT(8) /* edge detection of input pin*/
#define TCLR_TRG_SHIFT (10) /* trigmode on pwm outpin */
#define TCLR_PT BIT(12) /* pulse/toggle mode of outpin*/
#define TCLR_CAPTMODE BIT(13) /* capture mode */
#define TCLR_GPOCFG BIT(14) /* 0=output,1=input */
#define TCFG_RESET BIT(0) /* software reset */
#define TCFG_EMUFREE BIT(1) /* behaviour of tmr on debug */
#define TCFG_IDLEMOD_SHIFT (2) /* power management */
/* device type */
#define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10))
#define TST_DEVICE 0x0
@ -87,7 +97,8 @@ struct cm_wkuppll {
unsigned int wkctrlclkctrl; /* offset 0x04 */
unsigned int wkgpio0clkctrl; /* offset 0x08 */
unsigned int wkl4wkclkctrl; /* offset 0x0c */
unsigned int resv2[4];
unsigned int timer0clkctrl; /* offset 0x10 */
unsigned int resv2[3];
unsigned int idlestdpllmpu; /* offset 0x20 */
unsigned int resv3[2];
unsigned int clkseldpllmpu; /* offset 0x2c */
@ -121,7 +132,9 @@ struct cm_wkuppll {
unsigned int wkup_uart0ctrl; /* offset 0xB4 */
unsigned int wkup_i2c0ctrl; /* offset 0xB8 */
unsigned int wkup_adctscctrl; /* offset 0xBC */
unsigned int resv12[6];
unsigned int resv12;
unsigned int timer1clkctrl; /* offset 0xC4 */
unsigned int resv13[4];
unsigned int divm6dpllcore; /* offset 0xD8 */
};
@ -178,7 +191,9 @@ struct cm_perpll {
unsigned int epwmss2clkctrl; /* offset 0xD8 */
unsigned int l3instrclkctrl; /* offset 0xDC */
unsigned int l3clkctrl; /* Offset 0xE0 */
unsigned int resv8[4];
unsigned int resv8[2];
unsigned int timer5clkctrl; /* offset 0xEC */
unsigned int timer6clkctrl; /* offset 0xF0 */
unsigned int mmc1clkctrl; /* offset 0xF4 */
unsigned int mmc2clkctrl; /* offset 0xF8 */
unsigned int resv9[8];
@ -191,9 +206,17 @@ struct cm_perpll {
/* Encapsulating Display pll registers */
struct cm_dpll {
unsigned int resv1[2];
unsigned int resv1;
unsigned int clktimer7clk; /* offset 0x04 */
unsigned int clktimer2clk; /* offset 0x08 */
unsigned int resv2[10];
unsigned int clktimer3clk; /* offset 0x0C */
unsigned int clktimer4clk; /* offset 0x10 */
unsigned int resv2;
unsigned int clktimer5clk; /* offset 0x18 */
unsigned int clktimer6clk; /* offset 0x1C */
unsigned int resv3[2];
unsigned int clktimer1clk; /* offset 0x28 */
unsigned int resv4[2];
unsigned int clklcdcpixelclk; /* offset 0x34 */
};
#else

5
arch/arm/include/asm/arch-exynos/clk.h
View File

@ -16,6 +16,11 @@
#define BPLL 5
#define RPLL 6
#define MASK_PRE_RATIO(x) (0xff << ((x << 4) + 8))
#define MASK_RATIO(x) (0xf << (x << 4))
#define SET_PRE_RATIO(x, y) ((y & 0xff) << ((x << 4) + 8))
#define SET_RATIO(x, y) ((y & 0xf) << (x << 4))
enum pll_src_bit {
EXYNOS_SRC_MPLL = 6,
EXYNOS_SRC_EPLL,

1
arch/arm/include/asm/arch-exynos/power.h
View File

@ -1726,4 +1726,5 @@ uint32_t get_reset_status(void);
/* Read the resume function and call it */
void power_exit_wakeup(void);
#endif

2
arch/arm/include/asm/arch-keystone/hardware-k2hk.h
View File

@ -115,8 +115,6 @@
#define K2HK_LPSC_ARM_SREFLEX 51
#define K2HK_LPSC_TETRIS 52
#define K2HK_UART0_BASE 0x02530c00
/* DDR3A definitions */
#define K2HK_DDR3A_EMIF_CTRL_BASE 0x21010000
#define K2HK_DDR3A_EMIF_DATA_BASE 0x80000000

3
arch/arm/include/asm/arch-keystone/hardware.h
View File

@ -142,6 +142,9 @@ struct ddr3_emif_config {
#define KS2_DDR3_PMCTL_OFFSET 0x38
#define KS2_DDR3_ZQCFG_OFFSET 0xC8
#define KS2_UART0_BASE 0x02530c00
#define KS2_UART1_BASE 0x02531000
#ifdef CONFIG_SOC_K2HK
#include <asm/arch/hardware-k2hk.h>
#endif

8
arch/arm/include/asm/arch-omap3/mem.h
View File

@ -354,14 +354,6 @@ enum {
#define GPMC_CS_ENABLE 0x1
#define SMNAND_GPMC_CONFIG1 0x00000800
#define SMNAND_GPMC_CONFIG2 0x00141400
#define SMNAND_GPMC_CONFIG3 0x00141400
#define SMNAND_GPMC_CONFIG4 0x0F010F01
#define SMNAND_GPMC_CONFIG5 0x010C1414
#define SMNAND_GPMC_CONFIG6 0x1F0F0A80
#define SMNAND_GPMC_CONFIG7 0x00000C44
#define M_NAND_GPMC_CONFIG1 0x00001800
#define M_NAND_GPMC_CONFIG2 0x00141400
#define M_NAND_GPMC_CONFIG3 0x00141400

2
board/BuR/tseries/board.c
View File

@ -117,7 +117,9 @@ void sdram_init(void)
int board_init(void)
{
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_NAND
gpmc_init();
#endif
return 0;
}

9
board/BuR/tseries/mux.c
View File

@ -27,6 +27,11 @@ static struct module_pin_mux uart0_pin_mux[] = {
};
#ifdef CONFIG_MMC
static struct module_pin_mux mmc1_pin_mux[] = {
{OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
{OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */
{OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */
{OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */
{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
@ -125,7 +130,7 @@ static struct module_pin_mux gpIOs[] = {
{OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | RXACTIVE)},
/* TIMER6 (MMC0_DAT2) - PWM_BACK_3V3, later used as MODE3 for PWM */
{OFFSET(mmc0_dat2), (MODE(7) | PULLUDEN | RXACTIVE)},
/* GPIO2_28 (MMC0_DAT1) - MII_nNAND */
/* GPIO2_27 (MMC0_DAT1) - MII_nNAND */
{OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | RXACTIVE)},
/* GPIO2_29 (MMC0_DAT0) - NAND_1n0 */
{OFFSET(mmc0_dat0), (MODE(7) | PULLUDEN | RXACTIVE)},
@ -148,7 +153,7 @@ static struct module_pin_mux gpIOs[] = {
* DISPLAY_ONOFF (Backlight Enable at LVDS Versions)
*/
{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | RXACTIVE)},
/* GPIO0_19 (DMA_INTR0) - ISPLAY_MODE (CPLD) */
/* GPIO0_19 (DMA_INTR0) - DISPLAY_MODE (CPLD) */
{OFFSET(xdma_event_intr0), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
/* GPIO0_20 (DMA_INTR1) - REP-Switch */
{OFFSET(xdma_event_intr1), (MODE(7) | PULLUP_EN | RXACTIVE)},

12
board/compulab/cm_t35/cm_t35.c
View File

@ -54,12 +54,12 @@ static u32 gpmc_net_config[GPMC_MAX_REG] = {
};
static u32 gpmc_nand_config[GPMC_MAX_REG] = {
SMNAND_GPMC_CONFIG1,
SMNAND_GPMC_CONFIG2,
SMNAND_GPMC_CONFIG3,
SMNAND_GPMC_CONFIG4,
SMNAND_GPMC_CONFIG5,
SMNAND_GPMC_CONFIG6,
M_NAND_GPMC_CONFIG1,
M_NAND_GPMC_CONFIG2,
M_NAND_GPMC_CONFIG3,
M_NAND_GPMC_CONFIG4,
M_NAND_GPMC_CONFIG5,
M_NAND_GPMC_CONFIG6,
0,
};

13
board/samsung/common/board.c
View File

@ -243,13 +243,6 @@ int board_eth_init(bd_t *bis)
int board_mmc_init(bd_t *bis)
{
int ret;
#ifdef CONFIG_SDHCI
/* mmc initializattion for available channels */
ret = exynos_mmc_init(gd->fdt_blob);
if (ret)
debug("mmc init failed\n");
#endif
#ifdef CONFIG_DWMMC
/* dwmmc initializattion for available channels */
ret = exynos_dwmmc_init(gd->fdt_blob);
@ -257,6 +250,12 @@ int board_mmc_init(bd_t *bis)
debug("dwmmc init failed\n");
#endif
#ifdef CONFIG_SDHCI
/* mmc initializattion for available channels */
ret = exynos_mmc_init(gd->fdt_blob);
if (ret)
debug("mmc init failed\n");
#endif
return ret;
}
#endif

8
board/samsung/goni/goni.c
View File

@ -14,6 +14,8 @@
#include <asm/arch/cpu.h>
#include <power/max8998_pmic.h>
#include <samsung/misc.h>
#include <usb.h>
#include <usb_mass_storage.h>
DECLARE_GLOBAL_DATA_PTR;
@ -175,6 +177,12 @@ struct s3c_plat_otg_data s5pc110_otg_data = {
.regs_otg = S5PC110_OTG_BASE,
.usb_phy_ctrl = S5PC110_USB_PHY_CONTROL,
};
int board_usb_init(int index, enum usb_init_type init)
{
debug("USB_udc_probe\n");
return s3c_udc_probe(&s5pc110_otg_data);
}
#endif
#ifdef CONFIG_MISC_INIT_R

4
board/samsung/smdk5250/Makefile
View File

@ -7,9 +7,5 @@
obj-y += smdk5250_spl.o
ifndef CONFIG_SPL_BUILD
ifdef CONFIG_OF_CONTROL
obj-y += exynos5-dt.o
else
obj-y += smdk5250.o
endif
endif

238
board/samsung/smdk5250/exynos5-dt.c
View File

@ -11,15 +11,16 @@
#include <i2c.h>
#include <netdev.h>
#include <spi.h>
#include <asm/gpio.h>
#include <asm/arch/cpu.h>
#include <asm/arch/dwmmc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/power.h>
#include <asm/arch/sromc.h>
#include <power/pmic.h>
#include <power/max77686_pmic.h>
#include <power/tps65090_pmic.h>
#include <tmu.h>
DECLARE_GLOBAL_DATA_PTR;
@ -41,7 +42,197 @@ int exynos_init(void)
return 0;
}
#if defined(CONFIG_POWER)
#ifdef CONFIG_POWER_MAX77686
static int pmic_reg_update(struct pmic *p, int reg, uint regval)
{
u32 val;
int ret = 0;
ret = pmic_reg_read(p, reg, &val);
if (ret) {
debug("%s: PMIC %d register read failed\n", __func__, reg);
return -1;
}
val |= regval;
ret = pmic_reg_write(p, reg, val);
if (ret) {
debug("%s: PMIC %d register write failed\n", __func__, reg);
return -1;
}
return 0;
}
static int max77686_init(void)
{
struct pmic *p;
if (pmic_init(I2C_PMIC))
return -1;
p = pmic_get("MAX77686_PMIC");
if (!p)
return -ENODEV;
if (pmic_probe(p))
return -1;
if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
return -1;
if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
return -1;
/* VDD_MIF */
if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
MAX77686_BUCK1OUT_1V)) {
debug("%s: PMIC %d register write failed\n", __func__,
MAX77686_REG_PMIC_BUCK1OUT);
return -1;
}
if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
MAX77686_BUCK1CTRL_EN))
return -1;
/* VDD_ARM */
if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
MAX77686_BUCK2DVS1_1_3V)) {
debug("%s: PMIC %d register write failed\n", __func__,
MAX77686_REG_PMIC_BUCK2DVS1);
return -1;
}
if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
MAX77686_BUCK2CTRL_ON))
return -1;
/* VDD_INT */
if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
MAX77686_BUCK3DVS1_1_0125V)) {
debug("%s: PMIC %d register write failed\n", __func__,
MAX77686_REG_PMIC_BUCK3DVS1);
return -1;
}
if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
MAX77686_BUCK3CTRL_ON))
return -1;
/* VDD_G3D */
if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
MAX77686_BUCK4DVS1_1_2V)) {
debug("%s: PMIC %d register write failed\n", __func__,
MAX77686_REG_PMIC_BUCK4DVS1);
return -1;
}
if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
MAX77686_BUCK3CTRL_ON))
return -1;
/* VDD_LDO2 */
if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
MAX77686_LD02CTRL1_1_5V | EN_LDO))
return -1;
/* VDD_LDO3 */
if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
MAX77686_LD03CTRL1_1_8V | EN_LDO))
return -1;
/* VDD_LDO5 */
if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
MAX77686_LD05CTRL1_1_8V | EN_LDO))
return -1;
/* VDD_LDO10 */
if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
MAX77686_LD10CTRL1_1_8V | EN_LDO))
return -1;
return 0;
}
#endif /* CONFIG_POWER_MAX77686 */
int exynos_power_init(void)
{
int ret = 0;
#ifdef CONFIG_POWER_MAX77686
ret = max77686_init();
if (ret)
return ret;
#endif
#ifdef CONFIG_POWER_TPS65090
/*
* The TPS65090 may not be in the device tree. If so, it is not
* an error.
*/
ret = tps65090_init();
if (ret == 0 || ret == -ENODEV)
return 0;
#endif
return ret;
}
#endif /* CONFIG_POWER */
#ifdef CONFIG_LCD
static int board_dp_bridge_setup(void)
{
const int max_tries = 10;
int num_tries, node;
/*
* TODO(sjg): Use device tree for GPIOs when exynos GPIO
* numbering patch is in mainline.
*/
debug("%s\n", __func__);
node = fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_NXP_PTN3460);
if (node < 0) {
debug("%s: No node for DP bridge in device tree\n", __func__);
return -ENODEV;
}
/* Setup the GPIOs */
/* PD is ACTIVE_LOW, and initially de-asserted */
gpio_set_pull(EXYNOS5_GPIO_Y25, S5P_GPIO_PULL_NONE);
gpio_direction_output(EXYNOS5_GPIO_Y25, 1);
/* Reset is ACTIVE_LOW */
gpio_set_pull(EXYNOS5_GPIO_X15, S5P_GPIO_PULL_NONE);
gpio_direction_output(EXYNOS5_GPIO_X15, 0);
udelay(10);
gpio_set_value(EXYNOS5_GPIO_X15, 1);
gpio_direction_input(EXYNOS5_GPIO_X07);
/*
* We need to wait for 90ms after bringing up the bridge since there
* is a phantom "high" on the HPD chip during its bootup. The phantom
* high comes within 7ms of de-asserting PD and persists for at least
* 15ms. The real high comes roughly 50ms after PD is de-asserted. The
* phantom high makes it hard for us to know when the NXP chip is up.
*/
mdelay(90);
for (num_tries = 0; num_tries < max_tries; num_tries++) {
/* Check HPD. If it's high, we're all good. */
if (gpio_get_value(EXYNOS5_GPIO_X07))
return 0;
debug("%s: eDP bridge failed to come up; try %d of %d\n",
__func__, num_tries, max_tries);
}
/* Immediately go into bridge reset if the hp line is not high */
return -ENODEV;
}
void exynos_cfg_lcd_gpio(void)
{
/* For Backlight */
@ -60,4 +251,49 @@ void exynos_set_dp_phy(unsigned int onoff)
{
set_dp_phy_ctrl(onoff);
}
void exynos_backlight_on(unsigned int on)
{
debug("%s(%u)\n", __func__, on);
if (!on)
return;
#ifdef CONFIG_POWER_TPS65090
int ret;
ret = tps65090_fet_enable(1); /* Enable FET1, backlight */
if (ret)
return;
/* T5 in the LCD timing spec (defined as > 10ms) */
mdelay(10);
/* board_dp_backlight_pwm */
gpio_direction_output(EXYNOS5_GPIO_B20, 1);
/* T6 in the LCD timing spec (defined as > 10ms) */
mdelay(10);
/* board_dp_backlight_en */
gpio_direction_output(EXYNOS5_GPIO_X30, 1);
#endif
}
void exynos_lcd_power_on(void)
{
int ret;
debug("%s\n", __func__);
#ifdef CONFIG_POWER_TPS65090
/* board_dp_lcd_vdd */
tps65090_fet_enable(6); /* Enable FET6, lcd panel */
#endif
ret = board_dp_bridge_setup();
if (ret && ret != -ENODEV)
printf("LCD bridge failed to enable: %d\n", ret);
}
#endif

363
board/samsung/smdk5250/smdk5250.c
View File

@ -1,363 +0,0 @@
/*
* Copyright (C) 2012 Samsung Electronics
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <cros_ec.h>
#include <fdtdec.h>
#include <asm/io.h>
#include <errno.h>
#include <i2c.h>
#include <lcd.h>
#include <netdev.h>
#include <spi.h>
#include <asm/arch/cpu.h>
#include <asm/arch/dwmmc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/power.h>
#include <asm/arch/sromc.h>
#include <asm/arch/dp_info.h>
#include <power/pmic.h>
#include <power/max77686_pmic.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SOUND_MAX98095
static void board_enable_audio_codec(void)
{
/* Enable MAX98095 Codec */
gpio_direction_output(EXYNOS5_GPIO_X17, 1);
gpio_set_pull(EXYNOS5_GPIO_X17, S5P_GPIO_PULL_NONE);
}
#endif
int exynos_init(void)
{
#ifdef CONFIG_SOUND_MAX98095
board_enable_audio_codec();
#endif
return 0;
}
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_SMC911X
u32 smc_bw_conf, smc_bc_conf;
struct fdt_sromc config;
fdt_addr_t base_addr;
/* Non-FDT configuration - bank number and timing parameters*/
config.bank = CONFIG_ENV_SROM_BANK;
config.width = 2;
config.timing[FDT_SROM_TACS] = 0x01;
config.timing[FDT_SROM_TCOS] = 0x01;
config.timing[FDT_SROM_TACC] = 0x06;
config.timing[FDT_SROM_TCOH] = 0x01;
config.timing[FDT_SROM_TAH] = 0x0C;
config.timing[FDT_SROM_TACP] = 0x09;
config.timing[FDT_SROM_PMC] = 0x01;
base_addr = CONFIG_SMC911X_BASE;
/* Ethernet needs data bus width of 16 bits */
if (config.width != 2) {
debug("%s: Unsupported bus width %d\n", __func__,
config.width);
return -1;
}
smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
| SROMC_BYTE_ENABLE(config.bank);
smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) |\
SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |\
SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |\
SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |\
SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) |\
SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |\
SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
/* Select and configure the SROMC bank */
exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
return smc911x_initialize(0, base_addr);
#endif
return 0;
}
#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{
printf("\nBoard: SMDK5250\n");
return 0;
}
#endif
#ifdef CONFIG_GENERIC_MMC
int board_mmc_init(bd_t *bis)
{
int err, ret = 0, index, bus_width;
u32 base;
err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
if (err)
debug("SDMMC0 not configured\n");
ret |= err;
/*EMMC: dwmmc Channel-0 with 8 bit bus width */
index = 0;
base = samsung_get_base_mmc() + (0x10000 * index);
bus_width = 8;
err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL);
if (err)
debug("dwmmc Channel-0 init failed\n");
ret |= err;
err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
if (err)
debug("SDMMC2 not configured\n");
ret |= err;
/*SD: dwmmc Channel-2 with 4 bit bus width */
index = 2;
base = samsung_get_base_mmc() + (0x10000 * index);
bus_width = 4;
err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL);
if (err)
debug("dwmmc Channel-2 init failed\n");
ret |= err;
return ret;
}
#endif
void board_i2c_init(const void *blob)
{
int i;
for (i = 0; i < CONFIG_MAX_I2C_NUM; i++) {
exynos_pinmux_config((PERIPH_ID_I2C0 + i),
PINMUX_FLAG_NONE);
}
}
#if defined(CONFIG_POWER)
#ifdef CONFIG_POWER_MAX77686
static int pmic_reg_update(struct pmic *p, int reg, uint regval)
{
u32 val;
int ret = 0;
ret = pmic_reg_read(p, reg, &val);
if (ret) {
debug("%s: PMIC %d register read failed\n", __func__, reg);
return -1;
}
val |= regval;
ret = pmic_reg_write(p, reg, val);
if (ret) {
debug("%s: PMIC %d register write failed\n", __func__, reg);
return -1;
}
return 0;
}
static int max77686_init(void)
{
struct pmic *p;
if (pmic_init(I2C_PMIC))
return -1;
p = pmic_get("MAX77686_PMIC");
if (!p)
return -ENODEV;
if (pmic_probe(p))
return -1;
if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
return -1;
if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
return -1;
/* VDD_MIF */
if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
MAX77686_BUCK1OUT_1V)) {
debug("%s: PMIC %d register write failed\n", __func__,
MAX77686_REG_PMIC_BUCK1OUT);
return -1;
}
if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
MAX77686_BUCK1CTRL_EN))
return -1;
/* VDD_ARM */
if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
MAX77686_BUCK2DVS1_1_3V)) {
debug("%s: PMIC %d register write failed\n", __func__,
MAX77686_REG_PMIC_BUCK2DVS1);
return -1;
}
if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
MAX77686_BUCK2CTRL_ON))
return -1;
/* VDD_INT */
if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
MAX77686_BUCK3DVS1_1_0125V)) {
debug("%s: PMIC %d register write failed\n", __func__,
MAX77686_REG_PMIC_BUCK3DVS1);
return -1;
}
if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
MAX77686_BUCK3CTRL_ON))
return -1;
/* VDD_G3D */
if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
MAX77686_BUCK4DVS1_1_2V)) {
debug("%s: PMIC %d register write failed\n", __func__,
MAX77686_REG_PMIC_BUCK4DVS1);
return -1;
}
if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
MAX77686_BUCK3CTRL_ON))
return -1;
/* VDD_LDO2 */
if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
MAX77686_LD02CTRL1_1_5V | EN_LDO))
return -1;
/* VDD_LDO3 */
if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
MAX77686_LD03CTRL1_1_8V | EN_LDO))
return -1;
/* VDD_LDO5 */
if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
MAX77686_LD05CTRL1_1_8V | EN_LDO))
return -1;
/* VDD_LDO10 */
if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
MAX77686_LD10CTRL1_1_8V | EN_LDO))
return -1;
return 0;
}
#endif /* CONFIG_POWER_MAX77686 */
int exynos_power_init(void)
{
int ret = 0;
#ifdef CONFIG_POWER_MAX77686
ret = max77686_init();
#endif
return ret;
}
#endif /* CONFIG_POWER */
#ifdef CONFIG_LCD
void exynos_cfg_lcd_gpio(void)
{
/* For Backlight */
gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_OUTPUT);
gpio_set_value(EXYNOS5_GPIO_B20, 1);
/* LCD power on */
gpio_cfg_pin(EXYNOS5_GPIO_X15, S5P_GPIO_OUTPUT);
gpio_set_value(EXYNOS5_GPIO_X15, 1);
/* Set Hotplug detect for DP */
gpio_cfg_pin(EXYNOS5_GPIO_X07, S5P_GPIO_FUNC(0x3));
}
void exynos_set_dp_phy(unsigned int onoff)
{
set_dp_phy_ctrl(onoff);
}
vidinfo_t panel_info = {
.vl_freq = 60,
.vl_col = 2560,
.vl_row = 1600,
.vl_width = 2560,
.vl_height = 1600,
.vl_clkp = CONFIG_SYS_LOW,
.vl_hsp = CONFIG_SYS_LOW,
.vl_vsp = CONFIG_SYS_LOW,
.vl_dp = CONFIG_SYS_LOW,
.vl_bpix = 4, /* LCD_BPP = 2^4, for output conosle on LCD */
/* wDP panel timing infomation */
.vl_hspw = 32,
.vl_hbpd = 80,
.vl_hfpd = 48,
.vl_vspw = 6,
.vl_vbpd = 37,
.vl_vfpd = 3,
.vl_cmd_allow_len = 0xf,
.win_id = 3,
.dual_lcd_enabled = 0,
.init_delay = 0,
.power_on_delay = 0,
.reset_delay = 0,
.interface_mode = FIMD_RGB_INTERFACE,
.dp_enabled = 1,
};
static struct edp_device_info edp_info = {
.disp_info = {
.h_res = 2560,
.h_sync_width = 32,
.h_back_porch = 80,
.h_front_porch = 48,
.v_res = 1600,
.v_sync_width = 6,
.v_back_porch = 37,
.v_front_porch = 3,
.v_sync_rate = 60,
},
.lt_info = {
.lt_status = DP_LT_NONE,
},
.video_info = {
.master_mode = 0,
.bist_mode = DP_DISABLE,
.bist_pattern = NO_PATTERN,
.h_sync_polarity = 0,
.v_sync_polarity = 0,
.interlaced = 0,
.color_space = COLOR_RGB,
.dynamic_range = VESA,
.ycbcr_coeff = COLOR_YCBCR601,
.color_depth = COLOR_8,
},
};
static struct exynos_dp_platform_data dp_platform_data = {
.edp_dev_info = &edp_info,
};
void init_panel_info(vidinfo_t *vid)
{
vid->rgb_mode = MODE_RGB_P;
exynos_set_dp_platform_data(&dp_platform_data);
}
#endif

3
board/samsung/smdk5420/smdk5420.c
View File

@ -42,9 +42,6 @@ int exynos_init(void)
#ifdef CONFIG_LCD
void cfg_lcd_gpio(void)
{
struct exynos5_gpio_part1 *gpio1 =
(struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
/* For Backlight */
gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_OUTPUT);
gpio_set_value(EXYNOS5420_GPIO_B20, 1);

2
board/ti/am43xx/Makefile
View File

@ -6,7 +6,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_SPL_BUILD
ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
obj-y := mux.o
endif

55
board/ti/am43xx/board.c
View File

@ -19,6 +19,7 @@
#include <asm/arch/gpio.h>
#include <asm/emif.h>
#include "board.h"
#include <power/tps65218.h>
#include <miiphy.h>
#include <cpsw.h>
@ -70,7 +71,7 @@ static int read_eeprom(struct am43xx_board_id *header)
return 0;
}
#ifdef CONFIG_SPL_BUILD
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define NUM_OPPS 6
@ -254,13 +255,6 @@ void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
const struct dpll_params *get_dpll_ddr_params(void)
{
struct am43xx_board_id header;
enable_i2c0_pin_mux();
i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
if (read_eeprom(&header) < 0)
puts("Could not get board ID.\n");
if (board_is_eposevm())
return &epos_evm_dpll_ddr;
else if (board_is_gpevm())
@ -302,7 +296,10 @@ static u32 get_sys_clk_index(void)
static int get_opp_offset(int max_off, int min_off)
{
struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
int opp = readl(&ctrl->dev_attr), offset, i;
int opp, offset, i;
/* Bits 0:11 are defined to be the MPU_MAX_FREQ */
opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
for (i = max_off; i >= min_off; i--) {
offset = opp & (1 << i);
@ -335,6 +332,46 @@ const struct dpll_params *get_dpll_per_params(void)
return &dpll_per[ind];
}
void scale_vcores(void)
{
const struct dpll_params *mpu_params;
int mpu_vdd;
struct am43xx_board_id header;
enable_i2c0_pin_mux();
i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
if (read_eeprom(&header) < 0)
puts("Could not get board ID.\n");
/* Get the frequency */
mpu_params = get_dpll_mpu_params();
if (i2c_probe(TPS65218_CHIP_PM))
return;
if (mpu_params->m == 1000) {
mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
} else if (mpu_params->m == 600) {
mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
} else {
puts("Unknown MPU clock, not scaling\n");
return;
}
/* Set DCDC1 (CORE) voltage to 1.1V */
if (tps65218_voltage_update(TPS65218_DCDC1,
TPS65218_DCDC_VOLT_SEL_1100MV)) {
puts("tps65218_voltage_update failure\n");
return;
}
/* Set DCDC2 (MPU) voltage */
if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
puts("tps65218_voltage_update failure\n");
return;
}
}
void set_uart_mux_conf(void)
{
enable_uart0_pin_mux();

1
boards.cfg
View File

@ -273,6 +273,7 @@ Active arm armv7 am33xx ti am335x
Active arm armv7 am33xx ti am335x am335x_evm_uart5 am335x_evm:SERIAL6,CONS_INDEX=6,NAND Tom Rini <trini@ti.com>
Active arm armv7 am33xx ti am335x am335x_evm_usbspl am335x_evm:SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT Tom Rini <trini@ti.com>
Active arm armv7 am33xx ti am43xx am43xx_evm am43xx_evm:SERIAL1,CONS_INDEX=1 Lokesh Vutla <lokeshvutla@ti.com>
Active arm armv7 am33xx ti am43xx am43xx_evm_qspiboot am43xx_evm:SERIAL1,CONS_INDEX=1,QSPI,QSPI_BOOT Lokesh Vutla <lokeshvutla@ti.com>
Active arm armv7 am33xx ti ti814x ti814x_evm - Matt Porter <matt.porter@linaro.org>
Active arm armv7 am33xx ti ti816x ti816x_evm - -
Active arm armv7 at91 atmel sama5d3_xplained sama5d3_xplained_mmc sama5d3_xplained:SAMA5D3,SYS_USE_MMC Bo Shen <voice.shen@atmel.com>

60
doc/README.nand
View File

@ -190,6 +190,24 @@ Configuration Options:
This is used by SoC platforms which do not have built-in ELM
hardware engine required for BCH ECC correction.
CONFIG_SYS_NAND_BUSWIDTH_16BIT
Indicates that NAND device has 16-bit wide data-bus. In absence of this
config, bus-width of NAND device is assumed to be either 8-bit and later
determined by reading ONFI params.
Above config is useful when NAND device's bus-width information cannot
be determined from on-chip ONFI params, like in following scenarios:
- SPL boot does not support reading of ONFI parameters. This is done to
keep SPL code foot-print small.
- In current U-Boot flow using nand_init(), driver initialization
happens in board_nand_init() which is called before any device probe
(nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are
not available while configuring controller. So a static CONFIG_NAND_xx
is needed to know the device's bus-width in advance.
Some drivers using above config are:
drivers/mtd/nand/mxc_nand.c
drivers/mtd/nand/ndfc.c
drivers/mtd/nand/omap_gpmc.c
Platform specific options
=========================
@ -231,6 +249,48 @@ Platform specific options
8-bit BCH code with
- ecc calculation using GPMC hardware engine,
- error detection using ELM hardware engine.
OMAP_ECC_BCH16_CODE_HW
16-bit BCH code with
- ecc calculation using GPMC hardware engine,
- error detection using ELM hardware engine.
How to select ECC scheme on OMAP and AMxx platforms ?
-----------------------------------------------------
Though higher ECC schemes have more capability to detect and correct
bit-flips, but still selection of ECC scheme is dependent on following
- hardware engines present in SoC.
Some legacy OMAP SoC do not have ELM h/w engine thus such
SoC cannot support BCHx_HW ECC schemes.
- size of OOB/Spare region
With higher ECC schemes, more OOB/Spare area is required to
store ECC. So choice of ECC scheme is limited by NAND oobsize.
In general following expression can help:
NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES
where
NAND_OOBSIZE = number of bytes available in
OOB/spare area per NAND page.
NAND_PAGESIZE = bytes in main-area of NAND page.
ECC_BYTES = number of ECC bytes generated to
protect 512 bytes of data, which is:
3 for HAM1_xx ecc schemes
7 for BCH4_xx ecc schemes
14 for BCH8_xx ecc schemes
26 for BCH16_xx ecc schemes
example to check for BCH16 on 2K page NAND
NAND_PAGESIZE = 2048
NAND_OOBSIZE = 64
2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE
Thus BCH16 cannot be supported on 2K page NAND.
However, for 4K pagesize NAND
NAND_PAGESIZE = 4096
NAND_OOBSIZE = 64
ECC_BYTES = 26
2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
Thus BCH16 can be supported on 4K page NAND.
NOTE:
=====

8
doc/device-tree-bindings/exynos/dwmmc.txt
View File

@ -1,18 +1,18 @@
* Exynos 5250 DWC_mobile_storage
* Exynos DWC_mobile_storage
The Exynos 5250 provides DWC_mobile_storage interface which supports
The Exynos provides DWC_mobile_storage interface which supports
. Embedded Multimedia Cards (EMMC-version 4.5)
. Secure Digital memory (SD mem-version 2.0)
. Secure Digital I/O (SDIO-version 3.0)
. Consumer Electronics Advanced Transport Architecture (CE-ATA-version 1.1)
The Exynos 5250 DWC_mobile_storage provides four channels.
The Exynos DWC_mobile_storage provides four channels.
SOC specific and Board specific properties are channel specific.
Required SoC Specific Properties:
- compatible: should be
- samsung,exynos5250-dwmmc: for exynos5250 platforms
- samsung,exynos-dwmmc: for exynos platforms
- reg: physical base address of the controller and length of memory mapped
region.

17
doc/device-tree-bindings/power/tps65090.txt 100644
View File

@ -0,0 +1,17 @@
TPS65090 Frontend PMU with Switchmode Charger
Required Properties:
-compatible: "ti,tps65090-charger"
Optional Properties:
-ti,enable-low-current-chrg: Enables charging when a low current is detected
while the default logic is to stop charging.
This node is a subnode of the tps65090 PMIC.
Example:
tps65090-charger {
compatible = "ti,tps65090-charger";
ti,enable-low-current-chrg;
};

122
doc/device-tree-bindings/regulator/tps65090.txt 100644
View File

@ -0,0 +1,122 @@
TPS65090 regulators
Required properties:
- compatible: "ti,tps65090"
- reg: I2C slave address
- interrupts: the interrupt outputs of the controller
- regulators: A node that houses a sub-node for each regulator within the
device. Each sub-node is identified using the node's name, with valid
values listed below. The content of each sub-node is defined by the
standard binding for regulators; see regulator.txt.
dcdc[1-3], fet[1-7] and ldo[1-2] respectively.
- vsys[1-3]-supply: The input supply for DCDC[1-3] respectively.
- infet[1-7]-supply: The input supply for FET[1-7] respectively.
- vsys-l[1-2]-supply: The input supply for LDO[1-2] respectively.
Optional properties:
- ti,enable-ext-control: This is applicable for DCDC1, DCDC2 and DCDC3.
If DCDCs are externally controlled then this property should be there.
- "dcdc-ext-control-gpios: This is applicable for DCDC1, DCDC2 and DCDC3.
If DCDCs are externally controlled and if it is from GPIO then GPIO
number should be provided. If it is externally controlled and no GPIO
entry then driver will just configure this rails as external control
and will not provide any enable/disable APIs.
Each regulator is defined using the standard binding for regulators.
Example:
tps65090@48 {
compatible = "ti,tps65090";
reg = <0x48>;
interrupts = <0 88 0x4>;
vsys1-supply = <&some_reg>;
vsys2-supply = <&some_reg>;
vsys3-supply = <&some_reg>;
infet1-supply = <&some_reg>;
infet2-supply = <&some_reg>;
infet3-supply = <&some_reg>;
infet4-supply = <&some_reg>;
infet5-supply = <&some_reg>;
infet6-supply = <&some_reg>;
infet7-supply = <&some_reg>;
vsys_l1-supply = <&some_reg>;
vsys_l2-supply = <&some_reg>;
regulators {
dcdc1 {
regulator-name = "dcdc1";
regulator-boot-on;
regulator-always-on;
ti,enable-ext-control;
dcdc-ext-control-gpios = <&gpio 10 0>;
};
dcdc2 {
regulator-name = "dcdc2";
regulator-boot-on;
regulator-always-on;
};
dcdc3 {
regulator-name = "dcdc3";
regulator-boot-on;
regulator-always-on;
};
fet1 {
regulator-name = "fet1";
regulator-boot-on;
regulator-always-on;
};
fet2 {
regulator-name = "fet2";
regulator-boot-on;
regulator-always-on;
};
fet3 {
regulator-name = "fet3";
regulator-boot-on;
regulator-always-on;
};
fet4 {
regulator-name = "fet4";
regulator-boot-on;
regulator-always-on;
};
fet5 {
regulator-name = "fet5";
regulator-boot-on;
regulator-always-on;
};
fet6 {
regulator-name = "fet6";
regulator-boot-on;
regulator-always-on;
};
fet7 {
regulator-name = "fet7";
regulator-boot-on;
regulator-always-on;
};
ldo1 {
regulator-name = "ldo1";
regulator-boot-on;
regulator-always-on;
};
ldo2 {
regulator-name = "ldo2";
regulator-boot-on;
regulator-always-on;
};
};
};

12
drivers/mmc/dw_mmc.c
View File

@ -284,8 +284,8 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
static void dwmci_set_ios(struct mmc *mmc)
{
struct dwmci_host *host = mmc->priv;
u32 ctype;
struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
u32 ctype, regs;
debug("Buswidth = %d, clock: %d\n",mmc->bus_width, mmc->clock);
@ -304,6 +304,14 @@ static void dwmci_set_ios(struct mmc *mmc)
dwmci_writel(host, DWMCI_CTYPE, ctype);
regs = dwmci_readl(host, DWMCI_UHS_REG);
if (mmc->card_caps & MMC_MODE_DDR_52MHz)
regs |= DWMCI_DDR_MODE;
else
regs &= DWMCI_DDR_MODE;
dwmci_writel(host, DWMCI_UHS_REG, regs);
if (host->clksel)
host->clksel(host);
}

211
drivers/mmc/exynos_dw_mmc.c
View File

@ -13,6 +13,8 @@
#include <asm/arch/dwmmc.h>
#include <asm/arch/clk.h>
#include <asm/arch/pinmux.h>
#include <asm/gpio.h>
#include <asm-generic/errno.h>
#define DWMMC_MAX_CH_NUM 4
#define DWMMC_MAX_FREQ 52000000
@ -44,7 +46,11 @@ unsigned int exynos_dwmci_get_clk(struct dwmci_host *host)
& DWMCI_DIVRATIO_MASK) + 1;
sclk = get_mmc_clk(host->dev_index);
return sclk / clk_div;
/*
* Assume to know divider value.
* When clock unit is broken, need to set "host->div"
*/
return sclk / clk_div / (host->div + 1);
}
static void exynos_dwmci_board_init(struct dwmci_host *host)
@ -60,48 +66,36 @@ static void exynos_dwmci_board_init(struct dwmci_host *host)
}
}
/*
* This function adds the mmc channel to be registered with mmc core.
* index - mmc channel number.
* regbase - register base address of mmc channel specified in 'index'.
* bus_width - operating bus width of mmc channel specified in 'index'.
* clksel - value to be written into CLKSEL register in case of FDT.
* NULL in case od non-FDT.
*/
int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
static int exynos_dwmci_core_init(struct dwmci_host *host, int index)
{
struct dwmci_host *host = NULL;
unsigned int div;
unsigned long freq, sclk;
host = malloc(sizeof(struct dwmci_host));
if (!host) {
printf("dwmci_host malloc fail!\n");
return 1;
}
if (host->bus_hz)
freq = host->bus_hz;
else
freq = DWMMC_MAX_FREQ;
/* request mmc clock vlaue of 52MHz. */
freq = 52000000;
sclk = get_mmc_clk(index);
div = DIV_ROUND_UP(sclk, freq);
/* set the clock divisor for mmc */
set_mmc_clk(index, div);
host->name = "EXYNOS DWMMC";
host->ioaddr = (void *)regbase;
host->buswidth = bus_width;
#ifdef CONFIG_EXYNOS5420
host->quirks = DWMCI_QUIRK_DISABLE_SMU;
#endif
host->board_init = exynos_dwmci_board_init;
if (clksel) {
host->clksel_val = clksel;
} else {
if (0 == index)
if (!host->clksel_val) {
if (index == 0)
host->clksel_val = DWMMC_MMC0_CLKSEL_VAL;
if (2 == index)
else if (index == 2)
host->clksel_val = DWMMC_MMC2_CLKSEL_VAL;
}
host->caps = MMC_MODE_DDR_52MHz;
host->clksel = exynos_dwmci_clksel;
host->dev_index = index;
host->get_mmc_clk = exynos_dwmci_get_clk;
@ -113,69 +107,134 @@ int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
return 0;
}
#ifdef CONFIG_OF_CONTROL
int exynos_dwmmc_init(const void *blob)
/*
* This function adds the mmc channel to be registered with mmc core.
* index - mmc channel number.
* regbase - register base address of mmc channel specified in 'index'.
* bus_width - operating bus width of mmc channel specified in 'index'.
* clksel - value to be written into CLKSEL register in case of FDT.
* NULL in case od non-FDT.
*/
int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
{
int index, bus_width;
int node_list[DWMMC_MAX_CH_NUM];
int err = 0, dev_id, flag, count, i;
u32 clksel_val, base, timing[3];
struct dwmci_host *host = NULL;
count = fdtdec_find_aliases_for_id(blob, "mmc",
COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list,
DWMMC_MAX_CH_NUM);
host = malloc(sizeof(struct dwmci_host));
if (!host) {
error("dwmci_host malloc fail!\n");
return -ENOMEM;
}
host->ioaddr = (void *)regbase;
host->buswidth = bus_width;
if (clksel)
host->clksel_val = clksel;
return exynos_dwmci_core_init(host, index);
}
#ifdef CONFIG_OF_CONTROL
static struct dwmci_host dwmci_host[DWMMC_MAX_CH_NUM];
static int do_dwmci_init(struct dwmci_host *host)
{
int index, flag, err;
index = host->dev_index;
flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
err = exynos_pinmux_config(host->dev_id, flag);
if (err) {
debug("DWMMC not configure\n");
return err;
}
return exynos_dwmci_core_init(host, index);
}
static int exynos_dwmci_get_config(const void *blob, int node,
struct dwmci_host *host)
{
int err = 0;
u32 base, clksel_val, timing[3];
/* Extract device id for each mmc channel */
host->dev_id = pinmux_decode_periph_id(blob, node);
/* Get the bus width from the device node */
host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
if (host->buswidth <= 0) {
debug("DWMMC: Can't get bus-width\n");
return -EINVAL;
}
host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id);
if (host->dev_index == host->dev_id)
host->dev_index = host->dev_id - PERIPH_ID_SDMMC0;
/* Set the base address from the device node */
base = fdtdec_get_addr(blob, node, "reg");
if (!base) {
debug("DWMMC: Can't get base address\n");
return -EINVAL;
}
host->ioaddr = (void *)base;
/* Extract the timing info from the node */
err = fdtdec_get_int_array(blob, node, "samsung,timing", timing, 3);
if (err) {
debug("Can't get sdr-timings for devider\n");
return -EINVAL;
}
clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) |
DWMCI_SET_DRV_CLK(timing[1]) |
DWMCI_SET_DIV_RATIO(timing[2]));
if (clksel_val)
host->clksel_val = clksel_val;
host->fifoth_val = fdtdec_get_int(blob, node, "fifoth_val", 0);
host->bus_hz = fdtdec_get_int(blob, node, "bus_hz", 0);
host->div = fdtdec_get_int(blob, node, "div", 0);
return 0;
}
static int exynos_dwmci_process_node(const void *blob,
int node_list[], int count)
{
struct dwmci_host *host;
int i, node, err;
for (i = 0; i < count; i++) {
int node = node_list[i];
node = node_list[i];
if (node <= 0)
continue;
/* Extract device id for each mmc channel */
dev_id = pinmux_decode_periph_id(blob, node);
/* Get the bus width from the device node */
bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
if (bus_width <= 0) {
debug("DWMMC: Can't get bus-width\n");
return -1;
}
if (8 == bus_width)
flag = PINMUX_FLAG_8BIT_MODE;
else
flag = PINMUX_FLAG_NONE;
/* config pinmux for each mmc channel */
err = exynos_pinmux_config(dev_id, flag);
host = &dwmci_host[i];
err = exynos_dwmci_get_config(blob, node, host);
if (err) {
debug("DWMMC not configured\n");
debug("%s: failed to decode dev %d\n", __func__, i);
return err;
}
index = dev_id - PERIPH_ID_SDMMC0;
/* Get the base address from the device node */
base = fdtdec_get_addr(blob, node, "reg");
if (!base) {
debug("DWMMC: Can't get base address\n");
return -1;
}
/* Extract the timing info from the node */
err = fdtdec_get_int_array(blob, node, "samsung,timing",
timing, 3);
if (err) {
debug("Can't get sdr-timings for divider\n");
return -1;
}
clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) |
DWMCI_SET_DRV_CLK(timing[1]) |
DWMCI_SET_DIV_RATIO(timing[2]));
/* Initialise each mmc channel */
err = exynos_dwmci_add_port(index, base, bus_width, clksel_val);
if (err)
debug("dwmmc Channel-%d init failed\n", index);
do_dwmci_init(host);
}
return 0;
}
int exynos_dwmmc_init(const void *blob)
{
int compat_id;
int node_list[DWMMC_MAX_CH_NUM];
int err = 0, count;
compat_id = COMPAT_SAMSUNG_EXYNOS_DWMMC;
count = fdtdec_find_aliases_for_id(blob, "mmc",
compat_id, node_list, DWMMC_MAX_CH_NUM);
err = exynos_dwmci_process_node(blob, node_list, count);
return err;
}
#endif

16
drivers/mmc/mmc.c
View File

@ -160,6 +160,9 @@ int mmc_set_blocklen(struct mmc *mmc, int len)
{
struct mmc_cmd cmd;
if (mmc->card_caps & MMC_MODE_DDR_52MHz)
return 0;
cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
cmd.resp_type = MMC_RSP_R1;
cmd.cmdarg = len;
@ -516,10 +519,13 @@ static int mmc_change_freq(struct mmc *mmc)
return 0;
/* High Speed is set, there are two types: 52MHz and 26MHz */
if (cardtype & MMC_HS_52MHZ)
if (cardtype & EXT_CSD_CARD_TYPE_52) {
if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
mmc->card_caps |= MMC_MODE_DDR_52MHz;
mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
else
} else {
mmc->card_caps |= MMC_MODE_HS;
}
return 0;
}
@ -1082,6 +1088,8 @@ static int mmc_startup(struct mmc *mmc)
/* An array of possible bus widths in order of preference */
static unsigned ext_csd_bits[] = {
EXT_CSD_DDR_BUS_WIDTH_8,
EXT_CSD_DDR_BUS_WIDTH_4,
EXT_CSD_BUS_WIDTH_8,
EXT_CSD_BUS_WIDTH_4,
EXT_CSD_BUS_WIDTH_1,
@ -1089,13 +1097,15 @@ static int mmc_startup(struct mmc *mmc)
/* An array to map CSD bus widths to host cap bits */
static unsigned ext_to_hostcaps[] = {
[EXT_CSD_DDR_BUS_WIDTH_4] = MMC_MODE_DDR_52MHz,
[EXT_CSD_DDR_BUS_WIDTH_8] = MMC_MODE_DDR_52MHz,
[EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
[EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
};
/* An array to map chosen bus width to an integer */
static unsigned widths[] = {
8, 4, 1,
8, 4, 8, 4, 1,
};
for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {

42
drivers/mmc/s5p_sdhci.c
View File

@ -65,17 +65,9 @@ static void s5p_sdhci_set_control_reg(struct sdhci_host *host)
sdhci_writel(host, ctrl, SDHCI_CONTROL2);
}
int s5p_sdhci_init(u32 regbase, int index, int bus_width)
static int s5p_sdhci_core_init(struct sdhci_host *host)
{
struct sdhci_host *host = NULL;
host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
if (!host) {
printf("sdhci__host malloc fail!\n");
return 1;
}
host->name = S5P_NAME;
host->ioaddr = (void *)regbase;
host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE |
SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR |
@ -85,15 +77,28 @@ int s5p_sdhci_init(u32 regbase, int index, int bus_width)
host->set_control_reg = &s5p_sdhci_set_control_reg;
host->set_clock = set_mmc_clk;
host->index = index;
host->host_caps = MMC_MODE_HC;
if (bus_width == 8)
if (host->bus_width == 8)
host->host_caps |= MMC_MODE_8BIT;
return add_sdhci(host, 52000000, 400000);
}
int s5p_sdhci_init(u32 regbase, int index, int bus_width)
{
struct sdhci_host *host = malloc(sizeof(struct sdhci_host));
if (!host) {
printf("sdhci__host malloc fail!\n");
return 1;
}
host->ioaddr = (void *)regbase;
host->index = index;
host->bus_width = bus_width;
return s5p_sdhci_core_init(host);
}
#ifdef CONFIG_OF_CONTROL
struct sdhci_host sdhci_host[SDHCI_MAX_HOSTS];
@ -126,20 +131,7 @@ static int do_sdhci_init(struct sdhci_host *host)
}
}
host->name = S5P_NAME;
host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE |
SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR |
SDHCI_QUIRK_WAIT_SEND_CMD;
host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
host->set_control_reg = &s5p_sdhci_set_control_reg;
host->set_clock = set_mmc_clk;
host->host_caps = MMC_MODE_HC;
return add_sdhci(host, 52000000, 400000);
return s5p_sdhci_core_init(host);
}
static int sdhci_get_config(const void *blob, int node, struct sdhci_host *host)

2
drivers/mtd/nand/am335x_spl_bch.c
View File

@ -55,7 +55,7 @@ static int nand_command(int block, int page, uint32_t offs,
}
/* Shift the offset from byte addressing to word addressing. */
if (this->options & NAND_BUSWIDTH_16)
if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
offs >>= 1;
/* Set ALE and clear CLE to start address cycle */

2
drivers/mtd/nand/atmel_nand.c
View File

@ -1195,7 +1195,7 @@ static int nand_command(int block, int page, uint32_t offs, u8 cmd)
hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
if (this->options & NAND_BUSWIDTH_16)
if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
offs >>= 1;
hwctrl(&mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);

11
drivers/mtd/nand/nand_base.c
View File

@ -575,7 +575,8 @@ static void nand_command(struct mtd_info *mtd, unsigned int command,
/* Serially input address */
if (column != -1) {
/* Adjust columns for 16 bit buswidth */
if (chip->options & NAND_BUSWIDTH_16)
if ((chip->options & NAND_BUSWIDTH_16) &&
!nand_opcode_8bits(command))
column >>= 1;
chip->cmd_ctrl(mtd, column, ctrl);
ctrl &= ~NAND_CTRL_CHANGE;
@ -668,7 +669,8 @@ static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
/* Serially input address */
if (column != -1) {
/* Adjust columns for 16 bit buswidth */
if (chip->options & NAND_BUSWIDTH_16)
if ((chip->options & NAND_BUSWIDTH_16) &&
!nand_opcode_8bits(command))
column >>= 1;
chip->cmd_ctrl(mtd, column, ctrl);
ctrl &= ~NAND_CTRL_CHANGE;
@ -2582,7 +2584,7 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
int *busw)
{
struct nand_onfi_params *p = &chip->onfi_params;
int i;
int i, j;
int val;
/* Try ONFI for unknown chip or LP */
@ -2593,7 +2595,8 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
for (i = 0; i < 3; i++) {
chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
for (j = 0; j < sizeof(*p); j++)
((uint8_t *)p)[j] = chip->read_byte(mtd);
if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
le16_to_cpu(p->crc)) {
pr_info("ONFI param page %d valid\n", i);

2
drivers/mtd/nand/nand_spl_simple.c
View File

@ -78,7 +78,7 @@ static int nand_command(int block, int page, uint32_t offs,
}
/* Shift the offset from byte addressing to word addressing. */
if (this->options & NAND_BUSWIDTH_16)
if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
offs >>= 1;
/* Begin command latch cycle */

28
drivers/mtd/nand/omap_elm.c
View File

@ -16,23 +16,21 @@
#include <common.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <linux/mtd/omap_gpmc.h>
#include <linux/mtd/omap_elm.h>
#include <asm/arch/hardware.h>
#define DRIVER_NAME "omap-elm"
#define ELM_DEFAULT_POLY (0)
struct elm *elm_cfg;
/**
* elm_load_syndromes - Load BCH syndromes based on nibble selection
* elm_load_syndromes - Load BCH syndromes based on bch_type selection
* @syndrome: BCH syndrome
* @nibbles:
* @bch_type: BCH4/BCH8/BCH16
* @poly: Syndrome Polynomial set to use
*
* Load BCH syndromes based on nibble selection
*/
static void elm_load_syndromes(u8 *syndrome, u32 nibbles, u8 poly)
static void elm_load_syndromes(u8 *syndrome, enum bch_level bch_type, u8 poly)
{
u32 *ptr;
u32 val;
@ -48,8 +46,7 @@ static void elm_load_syndromes(u8 *syndrome, u32 nibbles, u8 poly)
(syndrome[7] << 24);
writel(val, ptr);
/* BCH 8-bit with 26 nibbles (4*8=32) */
if (nibbles > 13) {
if (bch_type == BCH_8_BIT || bch_type == BCH_16_BIT) {
/* reg 2 */
ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[2];
val = syndrome[8] | (syndrome[9] << 8) | (syndrome[10] << 16) |
@ -62,8 +59,7 @@ static void elm_load_syndromes(u8 *syndrome, u32 nibbles, u8 poly)
writel(val, ptr);
}
/* BCH 16-bit with 52 nibbles (7*8=56) */
if (nibbles > 26) {
if (bch_type == BCH_16_BIT) {
/* reg 4 */
ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[4];
val = syndrome[16] | (syndrome[17] << 8) |
@ -87,7 +83,7 @@ static void elm_load_syndromes(u8 *syndrome, u32 nibbles, u8 poly)
/**
* elm_check_errors - Check for BCH errors and return error locations
* @syndrome: BCH syndrome
* @nibbles:
* @bch_type: BCH4/BCH8/BCH16
* @error_count: Returns number of errrors in the syndrome
* @error_locations: Returns error locations (in decimal) in this array
*
@ -95,14 +91,14 @@ static void elm_load_syndromes(u8 *syndrome, u32 nibbles, u8 poly)
* and locations in the array passed. Returns -1 if error is not correctable,
* else returns 0
*/
int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count,
int elm_check_error(u8 *syndrome, enum bch_level bch_type, u32 *error_count,
u32 *error_locations)
{
u8 poly = ELM_DEFAULT_POLY;
s8 i;
u32 location_status;
elm_load_syndromes(syndrome, nibbles, poly);
elm_load_syndromes(syndrome, bch_type, poly);
/* start processing */
writel((readl(&elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6])
@ -118,8 +114,10 @@ int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count,
/* check if correctable */
location_status = readl(&elm_cfg->error_location[poly].location_status);
if (!(location_status & ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK))
return -1;
if (!(location_status & ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK)) {
printf("%s: uncorrectable ECC errors\n", DRIVER_NAME);
return -EBADMSG;
}
/* get error count */
*error_count = readl(&elm_cfg->error_location[poly].location_status) &

193
drivers/mtd/nand/omap_gpmc.c
View File

@ -148,35 +148,20 @@ static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
}
/*
* Generic BCH interface
* Driver configurations
*/
struct nand_bch_priv {
uint8_t mode;
uint8_t type;
uint8_t nibbles;
struct omap_nand_info {
struct bch_control *control;
enum omap_ecc ecc_scheme;
};
/* bch types */
#define ECC_BCH4 0
#define ECC_BCH8 1
#define ECC_BCH16 2
/* BCH nibbles for diff bch levels */
#define ECC_BCH4_NIBBLES 13
#define ECC_BCH8_NIBBLES 26
#define ECC_BCH16_NIBBLES 52
/*
* This can be a single instance cause all current users have only one NAND
* with nearly the same setup (BCH8, some with ELM and others with sw BCH
* library).
* When some users with other BCH strength will exists this have to change!
*/
static __maybe_unused struct nand_bch_priv bch_priv = {
.type = ECC_BCH8,
.nibbles = ECC_BCH8_NIBBLES,
static __maybe_unused struct omap_nand_info omap_nand_info = {
.control = NULL
};
@ -206,7 +191,7 @@ __maybe_unused
static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
{
struct nand_chip *nand = mtd->priv;
struct nand_bch_priv *bch = nand->priv;
struct omap_nand_info *info = nand->priv;
unsigned int dev_width = (nand->options & NAND_BUSWIDTH_16) ? 1 : 0;
unsigned int ecc_algo = 0;
unsigned int bch_type = 0;
@ -215,7 +200,7 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
u32 ecc_config_val = 0;
/* configure GPMC for specific ecc-scheme */
switch (bch->ecc_scheme) {
switch (info->ecc_scheme) {
case OMAP_ECC_HAM1_CODE_SW:
return;
case OMAP_ECC_HAM1_CODE_HW:
@ -239,6 +224,19 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
eccsize1 = 2; /* non-ECC bits in nibbles per sector */
}
break;
case OMAP_ECC_BCH16_CODE_HW:
ecc_algo = 0x1;
bch_type = 0x2;
if (mode == NAND_ECC_WRITE) {
bch_wrapmode = 0x01;
eccsize0 = 0; /* extra bits in nibbles per sector */
eccsize1 = 52; /* OOB bits in nibbles per sector */
} else {
bch_wrapmode = 0x01;
eccsize0 = 52; /* ECC bits in nibbles per sector */
eccsize1 = 0; /* non-ECC bits in nibbles per sector */
}
break;
default:
return;
}
@ -277,11 +275,11 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
uint8_t *ecc_code)
{
struct nand_chip *chip = mtd->priv;
struct nand_bch_priv *bch = chip->priv;
struct omap_nand_info *info = chip->priv;
uint32_t *ptr, val = 0;
int8_t i = 0, j;
switch (bch->ecc_scheme) {
switch (info->ecc_scheme) {
case OMAP_ECC_HAM1_CODE_HW:
val = readl(&gpmc_cfg->ecc1_result);
ecc_code[0] = val & 0xFF;
@ -305,11 +303,34 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
ptr--;
}
break;
case OMAP_ECC_BCH16_CODE_HW:
val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[2]);
ecc_code[i++] = (val >> 8) & 0xFF;
ecc_code[i++] = (val >> 0) & 0xFF;
val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[1]);
ecc_code[i++] = (val >> 24) & 0xFF;
ecc_code[i++] = (val >> 16) & 0xFF;
ecc_code[i++] = (val >> 8) & 0xFF;
ecc_code[i++] = (val >> 0) & 0xFF;
val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[0]);
ecc_code[i++] = (val >> 24) & 0xFF;
ecc_code[i++] = (val >> 16) & 0xFF;
ecc_code[i++] = (val >> 8) & 0xFF;
ecc_code[i++] = (val >> 0) & 0xFF;
for (j = 3; j >= 0; j--) {
val = readl(&gpmc_cfg->bch_result_0_3[0].bch_result_x[j]
);
ecc_code[i++] = (val >> 24) & 0xFF;
ecc_code[i++] = (val >> 16) & 0xFF;
ecc_code[i++] = (val >> 8) & 0xFF;
ecc_code[i++] = (val >> 0) & 0xFF;
}
break;
default:
return -EINVAL;
}
/* ECC scheme specific syndrome customizations */
switch (bch->ecc_scheme) {
switch (info->ecc_scheme) {
case OMAP_ECC_HAM1_CODE_HW:
break;
#ifdef CONFIG_BCH
@ -323,6 +344,8 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
case OMAP_ECC_BCH8_CODE_HW:
ecc_code[chip->ecc.bytes - 1] = 0x00;
break;
case OMAP_ECC_BCH16_CODE_HW:
break;
default:
return -EINVAL;
}
@ -345,16 +368,17 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat,
uint8_t *read_ecc, uint8_t *calc_ecc)
{
struct nand_chip *chip = mtd->priv;
struct nand_bch_priv *bch = chip->priv;
uint32_t eccbytes = chip->ecc.bytes;
struct omap_nand_info *info = chip->priv;
struct nand_ecc_ctrl *ecc = &chip->ecc;
uint32_t error_count = 0, error_max;
uint32_t error_loc[8];
uint32_t error_loc[ELM_MAX_ERROR_COUNT];
enum bch_level bch_type;
uint32_t i, ecc_flag = 0;
uint8_t count, err = 0;
uint32_t byte_pos, bit_pos;
/* check calculated ecc */
for (i = 0; i < chip->ecc.bytes && !ecc_flag; i++) {
for (i = 0; i < ecc->bytes && !ecc_flag; i++) {
if (calc_ecc[i] != 0x00)
ecc_flag = 1;
}
@ -363,7 +387,7 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat,
/* check for whether its a erased-page */
ecc_flag = 0;
for (i = 0; i < chip->ecc.bytes && !ecc_flag; i++) {
for (i = 0; i < ecc->bytes && !ecc_flag; i++) {
if (read_ecc[i] != 0xff)
ecc_flag = 1;
}
@ -374,25 +398,33 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat,
* while reading ECC result we read it in big endian.
* Hence while loading to ELM we have rotate to get the right endian.
*/
switch (bch->ecc_scheme) {
switch (info->ecc_scheme) {
case OMAP_ECC_BCH8_CODE_HW:
omap_reverse_list(calc_ecc, eccbytes - 1);
bch_type = BCH_8_BIT;
omap_reverse_list(calc_ecc, ecc->bytes - 1);
break;
case OMAP_ECC_BCH16_CODE_HW:
bch_type = BCH_16_BIT;
omap_reverse_list(calc_ecc, ecc->bytes);
break;
default:
return -EINVAL;
}
/* use elm module to check for errors */
elm_config((enum bch_level)(bch->type));
if (elm_check_error(calc_ecc, bch->nibbles, &error_count, error_loc)) {
printf("nand: error: uncorrectable ECC errors\n");
return -EINVAL;
}
elm_config(bch_type);
err = elm_check_error(calc_ecc, bch_type, &error_count, error_loc);
if (err)
return err;
/* correct bch error */
for (count = 0; count < error_count; count++) {
switch (bch->type) {
case ECC_BCH8:
switch (info->ecc_scheme) {
case OMAP_ECC_BCH8_CODE_HW:
/* 14th byte in ECC is reserved to match ROM layout */
error_max = SECTOR_BYTES + (eccbytes - 1);
error_max = SECTOR_BYTES + (ecc->bytes - 1);
break;
case OMAP_ECC_BCH16_CODE_HW:
error_max = SECTOR_BYTES + ecc->bytes;
break;
default:
return -EINVAL;
@ -496,10 +528,10 @@ static int omap_correct_data_bch_sw(struct mtd_info *mtd, u_char *data,
/* cannot correct more than 8 errors */
unsigned int errloc[8];
struct nand_chip *chip = mtd->priv;
struct nand_bch_priv *chip_priv = chip->priv;
struct bch_control *bch = chip_priv->control;
struct omap_nand_info *info = chip->priv;
count = decode_bch(bch, NULL, 512, read_ecc, calc_ecc, NULL, errloc);
count = decode_bch(info->control, NULL, 512, read_ecc, calc_ecc,
NULL, errloc);
if (count > 0) {
/* correct errors */
for (i = 0; i < count; i++) {
@ -535,15 +567,11 @@ static int omap_correct_data_bch_sw(struct mtd_info *mtd, u_char *data,
static void __maybe_unused omap_free_bch(struct mtd_info *mtd)
{
struct nand_chip *chip = mtd->priv;
struct nand_bch_priv *chip_priv = chip->priv;
struct bch_control *bch = NULL;
struct omap_nand_info *info = chip->priv;
if (chip_priv)
bch = chip_priv->control;
if (bch) {
free_bch(bch);
chip_priv->control = NULL;
if (info->control) {
free_bch(info->control);
info->control = NULL;
}
}
#endif /* CONFIG_BCH */
@ -557,7 +585,7 @@ static void __maybe_unused omap_free_bch(struct mtd_info *mtd)
*/
static int omap_select_ecc_scheme(struct nand_chip *nand,
enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) {
struct nand_bch_priv *bch = nand->priv;
struct omap_nand_info *info = nand->priv;
struct nand_ecclayout *ecclayout = &omap_ecclayout;
int eccsteps = pagesize / SECTOR_BYTES;
int i;
@ -567,12 +595,10 @@ static int omap_select_ecc_scheme(struct nand_chip *nand,
debug("nand: selected OMAP_ECC_HAM1_CODE_SW\n");
/* For this ecc-scheme, ecc.bytes, ecc.layout, ... are
* initialized in nand_scan_tail(), so just set ecc.mode */
bch_priv.control = NULL;
bch_priv.type = 0;
info->control = NULL;
nand->ecc.mode = NAND_ECC_SOFT;
nand->ecc.layout = NULL;
nand->ecc.size = 0;
bch->ecc_scheme = OMAP_ECC_HAM1_CODE_SW;
break;
case OMAP_ECC_HAM1_CODE_HW:
@ -583,8 +609,7 @@ static int omap_select_ecc_scheme(struct nand_chip *nand,
(3 * eccsteps) + BADBLOCK_MARKER_LENGTH));
return -EINVAL;
}
bch_priv.control = NULL;
bch_priv.type = 0;
info->control = NULL;
/* populate ecc specific fields */
memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
nand->ecc.mode = NAND_ECC_HW;
@ -605,7 +630,6 @@ static int omap_select_ecc_scheme(struct nand_chip *nand,
ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
BADBLOCK_MARKER_LENGTH;
bch->ecc_scheme = OMAP_ECC_HAM1_CODE_HW;
break;
case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
@ -618,12 +642,11 @@ static int omap_select_ecc_scheme(struct nand_chip *nand,
return -EINVAL;
}
/* check if BCH S/W library can be used for error detection */
bch_priv.control = init_bch(13, 8, 0x201b);
if (!bch_priv.control) {
info->control = init_bch(13, 8, 0x201b);
if (!info->control) {
printf("nand: error: could not init_bch()\n");
return -ENODEV;
}
bch_priv.type = ECC_BCH8;
/* populate ecc specific fields */
memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
nand->ecc.mode = NAND_ECC_HW;
@ -647,7 +670,6 @@ static int omap_select_ecc_scheme(struct nand_chip *nand,
ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
BADBLOCK_MARKER_LENGTH;
bch->ecc_scheme = OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
break;
#else
printf("nand: error: CONFIG_BCH required for ECC\n");
@ -665,7 +687,7 @@ static int omap_select_ecc_scheme(struct nand_chip *nand,
}
/* intialize ELM for ECC error detection */
elm_init();
bch_priv.type = ECC_BCH8;
info->control = NULL;
/* populate ecc specific fields */
memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
nand->ecc.mode = NAND_ECC_HW;
@ -683,13 +705,44 @@ static int omap_select_ecc_scheme(struct nand_chip *nand,
ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
BADBLOCK_MARKER_LENGTH;
bch->ecc_scheme = OMAP_ECC_BCH8_CODE_HW;
break;
#else
printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n");
return -EINVAL;
#endif
case OMAP_ECC_BCH16_CODE_HW:
#ifdef CONFIG_NAND_OMAP_ELM
debug("nand: using OMAP_ECC_BCH16_CODE_HW\n");
/* check ecc-scheme requirements before updating ecc info */
if ((26 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
printf("nand: error: insufficient OOB: require=%d\n", (
(26 * eccsteps) + BADBLOCK_MARKER_LENGTH));
return -EINVAL;
}
/* intialize ELM for ECC error detection */
elm_init();
/* populate ecc specific fields */
nand->ecc.mode = NAND_ECC_HW;
nand->ecc.size = SECTOR_BYTES;
nand->ecc.bytes = 26;
nand->ecc.strength = 16;
nand->ecc.hwctl = omap_enable_hwecc;
nand->ecc.correct = omap_correct_data_bch;
nand->ecc.calculate = omap_calculate_ecc;
nand->ecc.read_page = omap_read_page_bch;
/* define ecc-layout */
ecclayout->eccbytes = nand->ecc.bytes * eccsteps;
for (i = 0; i < ecclayout->eccbytes; i++)
ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH;
ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
ecclayout->oobfree[0].length = oobsize - nand->ecc.bytes -
BADBLOCK_MARKER_LENGTH;
break;
#else
printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n");
return -EINVAL;
#endif
default:
debug("nand: error: ecc scheme not enabled or supported\n");
return -EINVAL;
@ -699,6 +752,7 @@ static int omap_select_ecc_scheme(struct nand_chip *nand,
if (ecc_scheme != OMAP_ECC_HAM1_CODE_SW)
nand->ecc.layout = ecclayout;
info->ecc_scheme = ecc_scheme;
return 0;
}
@ -802,16 +856,21 @@ int board_nand_init(struct nand_chip *nand)
nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
nand->priv = &bch_priv;
nand->priv = &omap_nand_info;
nand->cmd_ctrl = omap_nand_hwcontrol;
nand->options |= NAND_NO_PADDING | NAND_CACHEPRG;
/* If we are 16 bit dev, our gpmc config tells us that */
if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000)
nand->options |= NAND_BUSWIDTH_16;
nand->chip_delay = 100;
nand->ecc.layout = &omap_ecclayout;
/* configure driver and controller based on NAND device bus-width */
gpmc_config = readl(&gpmc_cfg->cs[cs].config1);
#if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT)
nand->options |= NAND_BUSWIDTH_16;
writel(gpmc_config | (0x1 << 12), &gpmc_cfg->cs[cs].config1);
#else
nand->options &= ~NAND_BUSWIDTH_16;
writel(gpmc_config & ~(0x1 << 12), &gpmc_cfg->cs[cs].config1);
#endif
/* select ECC scheme */
#if defined(CONFIG_NAND_OMAP_ECCSCHEME)
err = omap_select_ecc_scheme(nand, CONFIG_NAND_OMAP_ECCSCHEME,

4
drivers/power/battery/bat_trats.c
View File

@ -19,7 +19,7 @@ static int power_battery_charge(struct pmic *bat)
struct battery *battery = p_bat->bat;
int k;
if (bat->chrg->chrg_state(p_bat->chrg, CHARGER_ENABLE, 450))
if (bat->chrg->chrg_state(p_bat->chrg, PMIC_CHARGER_ENABLE, 450))
return -1;
for (k = 0; bat->chrg->chrg_bat_present(p_bat->chrg) &&
@ -42,7 +42,7 @@ static int power_battery_charge(struct pmic *bat)
}
}
exit:
bat->chrg->chrg_state(p_bat->chrg, CHARGER_DISABLE, 0);
bat->chrg->chrg_state(p_bat->chrg, PMIC_CHARGER_DISABLE, 0);
return 0;
}

2
drivers/power/battery/bat_trats2.c
View File

@ -17,7 +17,7 @@ static int power_battery_charge(struct pmic *bat)
{
struct power_battery *p_bat = bat->pbat;
if (bat->chrg->chrg_state(p_bat->chrg, CHARGER_ENABLE, 450))
if (bat->chrg->chrg_state(p_bat->chrg, PMIC_CHARGER_ENABLE, 450))
return -1;
return 0;

2
drivers/power/mfd/pmic_max77693.c
View File

@ -22,7 +22,7 @@ static int max77693_charger_state(struct pmic *p, int state, int current)
val = MAX77693_CHG_UNLOCK;
pmic_reg_write(p, MAX77693_CHG_CNFG_06, val);
if (state == CHARGER_DISABLE) {
if (state == PMIC_CHARGER_DISABLE) {
puts("Disable the charger.\n");
pmic_reg_read(p, MAX77693_CHG_CNFG_00, &val);
val &= ~0x01;

2
drivers/power/pmic/Makefile
View File

@ -11,5 +11,7 @@ obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o
obj-$(CONFIG_POWER_TPS65090) += pmic_tps65090.o
obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o
obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o

2
drivers/power/pmic/pmic_max8997.c
View File

@ -35,7 +35,7 @@ static int pmic_charger_state(struct pmic *p, int state, int current)
if (pmic_probe(p))
return -1;
if (state == CHARGER_DISABLE) {
if (state == PMIC_CHARGER_DISABLE) {
puts("Disable the charger.\n");
pmic_reg_read(p, MAX8997_REG_MBCCTRL2, &val);
val &= ~(MBCHOSTEN | VCHGR_FC);

310
drivers/power/pmic/pmic_tps65090.c 100644
View File

@ -0,0 +1,310 @@
/*
* Copyright (c) 2012 The Chromium OS Authors.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <errno.h>
#include <fdtdec.h>
#include <i2c.h>
#include <power/pmic.h>
#include <power/tps65090_pmic.h>
DECLARE_GLOBAL_DATA_PTR;
#define TPS65090_NAME "TPS65090_PMIC"
/* TPS65090 register addresses */
enum {
REG_IRQ1 = 0,
REG_CG_CTRL0 = 4,
REG_CG_STATUS1 = 0xa,
REG_FET1_CTRL = 0x0f,
REG_FET2_CTRL,
REG_FET3_CTRL,
REG_FET4_CTRL,
REG_FET5_CTRL,
REG_FET6_CTRL,
REG_FET7_CTRL,
TPS65090_NUM_REGS,
};
enum {
IRQ1_VBATG = 1 << 3,
CG_CTRL0_ENC_MASK = 0x01,
MAX_FET_NUM = 7,
MAX_CTRL_READ_TRIES = 5,
/* TPS65090 FET_CTRL register values */
FET_CTRL_TOFET = 1 << 7, /* Timeout, startup, overload */
FET_CTRL_PGFET = 1 << 4, /* Power good for FET status */
FET_CTRL_WAIT = 3 << 2, /* Overcurrent timeout max */
FET_CTRL_ADENFET = 1 << 1, /* Enable output auto discharge */
FET_CTRL_ENFET = 1 << 0, /* Enable FET */
};
/**
* Checks for a valid FET number
*
* @param fet_id FET number to check
* @return 0 if ok, -EINVAL if FET value is out of range
*/
static int tps65090_check_fet(unsigned int fet_id)
{
if (fet_id == 0 || fet_id > MAX_FET_NUM) {
debug("parameter fet_id is out of range, %u not in 1 ~ %u\n",
fet_id, MAX_FET_NUM);
return -EINVAL;
}
return 0;
}
/**
* Set the power state for a FET
*
* @param pmic pmic structure for the tps65090
* @param fet_id Fet number to set (1..MAX_FET_NUM)
* @param set 1 to power on FET, 0 to power off
* @return -EIO if we got a comms error, -EAGAIN if the FET failed to
* change state. If all is ok, returns 0.
*/
static int tps65090_fet_set(struct pmic *pmic, int fet_id, bool set)
{
int retry;
u32 reg, value;
value = FET_CTRL_ADENFET | FET_CTRL_WAIT;
if (set)
value |= FET_CTRL_ENFET;
if (pmic_reg_write(pmic, REG_FET1_CTRL + fet_id - 1, value))
return -EIO;
/* Try reading until we get a result */
for (retry = 0; retry < MAX_CTRL_READ_TRIES; retry++) {
if (pmic_reg_read(pmic, REG_FET1_CTRL + fet_id - 1, &reg))
return -EIO;
/* Check that the fet went into the expected state */
if (!!(reg & FET_CTRL_PGFET) == set)
return 0;
/* If we got a timeout, there is no point in waiting longer */
if (reg & FET_CTRL_TOFET)
break;
mdelay(1);
}
debug("FET %d: Power good should have set to %d but reg=%#02x\n",
fet_id, set, reg);
return -EAGAIN;
}
int tps65090_fet_enable(unsigned int fet_id)
{
struct pmic *pmic;
ulong start;
int loops;
int ret;
ret = tps65090_check_fet(fet_id);
if (ret)
return ret;
pmic = pmic_get(TPS65090_NAME);
if (!pmic)
return -EACCES;
start = get_timer(0);
for (loops = 0;; loops++) {
ret = tps65090_fet_set(pmic, fet_id, true);
if (!ret)
break;
if (get_timer(start) > 100)
break;
/* Turn it off and try again until we time out */
tps65090_fet_set(pmic, fet_id, false);
}
if (ret)
debug("%s: FET%d failed to power on: time=%lums, loops=%d\n",
__func__, fet_id, get_timer(start), loops);
else if (loops)
debug("%s: FET%d powered on after %lums, loops=%d\n",
__func__, fet_id, get_timer(start), loops);
/*
* Unfortunately, there are some conditions where the power
* good bit will be 0, but the fet still comes up. One such
* case occurs with the lcd backlight. We'll just return 0 here
* and assume that the fet will eventually come up.
*/
if (ret == -EAGAIN)
ret = 0;
return ret;
}
int tps65090_fet_disable(unsigned int fet_id)
{
struct pmic *pmic;
int ret;
ret = tps65090_check_fet(fet_id);
if (ret)
return ret;
pmic = pmic_get(TPS65090_NAME);
if (!pmic)
return -EACCES;
ret = tps65090_fet_set(pmic, fet_id, false);
return ret;
}
int tps65090_fet_is_enabled(unsigned int fet_id)
{
struct pmic *pmic;
u32 reg;
int ret;
ret = tps65090_check_fet(fet_id);
if (ret)
return ret;
pmic = pmic_get(TPS65090_NAME);
if (!pmic)
return -ENODEV;
ret = pmic_reg_read(pmic, REG_FET1_CTRL + fet_id - 1, &reg);
if (ret) {
debug("fail to read FET%u_CTRL register over I2C", fet_id);
return -EIO;
}
return reg & FET_CTRL_ENFET;
}
int tps65090_get_charging(void)
{
struct pmic *pmic;
u32 val;
int ret;
pmic = pmic_get(TPS65090_NAME);
if (!pmic)
return -EACCES;
ret = pmic_reg_read(pmic, REG_CG_CTRL0, &val);
if (ret)
return ret;
return !!(val & CG_CTRL0_ENC_MASK);
}
static int tps65090_charger_state(struct pmic *pmic, int state,
int current)
{
u32 val;
int ret;
ret = pmic_reg_read(pmic, REG_CG_CTRL0, &val);
if (!ret) {
if (state == PMIC_CHARGER_ENABLE)
val |= CG_CTRL0_ENC_MASK;
else
val &= ~CG_CTRL0_ENC_MASK;
ret = pmic_reg_write(pmic, REG_CG_CTRL0, val);
}
if (ret) {
debug("%s: Failed to read/write register\n", __func__);
return ret;
}
return 0;
}
int tps65090_get_status(void)
{
struct pmic *pmic;
u32 val;
int ret;
pmic = pmic_get(TPS65090_NAME);
if (!pmic)
return -EACCES;
ret = pmic_reg_read(pmic, REG_CG_STATUS1, &val);
if (ret)
return ret;
return val;
}
static int tps65090_charger_bat_present(struct pmic *pmic)
{
u32 val;
int ret;
ret = pmic_reg_read(pmic, REG_IRQ1, &val);
if (ret)
return ret;
return !!(val & IRQ1_VBATG);
}
static struct power_chrg power_chrg_pmic_ops = {
.chrg_bat_present = tps65090_charger_bat_present,
.chrg_state = tps65090_charger_state,
};
int tps65090_init(void)
{
struct pmic *p;
int bus;
int addr;
const void *blob = gd->fdt_blob;
int node, parent;
node = fdtdec_next_compatible(blob, 0, COMPAT_TI_TPS65090);
if (node < 0) {
debug("PMIC: No node for PMIC Chip in device tree\n");
debug("node = %d\n", node);
return -ENODEV;
}
parent = fdt_parent_offset(blob, node);
if (parent < 0) {
debug("%s: Cannot find node parent\n", __func__);
return -EINVAL;
}
bus = i2c_get_bus_num_fdt(parent);
if (p->bus < 0) {
debug("%s: Cannot find I2C bus\n", __func__);
return -ENOENT;
}
addr = fdtdec_get_int(blob, node, "reg", TPS65090_I2C_ADDR);
p = pmic_alloc();
if (!p) {
printf("%s: POWER allocation error!\n", __func__);
return -ENOMEM;
}
p->name = TPS65090_NAME;
p->bus = bus;
p->interface = PMIC_I2C;
p->number_of_regs = TPS65090_NUM_REGS;
p->hw.i2c.addr = addr;
p->hw.i2c.tx_num = 1;
p->chrg = &power_chrg_pmic_ops;
puts("TPS65090 PMIC init\n");
return 0;
}

97
drivers/power/pmic/pmic_tps65218.c 100644
View File

@ -0,0 +1,97 @@
/*
* (C) Copyright 2011-2013
* Texas Instruments, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <i2c.h>
#include <power/tps65218.h>
/**
* tps65218_reg_write() - Generic function that can write a TPS65218 PMIC
* register or bit field regardless of protection
* level.
*
* @prot_level: Register password protection. Use
* TPS65218_PROT_LEVEL_NONE,
* TPS65218_PROT_LEVEL_1 or TPS65218_PROT_LEVEL_2
* @dest_reg: Register address to write.
* @dest_val: Value to write.
* @mask: Bit mask (8 bits) to be applied. Function will only
* change bits that are set in the bit mask.
*
* @return: 0 for success, not 0 on failure, as per the i2c API
*/
int tps65218_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val,
uchar mask)
{
uchar read_val;
uchar xor_reg;
int ret;
/*
* If we are affecting only a bit field, read dest_reg and apply the
* mask
*/
if (mask != TPS65218_MASK_ALL_BITS) {
ret = i2c_read(TPS65218_CHIP_PM, dest_reg, 1, &read_val, 1);
if (ret)
return ret;
read_val &= (~mask);
read_val |= (dest_val & mask);
dest_val = read_val;
}
if (prot_level > 0) {
xor_reg = dest_reg ^ TPS65218_PASSWORD_UNLOCK;
ret = i2c_write(TPS65218_CHIP_PM, TPS65218_PASSWORD, 1,
&xor_reg, 1);
if (ret)
return ret;
}
ret = i2c_write(TPS65218_CHIP_PM, dest_reg, 1, &dest_val, 1);
if (ret)
return ret;
if (prot_level == TPS65218_PROT_LEVEL_2) {
ret = i2c_write(TPS65218_CHIP_PM, TPS65218_PASSWORD, 1,
&xor_reg, 1);
if (ret)
return ret;
ret = i2c_write(TPS65218_CHIP_PM, dest_reg, 1, &dest_val, 1);
if (ret)
return ret;
}
return 0;
}
/**
* tps65218_voltage_update() - Function to change a voltage level, as this
* is a multi-step process.
* @dc_cntrl_reg: DC voltage control register to change.
* @volt_sel: New value for the voltage register
* @return: 0 for success, not 0 on failure.
*/
int tps65218_voltage_update(uchar dc_cntrl_reg, uchar volt_sel)
{
if ((dc_cntrl_reg != TPS65218_DCDC1) &&
(dc_cntrl_reg != TPS65218_DCDC2))
return 1;
/* set voltage level */
if (tps65218_reg_write(TPS65218_PROT_LEVEL_2, dc_cntrl_reg, volt_sel,
TPS65218_MASK_ALL_BITS))
return 1;
/* set GO bit to initiate voltage transition */
if (tps65218_reg_write(TPS65218_PROT_LEVEL_2, TPS65218_SLEW,
TPS65218_DCDC_GO, TPS65218_DCDC_GO))
return 1;
return 0;
}

6
drivers/power/power_fsl.c
View File

@ -11,9 +11,9 @@
#include <fsl_pmic.h>
#include <errno.h>
#if defined(CONFIG_PMIC_FSL_MC13892)
#if defined(CONFIG_POWER_FSL_MC13892)
#define FSL_PMIC_I2C_LENGTH 3
#elif defined(CONFIG_PMIC_FSL_MC34704)
#elif defined(CONFIG_POWER_FSL_MC34704)
#define FSL_PMIC_I2C_LENGTH 1
#endif
@ -51,7 +51,7 @@ int pmic_init(unsigned char bus)
p->hw.i2c.addr = CONFIG_SYS_FSL_PMIC_I2C_ADDR;
p->hw.i2c.tx_num = FSL_PMIC_I2C_LENGTH;
#else
#error "You must select CONFIG_POWER_SPI or CONFIG_PMIC_I2C"
#error "You must select CONFIG_POWER_SPI or CONFIG_POWER_I2C"
#endif
return 0;

4
drivers/power/power_i2c.c
View File

@ -23,6 +23,8 @@ int pmic_reg_write(struct pmic *p, u32 reg, u32 val)
if (check_reg(p, reg))
return -1;
I2C_SET_BUS(p->bus);
switch (pmic_i2c_tx_num) {
case 3:
if (p->sensor_byte_order == PMIC_SENSOR_BYTE_ORDER_BIG) {
@ -66,6 +68,8 @@ int pmic_reg_read(struct pmic *p, u32 reg, u32 *val)
if (check_reg(p, reg))
return -1;
I2C_SET_BUS(p->bus);
if (i2c_read(pmic_i2c_addr, reg, 1, buf, pmic_i2c_tx_num))
return -1;

1
drivers/spi/ti_qspi.c
View File

@ -106,6 +106,7 @@ static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave)
slave->memory_map = (void *)MMAP_START_ADDR_DRA;
#else
slave->memory_map = (void *)MMAP_START_ADDR_AM43x;
slave->op_mode_rx = 8;
#endif
memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |

1
include/configs/am3517_crane.h
View File

@ -329,6 +329,7 @@
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
/* NAND boot config */
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_PAGE_SIZE 2048

45
include/configs/am43xx_evm.h
View File

@ -32,11 +32,15 @@
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_I2C_MULTI_EEPROMS
/* Power */
#define CONFIG_POWER_TPS65218
/* SPL defines. */
#define CONFIG_SPL_TEXT_BASE 0x40300350
#define CONFIG_SPL_MAX_SIZE (220 << 10) /* 220KB */
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
(128 << 20))
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_YMODEM_SUPPORT
/* Enabling L2 Cache */
@ -48,15 +52,24 @@
* Since SPL did pll and ddr initialization for us,
* we don't need to do it twice.
*/
#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT)
#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_QSPI_BOOT)
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
/*
* When building U-Boot such that there is no previous loader
* we need to call board_early_init_f. This is taken care of in
* s_init when we have SPL used.
*/
#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && !defined(CONFIG_SPL)
#define CONFIG_BOARD_EARLY_INIT_F
#endif
/* Now bring in the rest of the common code. */
#include <configs/ti_armv7_common.h>
/* Always 128 KiB env size */
#define CONFIG_ENV_SIZE (128 << 10)
/* Always 64 KiB env size */
#define CONFIG_ENV_SIZE (64 << 10)
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
@ -86,6 +99,30 @@
#define CONFIG_OMAP_USB_PHY
#define CONFIG_AM437X_USB2PHY2_HOST
#ifdef CONFIG_QSPI_BOOT
#define CONFIG_SYS_TEXT_BASE 0x30000000
#undef CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64 KB sectors */
#define CONFIG_ENV_OFFSET 0x110000
#define CONFIG_ENV_OFFSET_REDUND 0x120000
#ifdef MTDIDS_DEFAULT
#undef MTDIDS_DEFAULT
#endif
#ifdef MTDPARTS_DEFAULT
#undef MTDPARTS_DEFAULT
#endif
#define MTDPARTS_DEFAULT "mtdparts=qspi.0:512k(QSPI.u-boot)," \
"512k(QSPI.u-boot.backup)," \
"512k(QSPI.u-boot-spl-os)," \
"64k(QSPI.u-boot-env)," \
"64k(QSPI.u-boot-env.backup)," \
"8m(QSPI.kernel)," \
"-(QSPI.file-system)"
#endif
/* SPI */
#undef CONFIG_OMAP3_SPI
#define CONFIG_TI_QSPI
@ -94,6 +131,7 @@
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_TI_SPI_MMAP
#define CONFIG_SPI_FLASH_BAR
#define CONFIG_QSPI_SEL_GPIO 48
#define CONFIG_SF_DEFAULT_SPEED 48000000
#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3
@ -145,6 +183,7 @@
"loadfdt=load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
"mmcboot=mmc dev ${mmcdev}; " \
"setenv devnum ${mmcdev}; " \
"setenv devtype mmc; " \
"if mmc rescan; then " \
"echo SD/MMC found on device ${devnum};" \
"if run loadbootenv; then " \

4
include/configs/arndale.h
View File

@ -224,8 +224,8 @@
/* PMIC */
#define CONFIG_PMIC
#define CONFIG_PMIC_I2C
#define CONFIG_PMIC_MAX77686
#define CONFIG_POWER_I2C
#define CONFIG_POWER_MAX77686
#define CONFIG_DEFAULT_DEVICE_TREE exynos5250-arndale

2
include/configs/beaver.h
View File

@ -76,6 +76,7 @@
/* USB Host support */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_USB
@ -87,6 +88,7 @@
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
#include "tegra-common-ums.h"
#include "tegra-common-post.h"
#endif /* __CONFIG_H */

4
include/configs/bur_am335x_common.h
View File

@ -12,6 +12,8 @@
#ifndef __BUR_AM335X_COMMON_H__
#define __BUR_AM335X_COMMON_H__
/* ------------------------------------------------------------------------- */
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_AM33XX
#define CONFIG_OMAP
#define CONFIG_OMAP_COMMON
@ -94,7 +96,7 @@
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
#define CONFIG_SYS_I2C_OMAP24XX
#define CONFIG_CMD_I2C
/* GPIO */
#define CONFIG_OMAP_GPIO
#define CONFIG_CMD_GPIO

1
include/configs/cm_t335.h
View File

@ -141,7 +141,6 @@
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
#define CONFIG_CMD_NAND
#define GPMC_NAND_ECC_LP_x8_LAYOUT
#define MTDIDS_DEFAULT "nand0=nand"
#define MTDPARTS_DEFAULT "mtdparts=nand:2m(spl)," \
"1m(u-boot),1m(u-boot-env)," \

1
include/configs/cm_t35.h
View File

@ -158,7 +158,6 @@
/* CS0 */
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
#define GPMC_NAND_ECC_LP_x8_LAYOUT
/* Environment information */
#define CONFIG_BOOTDELAY 3

1
include/configs/devkit8000.h
View File

@ -314,6 +314,7 @@
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
/* NAND boot config */
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_PAGE_SIZE 2048

1
include/configs/dig297.h
View File

@ -138,6 +138,7 @@
* Board NAND Info.
*/
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
/* to access nand */
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */

4
include/configs/exynos4-dt.h
View File

@ -20,6 +20,7 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_COMMON
#define CONFIG_SYS_GENERIC_BOARD
/* Enable fdt support */
#define CONFIG_OF_CONTROL
@ -44,6 +45,9 @@
#define CONFIG_S5P_SDHCI
#define CONFIG_SDHCI
#define CONFIG_MMC_SDMA
#define CONFIG_DWMMC
#define CONFIG_EXYNOS_DWMMC
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_MMC_DEFAULT_DEV 0
/* PWM */

1
include/configs/exynos5-dt.h
View File

@ -259,6 +259,7 @@
/* PMIC */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_TPS65090
/* Ethernet Controllor Driver */
#ifdef CONFIG_CMD_NET

2
include/configs/exynos5250-dt.h
View File

@ -45,7 +45,7 @@
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK
/* PMIC */
#define CONFIG_PMIC_MAX77686
#define CONFIG_POWER_MAX77686
/* Sound */
#define CONFIG_CMD_SOUND

2
include/configs/jetson-tk1.h
View File

@ -63,6 +63,7 @@
/* USB Host support */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_USB
@ -74,6 +75,7 @@
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
#include "tegra-common-ums.h"
#include "tegra-common-post.h"
#endif /* __CONFIG_H */

4
include/configs/k2hk_evm.h
View File

@ -71,7 +71,8 @@
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_SYS_NS16550_REG_SIZE -4
#define CONFIG_SYS_NS16550_COM1 K2HK_UART0_BASE
#define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE
#define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE
#define CONFIG_SYS_NS16550_CLK clk_get_rate(K2HK_CLK1_6)
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
@ -130,6 +131,7 @@
/* NAND Configuration */
#define CONFIG_NAND_DAVINCI
#define CONFIG_CMD_NAND_ECCLAYOUT
#define CONFIG_SYS_NAND_CS 2
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST

2
include/configs/mx25pdk.h
View File

@ -107,7 +107,7 @@
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_FSL
#define CONFIG_PMIC_FSL_MC34704
#define CONFIG_POWER_FSL_MC34704
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x54
#define CONFIG_DOS_PARTITION

2
include/configs/mx35pdk.h
View File

@ -52,7 +52,7 @@
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_FSL
#define CONFIG_PMIC_FSL_MC13892
#define CONFIG_POWER_FSL_MC13892
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x08
#define CONFIG_RTC_MC13XXX

2
include/configs/mx53evk.h
View File

@ -47,7 +47,7 @@
#define CONFIG_POWER_I2C
#define CONFIG_POWER_FSL
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 8
#define CONFIG_PMIC_FSL_MC13892
#define CONFIG_POWER_FSL_MC13892
#define CONFIG_RTC_MC13XXX
/* MMC Configs */

2
include/configs/mx53loco.h
View File

@ -82,7 +82,7 @@
#define CONFIG_POWER_I2C
#define CONFIG_DIALOG_POWER
#define CONFIG_POWER_FSL
#define CONFIG_PMIC_FSL_MC13892
#define CONFIG_POWER_FSL_MC13892
#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8

1
include/configs/omap3_beagle.h
View File

@ -295,6 +295,7 @@
#define CONFIG_SPL_OMAP3_ID_NAND
/* NAND boot config */
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_PAGE_SIZE 2048

2
include/configs/omap3_evm_common.h
View File

@ -120,7 +120,7 @@
/* Max number of NAND devices */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
/* Timeout values (in ticks) */
#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)

1
include/configs/omap3_igep00x0.h
View File

@ -187,6 +187,7 @@
/* NAND boot config */
#ifdef CONFIG_NAND
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_PAGE_SIZE 2048

1
include/configs/omap3_logic.h
View File

@ -141,6 +141,7 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
/* NAND devices */
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV "nand0"

1
include/configs/omap3_overo.h
View File

@ -206,6 +206,7 @@
#define CONFIG_SYS_CACHELINE_SIZE 64
/* NAND boot config */
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_PAGE_SIZE 2048

1
include/configs/omap3_zoom1.h
View File

@ -98,6 +98,7 @@
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access nand at */
/* CS0 */
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
/* Environment information */

1
include/configs/pengwyn.h
View File

@ -149,7 +149,6 @@
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
#define GPMC_NAND_ECC_LP_x8_LAYOUT 1
#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \
"128k(SPL.backup1)," \

113
include/configs/s5p_goni.h
View File

@ -17,6 +17,7 @@
#define CONFIG_S5PC110 1 /* which is in a S5PC110 */
#define CONFIG_MACH_GONI 1 /* working with Goni */
#include <linux/sizes.h>
#include <asm/arch/cpu.h> /* get chip and board defs */
#define CONFIG_ARCH_CPU_INIT
@ -38,11 +39,9 @@
#define CONFIG_INITRD_TAG
#define CONFIG_CMDLINE_EDITING
/*
* Size of malloc() pool
* 1MB = 0x100000, 0x100000 = 1024 * 1024
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
/* Size of malloc() pool.*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 80 * SZ_1M)
/*
* select serial console configuration
*/
@ -72,14 +71,19 @@
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_ONENAND
#define CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_MMC
#define CONFIG_CMD_DFU
#define CONFIG_CMD_GPT
#define CONFIG_BOOTDELAY 1
#define CONFIG_ZERO_BOOTDELAY_CHECK
/* USB Composite download gadget - g_dnl */
#define CONFIG_USBDOWNLOAD_GADGET
#define CONFIG_DFU_FUNCTION
#define CONFIG_DFU_MMC
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
/* USB Samsung's IDs */
#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
#define CONFIG_G_DNL_MANUFACTURER "Samsung"
/* Actual modem binary size is 16MiB. Add 2MiB for bad block handling */
#define MTDIDS_DEFAULT "onenand0=samsung-onenand"
@ -90,30 +94,52 @@
",7m(kernel)"\
",1m(log)"\
",12m(modem)"\
",60m(qboot)"\
",-(UBI)\0"
",60m(qboot)\0"
#define NORMAL_MTDPARTS_DEFAULT MTDPARTS_DEFAULT
#define CONFIG_BOOTDELAY 1
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_BOOTCOMMAND "run ubifsboot"
/* partitions definitions */
#define PARTS_CSA "csa-mmc"
#define PARTS_BOOTLOADER "u-boot"
#define PARTS_BOOT "boot"
#define PARTS_ROOT "platform"
#define PARTS_DATA "data"
#define PARTS_CSC "csc"
#define PARTS_UMS "ums"
#define CONFIG_DFU_ALT \
"u-boot raw 0x80 0x400;" \
"uImage ext4 0 2;" \
"exynos3-goni.dtb ext4 0 2;" \
""PARTS_ROOT" part 0 5\0"
#define PARTS_DEFAULT \
"uuid_disk=${uuid_gpt_disk};" \
"name="PARTS_CSA",size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
"name="PARTS_BOOTLOADER",size=60MiB," \
"uuid=${uuid_gpt_"PARTS_BOOTLOADER"};" \
"name="PARTS_BOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
"name="PARTS_ROOT",size=1GiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
"name="PARTS_DATA",size=3GiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
"name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
"name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
#define CONFIG_BOOTCOMMAND "run mmcboot"
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
#define CONFIG_RAMDISK_BOOT "root=/dev/ram0 rw rootfstype=ext2" \
#define CONFIG_RAMDISK_BOOT "root=/dev/ram0 rw rootfstype=ext4" \
" ${console} ${meminfo}"
#define CONFIG_COMMON_BOOT "${console} ${meminfo} ${mtdparts}"
#define CONFIG_BOOTARGS "root=/dev/mtdblock8 ubi.mtd=8 ubi.mtd=3 ubi.mtd=6" \
" rootfstype=cramfs " CONFIG_COMMON_BOOT
#define CONFIG_BOOTARGS "root=/dev/mtdblock8 rootfstype=ext4 " \
CONFIG_COMMON_BOOT
#define CONFIG_UPDATEB "updateb=onenand erase 0x0 0x100000;" \
" onenand write 0x32008000 0x0 0x100000\0"
#define CONFIG_UBI_MTD " ubi.mtd=${ubiblock} ubi.mtd=3 ubi.mtd=6"
#define CONFIG_UBIFS_OPTION "rootflags=bulk_read,no_chk_data_crc"
#define CONFIG_MISC_COMMON
#define CONFIG_MISC_INIT_R
@ -130,42 +156,44 @@
"onenand erase 0x01560000 0x1eaa0000;" \
"onenand write 0x32000000 0x1260000 0x8C0000\0" \
"bootk=" \
"onenand read 0x30007FC0 0xc00000 0x600000;" \
"run loaduimage;" \
"bootm 0x30007FC0\0" \
"flashboot=" \
"set bootargs root=/dev/mtdblock${bootblock} " \
"rootfstype=${rootfstype}" CONFIG_UBI_MTD " ${opts} " \
"rootfstype=${rootfstype} ${opts} " \
"${lcdinfo} " CONFIG_COMMON_BOOT "; run bootk\0" \
"ubifsboot=" \
"set bootargs root=ubi0!rootfs rootfstype=ubifs " \
CONFIG_UBIFS_OPTION CONFIG_UBI_MTD " ${opts} ${lcdinfo} " \
"${opts} ${lcdinfo} " \
CONFIG_COMMON_BOOT "; run bootk\0" \
"tftpboot=" \
"set bootargs root=ubi0!rootfs rootfstype=ubifs " \
CONFIG_UBIFS_OPTION CONFIG_UBI_MTD " ${opts} ${lcdinfo} " \
CONFIG_COMMON_BOOT "; tftp 0x30007FC0 uImage; " \
"bootm 0x30007FC0\0" \
"${opts} ${lcdinfo} " CONFIG_COMMON_BOOT \
"; tftp 0x30007FC0 uImage; bootm 0x30007FC0\0" \
"ramboot=" \
"set bootargs " CONFIG_RAMDISK_BOOT \
" initrd=0x33000000,8M ramdisk=8192\0" \
"initrd=0x33000000,8M ramdisk=8192\0" \
"mmcboot=" \
"set bootargs root=${mmcblk} rootfstype=${rootfstype}" \
CONFIG_UBI_MTD " ${opts} ${lcdinfo} " \
"set bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
"rootfstype=${rootfstype} ${opts} ${lcdinfo} " \
CONFIG_COMMON_BOOT "; run bootk\0" \
"boottrace=setenv opts initcall_debug; run bootcmd\0" \
"bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \
"verify=n\0" \
"rootfstype=cramfs\0" \
"rootfstype=ext4\0" \
"console=" CONFIG_DEFAULT_CONSOLE \
"mtdparts=" MTDPARTS_DEFAULT \
"meminfo=mem=80M mem=256M@0x40000000 mem=128M@0x50000000\0" \
"mmcblk=/dev/mmcblk1p1\0" \
"loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x30007FC0 uImage\0" \
"mmcdev=0\0" \
"mmcbootpart=2\0" \
"mmcrootpart=5\0" \
"partitions=" PARTS_DEFAULT \
"bootblock=9\0" \
"ubiblock=8\0" \
"ubi=enabled\0" \
"opts=always_resume=1"
"opts=always_resume=1\0" \
"dfu_alt_info=" CONFIG_DFU_ALT "\0"
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT "Goni # "
@ -202,6 +230,18 @@
#define CONFIG_DOS_PARTITION 1
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_EXT4_WRITE
/* write support for filesystems */
#define CONFIG_FAT_WRITE
#define CONFIG_EXT4_WRITE
/* GPT */
#define CONFIG_EFI_PARTITION
#define CONFIG_PARTITION_UUIDS
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
#define CONFIG_SYS_CACHELINE_SIZE 64
@ -226,5 +266,8 @@
#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_S3C_UDC_OTG
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_USB_GADGET_MASS_STORAGE
#endif /* __CONFIG_H */

2
include/configs/tam3517-common.h
View File

@ -185,6 +185,7 @@
/* Configure the PISMO */
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define CONFIG_NAND
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_ENV_IS_IN_NAND
#define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */
@ -249,6 +250,7 @@
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
/* NAND boot config */
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64

2
include/configs/tao3530.h
View File

@ -137,10 +137,10 @@
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access nand at */
/* CS0 */
#define GPMC_NAND_ECC_LP_x16_LAYOUT
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
/* Environment information */
#define CONFIG_BOOTDELAY 3

26
include/configs/tegra-common-ums.h 100644
View File

@ -0,0 +1,26 @@
/*
* (C) Copyright 2014
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef _TEGRA_COMMON_UMS_H_
#define _TEGRA_COMMON_UMS_H
#ifndef CONFIG_SPL_BUILD
/* USB gadget, and mass storage protocol */
#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_CI_UDC
#define CONFIG_CI_UDC_HAS_HOSTPC
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_G_DNL_VENDOR_NUM 0x0955
#define CONFIG_G_DNL_PRODUCT_NUM 0x701A
#define CONFIG_G_DNL_MANUFACTURER "NVIDIA"
#define CONFIG_USBDOWNLOAD_GADGET
#define CONFIG_USB_GADGET_MASS_STORAGE
#define CONFIG_CMD_USB_MASS_STORAGE
#endif
#endif /* _TEGRA_COMMON_UMS_H */

9
include/configs/ti_am335x_common.h
View File

@ -75,6 +75,15 @@
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
/*
* When building U-Boot such that there is no previous loader
* we need to call board_early_init_f. This is taken care of in
* s_init when we have SPL used.
*/
#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && !defined(CONFIG_SPL)
#define CONFIG_BOARD_EARLY_INIT_F
#endif
#ifdef CONFIG_NAND
#define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */
#endif

3
include/configs/ti_armv7_common.h
View File

@ -196,7 +196,8 @@
* under common/spl/. Given our generally common memory map, we set a
* number of related defaults and sizes here.
*/
#ifndef CONFIG_NOR_BOOT
#if !defined(CONFIG_NOR_BOOT) && \
!(defined(CONFIG_QSPI_BOOT) && defined(CONFIG_AM43XX))
#define CONFIG_SPL
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_OS_BOOT

1
include/configs/tseries.h
View File

@ -157,7 +157,6 @@
/* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */
#define CONFIG_NAND_OMAP_ELM
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
#define CONFIG_SYS_NAND_PAGE_SIZE 2048

2
include/configs/venice2.h
View File

@ -63,6 +63,7 @@
/* USB Host support */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_USB
@ -74,6 +75,7 @@
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
#include "tegra-common-ums.h"
#include "tegra-common-post.h"
#endif /* __CONFIG_H */

2
include/configs/woodburn_common.h
View File

@ -55,7 +55,7 @@
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_FSL
#define CONFIG_PMIC_FSL_MC13892
#define CONFIG_POWER_FSL_MC13892
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
#define CONFIG_RTC_MC13XXX

5
include/dwmmc.h
View File

@ -123,6 +123,9 @@
#define DWMCI_BMOD_IDMAC_FB (1 << 1)
#define DWMCI_BMOD_IDMAC_EN (1 << 7)
/* UHS register */
#define DWMCI_DDR_MODE (1 << 16)
/* quirks */
#define DWMCI_QUIRK_DISABLE_SMU (1 << 0)
@ -134,7 +137,9 @@ struct dwmci_host {
unsigned int version;
unsigned int clock;
unsigned int bus_hz;
unsigned int div;
int dev_index;
int dev_id;
int buswidth;
u32 clksel_val;
u32 fifoth_val;

4
include/fdtdec.h
View File

@ -81,7 +81,7 @@ enum fdt_compat_id {
COMPAT_SAMSUNG_EXYNOS_FIMD, /* Exynos Display controller */
COMPAT_SAMSUNG_EXYNOS_MIPI_DSI, /* Exynos mipi dsi */
COMPAT_SAMSUNG_EXYNOS5_DP, /* Exynos Display port controller */
COMPAT_SAMSUNG_EXYNOS5_DWMMC, /* Exynos5 DWMMC controller */
COMPAT_SAMSUNG_EXYNOS_DWMMC, /* Exynos DWMMC controller */
COMPAT_SAMSUNG_EXYNOS_MMC, /* Exynos MMC controller */
COMPAT_SAMSUNG_EXYNOS_SERIAL, /* Exynos UART */
COMPAT_MAXIM_MAX77686_PMIC, /* MAX77686 PMIC */
@ -92,6 +92,8 @@ enum fdt_compat_id {
COMPAT_SAMSUNG_EXYNOS5_I2C, /* Exynos5 High Speed I2C Controller */
COMPAT_SANDBOX_HOST_EMULATION, /* Sandbox emulation of a function */
COMPAT_SANDBOX_LCD_SDL, /* Sandbox LCD emulation with SDL */
COMPAT_TI_TPS65090, /* Texas Instrument TPS65090 */
COMPAT_NXP_PTN3460, /* NXP PTN3460 DP/LVDS bridge */
COMPAT_COUNT,
};

2
include/initcall.h
View File

@ -6,4 +6,4 @@
typedef int (*init_fnc_t)(void);
int initcall_run_list(init_fnc_t init_sequence[]);
int initcall_run_list(const init_fnc_t init_sequence[]);

19
include/linux/mtd/nand.h
View File

@ -719,4 +719,23 @@ static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
}
#endif
/**
* Check if the opcode's address should be sent only on the lower 8 bits
* @command: opcode to check
*/
static inline int nand_opcode_8bits(unsigned int command)
{
switch (command) {
case NAND_CMD_READID:
case NAND_CMD_PARAM:
case NAND_CMD_GET_FEATURES:
case NAND_CMD_SET_FEATURES:
return 1;
default:
break;
}
return 0;
}
#endif /* __LINUX_MTD_NAND_H */

11
include/linux/mtd/omap_elm.h
View File

@ -24,6 +24,9 @@
#define ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK (0x100)
#define ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK (0x1F)
#define ELM_MAX_CHANNELS 8
#define ELM_MAX_ERROR_COUNT 16
#ifndef __ASSEMBLY__
enum bch_level {
@ -43,7 +46,7 @@ struct syndrome {
struct location {
u32 location_status; /* 0x800 */
u8 res1[124]; /* 0x804 */
u32 error_location_x[16]; /* 0x880.... */
u32 error_location_x[ELM_MAX_ERROR_COUNT]; /* 0x880, 0x980, .. */
u8 res2[64]; /* 0x8c0 */
};
@ -63,12 +66,12 @@ struct elm {
u8 res2[92]; /* 0x024 */
u32 page_ctrl; /* 0x080 */
u8 res3[892]; /* 0x084 */
struct syndrome syndrome_fragments[8]; /* 0x400 */
struct syndrome syndrome_fragments[ELM_MAX_CHANNELS]; /* 0x400,0x420 */
u8 res4[512]; /* 0x600 */
struct location error_location[8]; /* 0x800 */
struct location error_location[ELM_MAX_CHANNELS]; /* 0x800,0x900 ... */
};
int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count,
int elm_check_error(u8 *syndrome, enum bch_level bch_type, u32 *error_count,
u32 *error_locations);
int elm_config(enum bch_level level);
void elm_reset(void);

11
include/linux/mtd/omap_gpmc.h
View File

@ -11,6 +11,7 @@
#define GPMC_BUF_EMPTY 0
#define GPMC_BUF_FULL 1
#define GPMC_MAX_SECTORS 8
enum omap_ecc {
/* 1-bit ECC calculation by Software, Error detection by Software */
@ -26,6 +27,8 @@ enum omap_ecc {
OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
/* 8-bit ECC calculation by GPMC, Error detection by ELM */
OMAP_ECC_BCH8_CODE_HW,
/* 16-bit ECC calculation by GPMC, Error detection by ELM */
OMAP_ECC_BCH16_CODE_HW,
};
struct gpmc_cs {
@ -46,6 +49,10 @@ struct bch_res_0_3 {
u32 bch_result_x[4];
};
struct bch_res_4_6 {
u32 bch_result_x[3];
};
struct gpmc {
u8 res1[0x10];
u32 sysconfig; /* 0x10 */
@ -75,7 +82,9 @@ struct gpmc {
u8 res7[12]; /* 0x224 */
u32 testmomde_ctrl; /* 0x230 */
u8 res8[12]; /* 0x234 */
struct bch_res_0_3 bch_result_0_3[2]; /* 0x240 */
struct bch_res_0_3 bch_result_0_3[GPMC_MAX_SECTORS]; /* 0x240,0x250, */
u8 res9[16 * 4]; /* 0x2C0 - 0x2FF */
struct bch_res_4_6 bch_result_4_6[GPMC_MAX_SECTORS]; /* 0x300,0x310, */
};
/* Used for board specific gpmc initialization */

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