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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

utp
Tom Rini 2012-09-25 12:23:55 -07:00
parent ee1f4caaa2 d69dba367a
commit 5675b50916
97 changed files with 2678 additions and 2995 deletions
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6
Makefile
View File

@ -438,6 +438,11 @@ $(obj)u-boot.kwb: $(obj)u-boot.bin
$(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
$(obj)u-boot.pbl: $(obj)u-boot.bin
$(obj)tools/mkimage -n $(CONFIG_PBLRCW_CONFIG) \
-R $(CONFIG_PBLPBI_CONFIG) -T pblimage \
-d $< $@
$(obj)u-boot.sha1: $(obj)u-boot.bin
$(obj)tools/ubsha1 $(obj)u-boot.bin
@ -808,6 +813,7 @@ clobber: tidy
$(obj)cscope.* $(obj)*.*~
@rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL-y)
@rm -f $(obj)u-boot.kwb
@rm -f $(obj)u-boot.pbl
@rm -f $(obj)u-boot.imx
@rm -f $(obj)u-boot.ubl
@rm -f $(obj)u-boot.ais

37
README
View File

@ -383,6 +383,31 @@ The following options need to be configured:
symbol should be set to the TLB1 entry to be used for this
purpose.
CONFIG_SYS_FSL_ERRATUM_A004510
Enables a workaround for erratum A004510. If set,
then CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV and
CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY must be set.
CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 (optional)
Defines one or two SoC revisions (low 8 bits of SVR)
for which the A004510 workaround should be applied.
The rest of SVR is either not relevant to the decision
of whether the erratum is present (e.g. p2040 versus
p2041) or is implied by the build target, which controls
whether CONFIG_SYS_FSL_ERRATUM_A004510 is set.
See Freescale App Note 4493 for more information about
this erratum.
CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
This is the value to write into CCSR offset 0x18600
according to the A004510 workaround.
- Generic CPU options:
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
@ -3100,12 +3125,12 @@ to save the current settings.
These two #defines specify the address and size of the
environment area within the remote memory space. The
local device can get the environment from remote memory
space by SRIO or other links.
space by SRIO or PCIE links.
BE CAREFUL! For some special cases, the local device can not use
"saveenv" command. For example, the local device will get the
environment stored in a remote NOR flash by SRIO link, but it can
not erase, write this NOR flash by SRIO interface.
environment stored in a remote NOR flash by SRIO or PCIE link,
but it can not erase, write this NOR flash by SRIO or PCIE interface.
- CONFIG_ENV_IS_IN_NAND:
@ -3553,9 +3578,9 @@ within that device.
- CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
Specifies that QE/FMAN firmware is located in the remote (master)
memory space. CONFIG_SYS_FMAN_FW_ADDR is a virtual address which
can be mapped from slave TLB->slave LAW->slave SRIO outbound window
->master inbound window->master LAW->the ucode address in master's
NOR flash.
can be mapped from slave TLB->slave LAW->slave SRIO or PCIE outbound
window->master inbound window->master LAW->the ucode address in
master's memory space.
Building the Software:
======================

10
arch/powerpc/cpu/mpc85xx/Makefile
View File

@ -55,8 +55,6 @@ COBJS-$(CONFIG_P1011) += ddr-gen3.o
COBJS-$(CONFIG_P1012) += ddr-gen3.o
COBJS-$(CONFIG_P1013) += ddr-gen3.o
COBJS-$(CONFIG_P1014) += ddr-gen3.o
COBJS-$(CONFIG_P1015) += ddr-gen3.o
COBJS-$(CONFIG_P1016) += ddr-gen3.o
COBJS-$(CONFIG_P1020) += ddr-gen3.o
COBJS-$(CONFIG_P1021) += ddr-gen3.o
COBJS-$(CONFIG_P1022) += ddr-gen3.o
@ -64,10 +62,8 @@ COBJS-$(CONFIG_P1024) += ddr-gen3.o
COBJS-$(CONFIG_P1025) += ddr-gen3.o
COBJS-$(CONFIG_P2010) += ddr-gen3.o
COBJS-$(CONFIG_P2020) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P2040) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P2041) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P3060) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o
COBJS-$(CONFIG_BSC9131) += ddr-gen3.o
@ -80,10 +76,8 @@ COBJS-$(CONFIG_PCI) += pci.o
COBJS-$(CONFIG_SYS_DPAA_QBMAN) += portals.o
# various SoC specific assignments
COBJS-$(CONFIG_PPC_P2040) += p2041_ids.o
COBJS-$(CONFIG_PPC_P2041) += p2041_ids.o
COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o
COBJS-$(CONFIG_PPC_P3060) += p3060_ids.o
COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o
@ -103,8 +97,6 @@ COBJS-$(CONFIG_P1011) += p1021_serdes.o
COBJS-$(CONFIG_P1012) += p1021_serdes.o
COBJS-$(CONFIG_P1013) += p1022_serdes.o
COBJS-$(CONFIG_P1014) += p1010_serdes.o
COBJS-$(CONFIG_P1015) += p1021_serdes.o
COBJS-$(CONFIG_P1016) += p1021_serdes.o
COBJS-$(CONFIG_P1017) += p1023_serdes.o
COBJS-$(CONFIG_P1020) += p1021_serdes.o
COBJS-$(CONFIG_P1021) += p1021_serdes.o
@ -114,10 +106,8 @@ COBJS-$(CONFIG_P1024) += p1021_serdes.o
COBJS-$(CONFIG_P1025) += p1021_serdes.o
COBJS-$(CONFIG_P2010) += p2020_serdes.o
COBJS-$(CONFIG_P2020) += p2020_serdes.o
COBJS-$(CONFIG_PPC_P2040) += p2041_serdes.o
COBJS-$(CONFIG_PPC_P2041) += p2041_serdes.o
COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o
COBJS-$(CONFIG_PPC_P3060) += p3060_serdes.o
COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o

9
arch/powerpc/cpu/mpc85xx/cmd_errata.c
View File

@ -27,6 +27,9 @@
static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
extern int enable_cpu_a011_workaround;
#endif
__maybe_unused u32 svr = get_svr();
#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
@ -56,8 +59,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
/*
* NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
* also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
* The SVR has been checked by cpu_init_r().
*/
if (SVR_SOC_VER(svr) != SVR_P4080 || SVR_MAJ(svr) < 3)
if (enable_cpu_a011_workaround)
puts("Work-around for Erratum CPU-A011 enabled\n");
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999)
@ -119,6 +123,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
puts("Work-around for Erratum NMG ETSEC129 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
puts("Work-around for Erratum A004510 enabled\n");
#endif
return 0;
}

15
arch/powerpc/cpu/mpc85xx/cpu.c
View File

@ -117,6 +117,9 @@ int checkcpu (void)
case PVR_VER_E5500:
puts("E5500");
break;
case PVR_VER_E6500:
puts("E6500");
break;
default:
puts("Unknown");
break;
@ -427,10 +430,20 @@ static void dump_spd_ddr_reg(void)
case 0:
ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
break;
#ifdef CONFIG_SYS_MPC85xx_DDR2_ADDR
#if defined(CONFIG_SYS_MPC85xx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
case 1:
ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
break;
#endif
#if defined(CONFIG_SYS_MPC85xx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
case 2:
ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR3_ADDR;
break;
#endif
#if defined(CONFIG_SYS_MPC85xx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
case 3:
ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR4_ADDR;
break;
#endif
default:
printf("%s unexpected controller number = %u\n",

52
arch/powerpc/cpu/mpc85xx/cpu_init.c
View File

@ -38,6 +38,7 @@
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_srio.h>
#include <hwconfig.h>
#include <linux/compiler.h>
#include "mp.h"
#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
@ -311,11 +312,41 @@ int cpu_init_r(void)
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
/*
* CPU22 and NMG_CPU_A011 share the same workaround.
* CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
* NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
* also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
* also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
* fixed in 2.0. NMG_CPU_A011 is activated by default and can
* be disabled by hwconfig with syntax:
*
* fsl_cpu_a011:disable
*/
if (SVR_SOC_VER(svr) != SVR_P4080 || SVR_MAJ(svr) < 3) {
extern int enable_cpu_a011_workaround;
#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
#else
char buffer[HWCONFIG_BUFFER_SIZE];
char *buf = NULL;
int n, res;
n = getenv_f("hwconfig", buffer, sizeof(buffer));
if (n > 0)
buf = buffer;
res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
if (res > 0)
enable_cpu_a011_workaround = 0;
else {
if (n >= HWCONFIG_BUFFER_SIZE) {
printf("fsl_cpu_a011 was not found. hwconfig variable "
"may be too long\n");
}
enable_cpu_a011_workaround =
(SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
(SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
}
#endif
if (enable_cpu_a011_workaround) {
flush_dcache();
mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
sync();
@ -447,11 +478,18 @@ skip_l2:
#ifdef CONFIG_SYS_SRIO
srio_init();
#ifdef CONFIG_SRIOBOOT_MASTER
srio_boot_master();
#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF
srio_boot_master_release_slave();
#endif
#ifdef CONFIG_FSL_CORENET
char *s = getenv("bootmaster");
if (s) {
if (!strcmp(s, "SRIO1")) {
srio_boot_master(1);
srio_boot_master_release_slave(1);
}
if (!strcmp(s, "SRIO2")) {
srio_boot_master(2);
srio_boot_master_release_slave(2);
}
}
#endif
#endif

26
arch/powerpc/cpu/mpc85xx/ddr-gen3.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2008-2011 Freescale Semiconductor, Inc.
* Copyright 2008-2012 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@ -32,9 +32,21 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
case 0:
ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
break;
#if defined(CONFIG_SYS_MPC85xx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
case 1:
ddr = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
break;
#endif
#if defined(CONFIG_SYS_MPC85xx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
case 2:
ddr = (void *)CONFIG_SYS_MPC85xx_DDR3_ADDR;
break;
#endif
#if defined(CONFIG_SYS_MPC85xx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
case 3:
ddr = (void *)CONFIG_SYS_MPC85xx_DDR4_ADDR;
break;
#endif
default:
printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
return;
@ -43,6 +55,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
out_be32(&ddr->eor, regs->ddr_eor);
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
debug("Workaround for ERRATUM_DDR111_DDR134\n");
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
cs_sa = (regs->cs[i].bnds >> 16) & 0xfff;
cs_ea = regs->cs[i].bnds & 0xfff;
@ -115,8 +128,12 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
out_be32(&ddr->err_disable, regs->err_disable);
out_be32(&ddr->err_int_en, regs->err_int_en);
for (i = 0; i < 32; i++)
out_be32(&ddr->debug[i], regs->debug[i]);
for (i = 0; i < 32; i++) {
if (regs->debug[i]) {
debug("Write to debug_%d as %08x\n", i+1, regs->debug[i]);
out_be32(&ddr->debug[i], regs->debug[i]);
}
}
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
out_be32(&ddr->debug[12], 0x00000015);
@ -128,6 +145,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
debug("Workaround for ERRATUM_DDR_A003\n");
if (regs->ddr_sdram_rcw_2 & 0x00f00000) {
out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff);
out_be32(&ddr->debug[2], 0x00000400);
@ -209,6 +227,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
* This erratum does not affect DDR3 mode, only for DDR2 mode.
*/
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
debug("Workaround for ERRATUM_DDR_115\n");
if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
&& in_be32(&ddr->sdram_cfg) & 0x80000) {
/* set DEBUG_1[31] */
@ -216,6 +235,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
}
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
debug("Workaround for ERRATUM_DDR111_DDR134\n");
/*
* This is the combined workaround for DDR111 and DDR134
* following the published errata for MPC8572

7
arch/powerpc/cpu/mpc85xx/fdt.c
View File

@ -57,8 +57,9 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
if (reg) {
u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr;
val = cpu_to_fdt32(val);
u32 phys_cpu_id = thread_to_core(*reg);
u64 val = phys_cpu_id * SIZE_BOOT_ENTRY + spin_tbl_addr;
val = cpu_to_fdt64(val);
if (*reg == id) {
fdt_setprop_string(blob, off, "status",
"okay");
@ -534,7 +535,7 @@ void fdt_fixup_fman_firmware(void *blob)
#define fdt_fixup_fman_firmware(x)
#endif
#if defined(CONFIG_PPC_P4080) || defined(CONFIG_PPC_P3060)
#if defined(CONFIG_PPC_P4080)
static void fdt_fixup_usb(void *fdt)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);

8
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
View File

@ -46,8 +46,6 @@
static u32 serdes_prtcl_map;
#define HWCONFIG_BUFFER_SIZE 128
#ifdef DEBUG
static const char *serdes_prtcl_str[] = {
[NONE] = "NA",
@ -68,6 +66,7 @@ static const char *serdes_prtcl_str[] = {
[SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2",
[SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3",
[SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4",
[SGMII_FM2_DTSEC5] = "SGMII_FM2_DTSEC5",
[XAUI_FM1] = "XAUI_FM1",
[XAUI_FM2] = "XAUI_FM2",
[AURORA] = "DEBUG",
@ -658,6 +657,7 @@ void fsl_serdes_init(void)
case SGMII_FM2_DTSEC2:
case SGMII_FM2_DTSEC3:
case SGMII_FM2_DTSEC4:
case SGMII_FM2_DTSEC5:
case XAUI_FM1:
case XAUI_FM2:
case SRIO1:
@ -717,6 +717,10 @@ void fsl_serdes_init(void)
serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
FSL_CORENET_DEVDISR2_DTSEC2_4;
break;
case SGMII_FM2_DTSEC5:
serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
FSL_CORENET_DEVDISR2_DTSEC2_5;
break;
case XAUI_FM1:
serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
FSL_CORENET_DEVDISR2_10GEC1;

117
arch/powerpc/cpu/mpc85xx/p3060_ids.c
View File

@ -1,117 +0,0 @@
/*
* Copyright 2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#ifdef CONFIG_SYS_DPAA_QBMAN
struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
/* dqrr liodn, frame data liodn, liodn off, sdest */
SET_QP_INFO( 1, 2, 1, 0),
SET_QP_INFO( 3, 4, 2, 1),
SET_QP_INFO( 5, 6, 3, 2),
SET_QP_INFO( 7, 8, 4, 3),
SET_QP_INFO( 9, 10, 5, 4),
SET_QP_INFO(11, 12, 6, 5),
SET_QP_INFO(13, 14, 7, 6),
SET_QP_INFO(15, 16, 8, 7),
SET_QP_INFO(17, 18, 9, 0), /* for now sdest to 0 */
SET_QP_INFO(19, 20, 10, 0), /* for now sdest to 0 */
};
#endif
struct srio_liodn_id_table srio_liodn_tbl[] = {
SET_SRIO_LIODN_1(1, 198),
SET_SRIO_LIODN_1(2, 199),
};
int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
struct liodn_id_table liodn_tbl[] = {
SET_USB_LIODN(1, "fsl-usb2-mph", 127),
SET_USB_LIODN(2, "fsl-usb2-dr", 157),
SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193),
SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194),
SET_DMA_LIODN(1, 196),
SET_DMA_LIODN(2, 197),
SET_GUTS_LIODN("fsl,srio-rmu", 200, rmuliodnr, 0xd3000),
#ifdef CONFIG_SYS_DPAA_QBMAN
SET_QMAN_LIODN(31),
SET_BMAN_LIODN(32),
#endif
SET_PME_LIODN(128),
};
int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
#ifdef CONFIG_SYS_DPAA_FMAN
struct liodn_id_table fman1_liodn_tbl[] = {
SET_FMAN_RX_1G_LIODN(1, 0, 11),
SET_FMAN_RX_1G_LIODN(1, 1, 12),
SET_FMAN_RX_1G_LIODN(1, 2, 13),
SET_FMAN_RX_1G_LIODN(1, 3, 14),
};
int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
#if (CONFIG_SYS_NUM_FMAN == 2)
struct liodn_id_table fman2_liodn_tbl[] = {
SET_FMAN_RX_1G_LIODN(2, 0, 16),
SET_FMAN_RX_1G_LIODN(2, 1, 17),
SET_FMAN_RX_1G_LIODN(2, 2, 18),
SET_FMAN_RX_1G_LIODN(2, 3, 19),
};
int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl);
#endif
#endif
struct liodn_id_table sec_liodn_tbl[] = {
SET_SEC_JR_LIODN_ENTRY(0, 146, 154),
SET_SEC_JR_LIODN_ENTRY(1, 147, 155),
SET_SEC_JR_LIODN_ENTRY(2, 178, 186),
SET_SEC_JR_LIODN_ENTRY(3, 179, 187),
SET_SEC_RTIC_LIODN_ENTRY(a, 144),
SET_SEC_RTIC_LIODN_ENTRY(b, 145),
SET_SEC_RTIC_LIODN_ENTRY(c, 176),
SET_SEC_RTIC_LIODN_ENTRY(d, 177),
SET_SEC_DECO_LIODN_ENTRY(0, 129, 161),
SET_SEC_DECO_LIODN_ENTRY(1, 130, 162),
SET_SEC_DECO_LIODN_ENTRY(2, 131, 163),
SET_SEC_DECO_LIODN_ENTRY(3, 132, 164),
SET_SEC_DECO_LIODN_ENTRY(4, 133, 165),
};
int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
struct liodn_id_table liodn_bases[] = {
[FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(96, 106),
#ifdef CONFIG_SYS_DPAA_FMAN
[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32),
#if (CONFIG_SYS_NUM_FMAN == 2)
[FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(64),
#endif
#endif
#ifdef CONFIG_SYS_DPAA_PME
[FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(116, 133),
#endif
};

118
arch/powerpc/cpu/mpc85xx/p3060_serdes.c
View File

@ -1,118 +0,0 @@
/*
* Copyright 2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/fsl_serdes.h>
#include <asm/processor.h>
#include <asm/io.h>
#include "fsl_corenet_serdes.h"
static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
[0x03] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC1,
SGMII_FM1_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM1_DTSEC2,
NONE, NONE, AURORA, AURORA},
[0x06] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, SGMII_FM2_DTSEC3,
SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4,
SGMII_FM2_DTSEC1, SGMII_FM1_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM1_DTSEC2, NONE, NONE, AURORA, AURORA},
[0x16] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
AURORA, AURORA, SGMII_FM2_DTSEC1, SGMII_FM1_DTSEC1,
SGMII_FM2_DTSEC2, SGMII_FM1_DTSEC2, SGMII_FM2_DTSEC3,
SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4},
[0x19] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
AURORA, AURORA, PCIE2, PCIE2, PCIE2, PCIE2, SGMII_FM2_DTSEC3,
SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4},
[0x1c] = {NONE, NONE, SRIO1, SRIO2, NONE, NONE, NONE, NONE,
AURORA, AURORA, SGMII_FM2_DTSEC1, SGMII_FM1_DTSEC1,
SGMII_FM2_DTSEC2, SGMII_FM1_DTSEC2, SGMII_FM2_DTSEC3,
SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4},
};
enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
{
if (!serdes_lane_enabled(lane))
return NONE;
return serdes_cfg_tbl[cfg][lane];
}
int is_serdes_prtcl_valid(u32 prtcl)
{
int i;
if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
return 0;
for (i = 0; i < SRDS_MAX_LANES; i++) {
if (serdes_cfg_tbl[prtcl][i] != NONE)
return 1;
}
return 0;
}
void soc_serdes_init(void)
{
/*
* On the P3060 the devdisr2 register does not correctly reflect
* the state of the MACs based on the RCW fields. So disable the MACs
* based on the srds_prtcl and ec1, ec2, ec3 fields
*/
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr2 = in_be32(&gur->devdisr2);
u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
/* NOTE: Leave FM1-1,FM1-2 alone for MDIO access */
if (!is_serdes_configured(SGMII_FM1_DTSEC3))
devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC1_3;
if (!is_serdes_configured(SGMII_FM1_DTSEC4))
devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC1_4;
if (!is_serdes_configured(SGMII_FM2_DTSEC1))
devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_1;
if (!is_serdes_configured(SGMII_FM2_DTSEC2))
devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_2;
if (!is_serdes_configured(SGMII_FM2_DTSEC3))
devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_3;
if (!is_serdes_configured(SGMII_FM2_DTSEC4))
devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_4;
if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2) {
devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC1_2;
}
if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1) {
devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC2_1;
}
out_be32(&gur->devdisr2, devdisr2);
}

87
arch/powerpc/cpu/mpc85xx/release.S
View File

@ -1,5 +1,5 @@
/*
* Copyright 2008-2011 Freescale Semiconductor, Inc.
* Copyright 2008-2012 Freescale Semiconductor, Inc.
* Kumar Gala <kumar.gala@freescale.com>
*
* See file CREDITS for list of people who contributed to this
@ -74,6 +74,33 @@ __secondary_start_page:
mtspr 977,r3
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
mfspr r3,SPRN_SVR
rlwinm r3,r3,0,0xff
li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
cmpw r3,r4
beq 1f
#ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
cmpw r3,r4
beq 1f
#endif
/* Not a supported revision affected by erratum */
b 2f
1: /* Erratum says set bits 55:60 to 001001 */
msync
isync
mfspr r3,976
li r4,0x48
rlwimi r3,r4,0,0x1f8
mtspr 976,r3
isync
2:
#endif
/* Enable branch prediction */
lis r3,BUCSR_ENABLE@h
ori r3,r3,BUCSR_ENABLE@l
@ -128,7 +155,27 @@ __secondary_start_page:
/* r10 has the base address for the entry */
mfspr r0,SPRN_PIR
#ifdef CONFIG_E500MC
#if defined(CONFIG_E6500)
/*
* PIR definition for E6500
* 0-17 Reserved (logic 0s)
* 8-19 CHIP_ID, 2’b00 - SoC 1
* all others - reserved
* 20-24 CLUSTER_ID 5’b00000 - CCM 1
* all others - reserved
* 25-26 CORE_CLUSTER_ID 2’b00 - cluster 1
* 2’b01 - cluster 2
* 2’b10 - cluster 3
* 2’b11 - cluster 4
* 27-28 CORE_ID 2’b00 - core 0
* 2’b01 - core 1
* 2’b10 - core 2
* 2’b11 - core 3
* 29-31 THREAD_ID 3’b000 - thread 0
* 3’b001 - thread 1
*/
rlwinm r4,r0,29,25,31
#elif defined(CONFIG_E500MC)
rlwinm r4,r0,27,27,31
#else
mr r4,r0
@ -143,6 +190,25 @@ __secondary_start_page:
mtspr L1CSR2,r8
#endif
#ifdef CONFIG_E6500
mfspr r0,SPRN_PIR
/*
* core 0 thread 0: pir reset value 0x00, new pir 0
* core 0 thread 1: pir reset value 0x01, new pir 1
* core 1 thread 0: pir reset value 0x08, new pir 2
* core 1 thread 1: pir reset value 0x09, new pir 3
* core 2 thread 0: pir reset value 0x10, new pir 4
* core 2 thread 1: pir reset value 0x11, new pir 5
* etc.
*
* Only thread 0 of each core will be running, updating PIR doesn't
* need to deal with the thread bits.
*/
rlwinm r4,r0,30,24,30
#endif
mtspr SPRN_PIR,r4 /* write to PIR register */
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
/*
@ -163,6 +229,12 @@ __secondary_start_page:
cmpw r3,r5
bge 2f
1:
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
lis r3,toreset(enable_cpu_a011_workaround)@ha
lwz r3,toreset(enable_cpu_a011_workaround)@l(r3)
cmpwi r3,0
beq 2f
#endif
mfspr r3,L1CSR2
oris r3,r3,(L1CSR2_DCWS)@h
mtspr L1CSR2,r3
@ -220,7 +292,7 @@ __secondary_start_page:
/* setup the entry */
li r3,0
li r8,1
stw r0,ENTRY_PIR(r10)
stw r4,ENTRY_PIR(r10)
stw r3,ENTRY_ADDR_UPPER(r10)
stw r8,ENTRY_ADDR_LOWER(r10)
stw r3,ENTRY_R3_UPPER(r10)
@ -346,6 +418,15 @@ __bootpg_addr:
__spin_table:
.space CONFIG_MAX_CPUS*ENTRY_SIZE
/*
* This variable is set by cpu_init_r() after parsing hwconfig
* to enable workaround for erratum NMG_CPU_A011.
*/
.align L1_CACHE_SHIFT
.global enable_cpu_a011_workaround
enable_cpu_a011_workaround:
.long 1
/* Fill in the empty space. The actual reset vector is
* the last word of the page */
__secondary_start_code_end:

3
arch/powerpc/cpu/mpc85xx/speed.c
View File

@ -186,8 +186,7 @@ void get_sys_info (sys_info_t * sysInfo)
#endif
#ifdef CONFIG_QE
#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
defined(CONFIG_P1021) || defined(CONFIG_P1025)
#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
sysInfo->freqQE = sysInfo->freqSystemBus;
#else
qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)

376
arch/powerpc/cpu/mpc85xx/start.S
View File

@ -86,6 +86,35 @@ _start_e500:
li r1,MSR_DE
mtmsr r1
#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
mfspr r3,SPRN_SVR
rlwinm r3,r3,0,0xff
li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
cmpw r3,r4
beq 1f
#ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
cmpw r3,r4
beq 1f
#endif
/* Not a supported revision affected by erratum */
li r27,0
b 2f
1: li r27,1 /* Remember for later that we have the erratum */
/* Erratum says set bits 55:60 to 001001 */
msync
isync
mfspr r3,976
li r4,0x48
rlwimi r3,r4,0,0x1f8
mtspr 976,r3
isync
2:
#endif
#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC)
/* ISBC uses L2 as stack.
* Disable L2 cache here so that u-boot can enable it later
@ -406,12 +435,11 @@ l2_disabled:
* Search for the TLB that covers the code we're executing, and shrink it
* so that it covers only this 4K page. That will ensure that any other
* TLB we create won't interfere with it. We assume that the TLB exists,
* which is why we don't check the Valid bit of MAS1.
* which is why we don't check the Valid bit of MAS1. We also assume
* it is in TLB1.
*
* This is necessary, for example, when booting from the on-chip ROM,
* which (oddly) creates a single 4GB TLB that covers CCSR and DDR.
* If we don't shrink this TLB now, then we'll accidentally delete it
* in "purge_old_ccsr_tlb" below.
*/
bl nexti /* Find our address */
nexti: mflr r1 /* R1 = our PC */
@ -421,11 +449,15 @@ nexti: mflr r1 /* R1 = our PC */
msync
tlbsx 0, r1 /* This must succeed */
mfspr r14, MAS0 /* Save ESEL for later */
rlwinm r14, r14, 16, 0xfff
/* Set the size of the TLB to 4KB */
mfspr r3, MAS1
li r2, 0xF00
andc r3, r3, r2 /* Clear the TSIZE bits */
ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l
oris r3, r3, MAS1_IPROT@h
mtspr MAS1, r3
/*
@ -440,6 +472,14 @@ nexti: mflr r1 /* R1 = our PC */
mfspr r2, MAS2
andc r2, r2, r3
or r2, r2, r1
#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
cmpwi r27,0
beq 1f
andi. r15, r2, MAS2_I|MAS2_G /* save the old I/G for later */
rlwinm r2, r2, 0, ~MAS2_I
ori r2, r2, MAS2_G
1:
#endif
mtspr MAS2, r2 /* Set the EPN to our PC base address */
mfspr r2, MAS3
@ -451,6 +491,39 @@ nexti: mflr r1 /* R1 = our PC */
msync
tlbwe
/*
* Clear out any other TLB entries that may exist, to avoid conflicts.
* Our TLB entry is in r14.
*/
li r0, TLBIVAX_ALL | TLBIVAX_TLB0
tlbivax 0, r0
tlbsync
mfspr r4, SPRN_TLB1CFG
rlwinm r4, r4, 0, TLBnCFG_NENTRY_MASK
li r3, 0
mtspr MAS1, r3
1: cmpw r3, r14
#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
cmpwi cr1, r3, CONFIG_SYS_PPC_E500_DEBUG_TLB
cror cr0*4+eq, cr0*4+eq, cr1*4+eq
#endif
rlwinm r5, r3, 16, MAS0_ESEL_MSK
addi r3, r3, 1
beq 2f /* skip the entry we're executing from */
oris r5, r5, MAS0_TLBSEL(1)@h
mtspr MAS0, r5
isync
tlbwe
isync
msync
2: cmpw r3, r4
blt 1b
/*
* Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default
* location is not where we want it. This typically happens on a 36-bit
@ -469,41 +542,15 @@ nexti: mflr r1 /* R1 = our PC */
#error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined."
#endif
purge_old_ccsr_tlb:
lis r8, CONFIG_SYS_CCSRBAR@h
ori r8, r8, CONFIG_SYS_CCSRBAR@l
lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h
ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l
/*
* In a multi-stage boot (e.g. NAND boot), a previous stage may have
* created a TLB for CCSR, which will interfere with our relocation
* code. Since we're going to create a new TLB for CCSR anyway,
* it should be safe to delete this old TLB here. We have to search
* for it, though.
*/
li r1, 0
mtspr MAS6, r1 /* Search the current address space and PID */
isync
msync
tlbsx 0, r8
mfspr r1, MAS1
andis. r2, r1, MAS1_VALID@h /* Check for the Valid bit */
beq 1f /* Skip if no TLB found */
rlwinm r1, r1, 0, 1, 31 /* Clear Valid bit */
mtspr MAS1, r1
isync
msync
tlbwe
1:
create_ccsr_new_tlb:
/*
* Create a TLB for the new location of CCSR. Register R8 is reserved
* for the virtual address of this TLB (CONFIG_SYS_CCSRBAR).
*/
lis r8, CONFIG_SYS_CCSRBAR@h
ori r8, r8, CONFIG_SYS_CCSRBAR@l
lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h
ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l
lis r0, FSL_BOOKE_MAS0(0, 0, 0)@h
ori r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l
lis r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
@ -719,6 +766,253 @@ delete_temp_tlbs:
tlbwe
#endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
#define DCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
#define LAW_SIZE_1M 0x13
#define DCSRBAR_LAWAR (LAW_EN | (0x1d << 20) | LAW_SIZE_1M)
cmpwi r27,0
beq 9f
/*
* Create a TLB entry for CCSR
*
* We're executing out of TLB1 entry in r14, and that's the only
* TLB entry that exists. To allocate some TLB entries for our
* own use, flip a bit high enough that we won't flip it again
* via incrementing.
*/
xori r8, r14, 32
lis r0, MAS0_TLBSEL(1)@h
rlwimi r0, r8, 16, MAS0_ESEL_MSK
lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@h
ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@l
lis r7, CONFIG_SYS_CCSRBAR@h
ori r7, r7, CONFIG_SYS_CCSRBAR@l
ori r2, r7, MAS2_I|MAS2_G
lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
lis r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
ori r4, r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
mtspr MAS0, r0
mtspr MAS1, r1
mtspr MAS2, r2
mtspr MAS3, r3
mtspr MAS7, r4
isync
tlbwe
isync
msync
/* Map DCSR temporarily to physical address zero */
li r0, 0
lis r3, DCSRBAR_LAWAR@h
ori r3, r3, DCSRBAR_LAWAR@l
stw r0, 0xc00(r7) /* LAWBARH0 */
stw r0, 0xc04(r7) /* LAWBARL0 */
sync
stw r3, 0xc08(r7) /* LAWAR0 */
/* Read back from LAWAR to ensure the update is complete. */
lwz r3, 0xc08(r7) /* LAWAR0 */
isync
/* Create a TLB entry for DCSR at zero */
addi r9, r8, 1
lis r0, MAS0_TLBSEL(1)@h
rlwimi r0, r9, 16, MAS0_ESEL_MSK
lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h
ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l
li r6, 0 /* DCSR effective address */
ori r2, r6, MAS2_I|MAS2_G
li r3, MAS3_SW|MAS3_SR
li r4, 0
mtspr MAS0, r0
mtspr MAS1, r1
mtspr MAS2, r2
mtspr MAS3, r3
mtspr MAS7, r4
isync
tlbwe
isync
msync
/* enable the timebase */
#define CTBENR 0xe2084
li r3, 1
addis r4, r7, CTBENR@ha
stw r3, CTBENR@l(r4)
lwz r3, CTBENR@l(r4)
twi 0,r3,0
isync
.macro erratum_set_ccsr offset value
addis r3, r7, \offset@ha
lis r4, \value@h
addi r3, r3, \offset@l
ori r4, r4, \value@l
bl erratum_set_value
.endm
.macro erratum_set_dcsr offset value
addis r3, r6, \offset@ha
lis r4, \value@h
addi r3, r3, \offset@l
ori r4, r4, \value@l
bl erratum_set_value
.endm
erratum_set_dcsr 0xb0e08 0xe0201800
erratum_set_dcsr 0xb0e18 0xe0201800
erratum_set_dcsr 0xb0e38 0xe0400000
erratum_set_dcsr 0xb0008 0x00900000
erratum_set_dcsr 0xb0e40 0xe00a0000
erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
erratum_set_ccsr 0x10f00 0x415e5000
erratum_set_ccsr 0x11f00 0x415e5000
/* Make temp mapping uncacheable again, if it was initially */
bl 2f
2: mflr r3
tlbsx 0, r3
mfspr r4, MAS2
rlwimi r4, r15, 0, MAS2_I
rlwimi r4, r15, 0, MAS2_G
mtspr MAS2, r4
isync
tlbwe
isync
msync
/* Clear the cache */
lis r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
ori r3,r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
sync
isync
mtspr SPRN_L1CSR1,r3
isync
2: sync
mfspr r4,SPRN_L1CSR1
and. r4,r4,r3
bne 2b
lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
sync
isync
mtspr SPRN_L1CSR1,r3
isync
2: sync
mfspr r4,SPRN_L1CSR1
and. r4,r4,r3
beq 2b
/* Remove temporary mappings */
lis r0, MAS0_TLBSEL(1)@h
rlwimi r0, r9, 16, MAS0_ESEL_MSK
li r3, 0
mtspr MAS0, r0
mtspr MAS1, r3
isync
tlbwe
isync
msync
li r3, 0
stw r3, 0xc08(r7) /* LAWAR0 */
lwz r3, 0xc08(r7)
isync
lis r0, MAS0_TLBSEL(1)@h
rlwimi r0, r8, 16, MAS0_ESEL_MSK
li r3, 0
mtspr MAS0, r0
mtspr MAS1, r3
isync
tlbwe
isync
msync
b 9f
/* r3 = addr, r4 = value, clobbers r5, r11, r12 */
erratum_set_value:
/* Lock two cache lines into I-Cache */
sync
mfspr r11, SPRN_L1CSR1
rlwinm r11, r11, 0, ~L1CSR1_ICUL
sync
isync
mtspr SPRN_L1CSR1, r11
isync
mflr r12
bl 5f
5: mflr r5
addi r5, r5, 2f - 5b
icbtls 0, 0, r5
addi r5, r5, 64
sync
mfspr r11, SPRN_L1CSR1
3: andi. r11, r11, L1CSR1_ICUL
bne 3b
icbtls 0, 0, r5
addi r5, r5, 64
sync
mfspr r11, SPRN_L1CSR1
3: andi. r11, r11, L1CSR1_ICUL
bne 3b
b 2f
.align 6
/* Inside a locked cacheline, wait a while, write, then wait a while */
2: sync
mfspr r5, SPRN_TBRL
addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */
4: mfspr r5, SPRN_TBRL
subf. r5, r5, r11
bgt 4b
stw r4, 0(r3)
mfspr r5, SPRN_TBRL
addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */
4: mfspr r5, SPRN_TBRL
subf. r5, r5, r11
bgt 4b
sync
/*
* Fill out the rest of this cache line and the next with nops,
* to ensure that nothing outside the locked area will be
* fetched due to a branch.
*/
.rept 19
nop
.endr
sync
mfspr r11, SPRN_L1CSR1
rlwinm r11, r11, 0, ~L1CSR1_ICUL
sync
isync
mtspr SPRN_L1CSR1, r11
isync
mtlr r12
blr
9:
#endif
create_init_ram_area:
lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
@ -855,18 +1149,12 @@ version_string:
.globl _start_cont
_start_cont:
/* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
lis r1,CONFIG_SYS_INIT_RAM_ADDR@h
ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
li r0,0
stwu r0,-4(r1)
stwu r0,-4(r1) /* Terminate call chain */
stwu r1,-8(r1) /* Save back chain and move SP */
lis r0,RESET_VECTOR@h /* Address of reset vector */
ori r0,r0,RESET_VECTOR@l
stwu r1,-8(r1) /* Save back chain and move SP */
stw r0,+12(r1) /* Save return addr (underflow vect) */
stw r0,0(r3) /* Terminate Back Chain */
stw r0,+4(r3) /* NULL return address. */
mr r1,r3 /* Transfer to SP(r1) */
GET_GOT
bl cpu_init_early_f

68
arch/powerpc/cpu/mpc8xxx/cpu.c
View File

@ -57,8 +57,6 @@ struct cpu_type cpu_type_list [] = {
CPU_TYPE_ENTRY(P1012, P1012, 1),
CPU_TYPE_ENTRY(P1013, P1013, 1),
CPU_TYPE_ENTRY(P1014, P1014, 1),
CPU_TYPE_ENTRY(P1015, P1015, 1),
CPU_TYPE_ENTRY(P1016, P1016, 1),
CPU_TYPE_ENTRY(P1017, P1017, 1),
CPU_TYPE_ENTRY(P1020, P1020, 2),
CPU_TYPE_ENTRY(P1021, P1021, 2),
@ -71,7 +69,6 @@ struct cpu_type cpu_type_list [] = {
CPU_TYPE_ENTRY(P2040, P2040, 4),
CPU_TYPE_ENTRY(P2041, P2041, 4),
CPU_TYPE_ENTRY(P3041, P3041, 4),
CPU_TYPE_ENTRY_MASK(P3060, P3060, 6, 0xf3),
CPU_TYPE_ENTRY(P4040, P4040, 4),
CPU_TYPE_ENTRY(P4080, P4080, 8),
CPU_TYPE_ENTRY(P5010, P5010, 1),
@ -85,7 +82,39 @@ struct cpu_type cpu_type_list [] = {
#endif
};
struct cpu_type cpu_type_unknown = CPU_TYPE_ENTRY(Unknown, Unknown, 1);
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
u32 compute_ppc_cpumask(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
int i = 0, count = 0;
u32 cluster, mask = 0;
do {
int j;
cluster = in_be32(&gur->tp_cluster[i++].lower);
for (j = 0; j < 4; j++) {
u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
u32 type = in_be32(&gur->tp_ityp[idx]);
if (type & TP_ITYP_AV) {
if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC)
mask |= 1 << count;
}
count++;
}
} while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
return mask;
}
#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
/*
* Before chassis genenration 2, the cpumask should be hard-coded.
* In case of cpu type unknown or cpumask unset, use 1 as fail save.
*/
#define compute_ppc_cpumask() 1
#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
struct cpu_type cpu_type_unknown = CPU_TYPE_ENTRY(Unknown, Unknown, 0);
struct cpu_type *identify_cpu(u32 ver)
{
@ -113,6 +142,9 @@ u32 cpu_mask()
return ((in_be32(&pic->frr) & MPC8xxx_PICFRR_NCPU_MASK) >>
MPC8xxx_PICFRR_NCPU_SHIFT) + 1;
if (cpu->num_cores == 0)
return compute_ppc_cpumask();
return cpu->mask;
}
@ -120,13 +152,14 @@ u32 cpu_mask()
* Return the number of cores on this SOC.
*/
int cpu_numcores() {
ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
struct cpu_type *cpu = gd->cpu;
/* better to query feature reporting register than just assume 1 */
if (cpu == &cpu_type_unknown)
return ((in_be32(&pic->frr) & MPC8xxx_PICFRR_NCPU_MASK) >>
MPC8xxx_PICFRR_NCPU_SHIFT) + 1;
/*
* Report # of cores in terms of the cpu_mask if we haven't
* figured out how many there are yet
*/
if (cpu->num_cores == 0)
return hweight32(cpu_mask());
return cpu->num_cores;
}
@ -138,9 +171,7 @@ int cpu_numcores() {
*/
int is_core_valid(unsigned int core)
{
struct cpu_type *cpu = gd->cpu;
return !!((1 << core) & cpu->mask);
return !!((1 << core) & cpu_mask());
}
int probecpu (void)
@ -156,6 +187,19 @@ int probecpu (void)
return 0;
}
/* Once in memory, compute mask & # cores once and save them off */
int fixup_cpu(void)
{
struct cpu_type *cpu = gd->cpu;
if (cpu->num_cores == 0) {
cpu->mask = cpu_mask();
cpu->num_cores = cpu_numcores();
}
return 0;
}
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()

221
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2008-2011 Freescale Semiconductor, Inc.
* Copyright 2008-2012 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
@ -151,8 +151,19 @@ static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
if (dimm_params[dimm_number].n_ranks > 0) {
go_config = 1;
/* These fields only available in CS0_CONFIG */
intlv_en = popts->memctl_interleaving;
intlv_ctl = popts->memctl_interleaving_mode;
if (!popts->memctl_interleaving)
break;
switch (popts->memctl_interleaving_mode) {
case FSL_DDR_CACHE_LINE_INTERLEAVING:
case FSL_DDR_PAGE_INTERLEAVING:
case FSL_DDR_BANK_INTERLEAVING:
case FSL_DDR_SUPERBANK_INTERLEAVING:
intlv_en = popts->memctl_interleaving;
intlv_ctl = popts->memctl_interleaving_mode;
break;
default:
break;
}
}
break;
case 1:
@ -302,29 +313,41 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
/* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts,
const common_timing_params_t *common_dimm,
unsigned int cas_latency)
{
/* Extended precharge to activate interval (tRP) */
unsigned int ext_pretoact = 0;
/* Extended Activate to precharge interval (tRAS) */
unsigned int ext_acttopre = 0;
unsigned int ext_refrec; /* Extended refresh recovery time (tRFC) */
unsigned int ext_caslat = 0; /* Extended MCAS latency from READ cmd */
unsigned int cntl_adj = 0; /* Control Adjust */
/* If the tRAS > 19 MCLK, we use the ext mode */
if (picos_to_mclk(common_dimm->tRAS_ps) > 0x13)
ext_acttopre = 1;
/* Extended activate to read/write interval (tRCD) */
unsigned int ext_acttorw = 0;
/* Extended refresh recovery time (tRFC) */
unsigned int ext_refrec;
/* Extended MCAS latency from READ cmd */
unsigned int ext_caslat = 0;
/* Extended last data to precharge interval (tWR) */
unsigned int ext_wrrec = 0;
/* Control Adjust */
unsigned int cntl_adj = 0;
ext_pretoact = picos_to_mclk(common_dimm->tRP_ps) >> 4;
ext_acttopre = picos_to_mclk(common_dimm->tRAS_ps) >> 4;
ext_acttorw = picos_to_mclk(common_dimm->tRCD_ps) >> 4;
ext_caslat = (2 * cas_latency - 1) >> 4;
ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4;
/* If the CAS latency more than 8, use the ext mode */
if (cas_latency > 8)
ext_caslat = 1;
/* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
ext_wrrec = (picos_to_mclk(common_dimm->tWR_ps) +
(popts->OTF_burst_chop_en ? 2 : 0)) >> 4;
ddr->timing_cfg_3 = (0
| ((ext_acttopre & 0x1) << 24)
| ((ext_refrec & 0xF) << 16)
| ((ext_caslat & 0x1) << 12)
| ((ext_pretoact & 0x1) << 28)
| ((ext_acttopre & 0x2) << 24)
| ((ext_acttorw & 0x1) << 22)
| ((ext_refrec & 0x1F) << 16)
| ((ext_caslat & 0x3) << 12)
| ((ext_wrrec & 0x1) << 8)
| ((cntl_adj & 0x7) << 0)
);
debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
@ -386,15 +409,16 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
* we need set extend bit for it at
* TIMING_CFG_3[EXT_CASLAT]
*/
if (cas_latency > 8)
cas_latency -= 8;
caslat_ctrl = 2 * cas_latency - 1;
#endif
refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8;
wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps);
wrrec_mclk = wrrec_table[wrrec_mclk - 1];
if (wrrec_mclk > 16)
printf("Error: WRREC doesn't support more than 16 clocks\n");
else
wrrec_mclk = wrrec_table[wrrec_mclk - 1];
if (popts->OTF_burst_chop_en)
wrrec_mclk += 2;
@ -825,7 +849,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
/* Mode Register - MR0 */
unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */
unsigned int wr; /* Write Recovery */
unsigned int wr = 0; /* Write Recovery */
unsigned int dll_rst; /* DLL Reset */
unsigned int mode; /* Normal=0 or Test=1 */
unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
@ -885,24 +909,37 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
dll_on = 1;
wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps;
wr = wr_table[wr_mclk - 5];
if (wr_mclk <= 16) {
wr = wr_table[wr_mclk - 5];
} else {
printf("Error: unsupported write recovery for mode register "
"wr_mclk = %d\n", wr_mclk);
}
dll_rst = 0; /* dll no reset */
mode = 0; /* normal mode */
/* look up table to get the cas latency bits */
if (cas_latency >= 5 && cas_latency <= 11) {
unsigned char cas_latency_table[7] = {
if (cas_latency >= 5 && cas_latency <= 16) {
unsigned char cas_latency_table[] = {
0x2, /* 5 clocks */
0x4, /* 6 clocks */
0x6, /* 7 clocks */
0x8, /* 8 clocks */
0xa, /* 9 clocks */
0xc, /* 10 clocks */
0xe /* 11 clocks */
0xe, /* 11 clocks */
0x1, /* 12 clocks */
0x3, /* 13 clocks */
0x5, /* 14 clocks */
0x7, /* 15 clocks */
0x9, /* 16 clocks */
};
caslat = cas_latency_table[cas_latency - 5];
} else {
printf("Error: unsupported cas latency for mode register\n");
}
bt = 0; /* Nibble sequential */
switch (popts->burst_length) {
@ -930,6 +967,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
| ((mode & 0x1) << 7)
| (((caslat >> 1) & 0x7) << 4)
| ((bt & 0x1) << 3)
| ((caslat & 1) << 2)
| ((bl & 0x3) << 0)
);
@ -1399,73 +1437,37 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
/* Chip Select Memory Bounds (CSn_BNDS) */
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
unsigned long long ea = 0, sa = 0;
unsigned long long ea, sa;
unsigned int cs_per_dimm
= CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
unsigned int dimm_number
= i / cs_per_dimm;
unsigned long long rank_density
= dimm_params[dimm_number].rank_density;
= dimm_params[dimm_number].rank_density >> dbw_cap_adj;
if (((i == 1) && (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1)) ||
((i == 2) && (popts->ba_intlv_ctl & 0x04)) ||
((i == 3) && (popts->ba_intlv_ctl & FSL_DDR_CS2_CS3))) {
/*
* Don't set up boundaries for unused CS
* cs1 for cs0_cs1, cs0_cs1_and_cs2_cs3, cs0_cs1_cs2_cs3
* cs2 for cs0_cs1_cs2_cs3
* cs3 for cs2_cs3, cs0_cs1_and_cs2_cs3, cs0_cs1_cs2_cs3
* But we need to set the ODT_RD_CFG and
* ODT_WR_CFG for CS1_CONFIG here.
*/
set_csn_config(dimm_number, i, ddr, popts, dimm_params);
continue;
}
if (dimm_params[dimm_number].n_ranks == 0) {
debug("Skipping setup of CS%u "
"because n_ranks on DIMM %u is 0\n", i, dimm_number);
continue;
}
if (popts->memctl_interleaving && popts->ba_intlv_ctl) {
/*
* This works superbank 2CS
* There are 2 or more memory controllers configured
* identically, memory is interleaved between them,
* and each controller uses rank interleaving within
* itself. Therefore the starting and ending address
* on each controller is twice the amount present on
* each controller. If any CS is not included in the
* interleaving, the memory on that CS is not accssible
* and the total memory size is reduced. The CS is also
* disabled.
*/
unsigned long long ctlr_density = 0;
if (popts->memctl_interleaving) {
switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
case FSL_DDR_CS0_CS1_CS2_CS3:
break;
case FSL_DDR_CS0_CS1:
case FSL_DDR_CS0_CS1_AND_CS2_CS3:
ctlr_density = dimm_params[0].rank_density * 2;
if (i > 1)
cs_en = 0;
break;
case FSL_DDR_CS2_CS3:
ctlr_density = dimm_params[0].rank_density;
default:
if (i > 0)
cs_en = 0;
break;
case FSL_DDR_CS0_CS1_CS2_CS3:
/*
* The four CS interleaving should have been verified by
* populate_memctl_options()
*/
ctlr_density = dimm_params[0].rank_density * 4;
break;
default:
break;
}
ea = (CONFIG_NUM_DDR_CONTROLLERS *
(ctlr_density >> dbw_cap_adj)) - 1;
}
else if (!popts->memctl_interleaving && popts->ba_intlv_ctl) {
sa = common_dimm->base_address;
ea = common_dimm->total_mem - 1;
} else if (!popts->memctl_interleaving) {
/*
* If memory interleaving between controllers is NOT
* enabled, the starting address for each memory
@ -1477,49 +1479,40 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
*/
switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
case FSL_DDR_CS0_CS1_CS2_CS3:
/* CS0+CS1+CS2+CS3 interleaving, only CS0_CNDS
* needs to be set.
*/
sa = common_dimm->base_address;
ea = sa + (4 * (rank_density >> dbw_cap_adj))-1;
ea = common_dimm->total_mem - 1;
break;
case FSL_DDR_CS0_CS1_AND_CS2_CS3:
/* CS0+CS1 and CS2+CS3 interleaving, CS0_CNDS
* and CS2_CNDS need to be set.
*/
if ((i == 2) && (dimm_number == 0)) {
if ((i >= 2) && (dimm_number == 0)) {
sa = dimm_params[dimm_number].base_address +
2 * (rank_density >> dbw_cap_adj);
ea = sa + 2 * (rank_density >> dbw_cap_adj) - 1;
2 * rank_density;
ea = sa + 2 * rank_density - 1;
} else {
sa = dimm_params[dimm_number].base_address;
ea = sa + (2 * (rank_density >>
dbw_cap_adj)) - 1;
ea = sa + 2 * rank_density - 1;
}
break;
case FSL_DDR_CS0_CS1:
/* CS0+CS1 interleaving, CS0_CNDS needs
* to be set
*/
if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
sa = dimm_params[dimm_number].base_address;
ea = sa + (rank_density >> dbw_cap_adj) - 1;
sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
ea = sa + rank_density - 1;
if (i != 1)
sa += (i % cs_per_dimm) * rank_density;
ea += (i % cs_per_dimm) * rank_density;
} else {
sa = 0;
ea = 0;
}
if (i == 0)
ea += (rank_density >> dbw_cap_adj);
ea += rank_density;
break;
case FSL_DDR_CS2_CS3:
/* CS2+CS3 interleaving*/
if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
sa = dimm_params[dimm_number].base_address;
ea = sa + (rank_density >> dbw_cap_adj) - 1;
sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
ea = sa + rank_density - 1;
if (i != 3)
sa += (i % cs_per_dimm) * rank_density;
ea += (i % cs_per_dimm) * rank_density;
} else {
sa = 0;
ea = 0;
@ -1528,38 +1521,18 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
ea += (rank_density >> dbw_cap_adj);
break;
default: /* No bank(chip-select) interleaving */
sa = dimm_params[dimm_number].base_address;
ea = sa + rank_density - 1;
if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
sa += (i % cs_per_dimm) * rank_density;
ea += (i % cs_per_dimm) * rank_density;
} else {
sa = 0;
ea = 0;
}
break;
}
}
else if (popts->memctl_interleaving && !popts->ba_intlv_ctl) {
/*
* Only the rank on CS0 of each memory controller may
* be used if memory controller interleaving is used
* without rank interleaving within each memory
* controller. However, the ending address programmed
* into each CS0 must be the sum of the amount of
* memory in the two CS0 ranks.
*/
if (i == 0) {
ea = (2 * (rank_density >> dbw_cap_adj)) - 1;
}
}
else if (!popts->memctl_interleaving && !popts->ba_intlv_ctl) {
/*
* No rank interleaving and no memory controller
* interleaving.
*/
sa = dimm_params[dimm_number].base_address;
ea = sa + (rank_density >> dbw_cap_adj) - 1;
if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
sa += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
ea += (i % cs_per_dimm) * (rank_density >> dbw_cap_adj);
} else {
sa = 0;
ea = 0;
}
}
sa >>= 24;
ea >>= 24;
@ -1574,7 +1547,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
set_csn_config(dimm_number, i, ddr, popts, dimm_params);
set_csn_config_2(i, ddr);
} else
printf("CS%d is disabled.\n", i);
debug("CS%d is disabled.\n", i);
}
/*
@ -1590,7 +1563,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
set_timing_cfg_0(ddr, popts);
#endif
set_timing_cfg_3(ddr, common_dimm, cas_latency);
set_timing_cfg_3(ddr, popts, common_dimm, cas_latency);
set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
set_timing_cfg_2(ddr, popts, common_dimm,
cas_latency, additive_latency);

25
arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2008-2009 Freescale Semiconductor, Inc.
* Copyright 2008-2012 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
*
* calculate the organization and timing parameter
@ -90,6 +90,7 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
{
unsigned int retval;
unsigned int mtb_ps;
int ftb_10th_ps;
int i;
if (spd->mem_type) {
@ -196,6 +197,14 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
mtb_ps = (spd->mtb_dividend * 1000) /spd->mtb_divisor;
pdimm->mtb_ps = mtb_ps;
/*
* FTB - fine timebase
* use 1/10th of ps as our unit to avoid floating point
* eg, 10 for 1ps, 25 for 2.5ps, 50 for 5ps
*/
ftb_10th_ps =
((spd->ftb_div & 0xf0) >> 4) * 10 / (spd->ftb_div & 0x0f);
pdimm->ftb_10th_ps = ftb_10th_ps;
/*
* sdram minimum cycle time
* we assume the MTB is 0.125ns
@ -204,7 +213,8 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
* =12 MTB (1.5ns) ->DDR3-1333
* =10 MTB (1.25ns) ->DDR3-1600
*/
pdimm->tCKmin_X_ps = spd->tCK_min * mtb_ps;
pdimm->tCKmin_X_ps = spd->tCK_min * mtb_ps +
(spd->fine_tCK_min * ftb_10th_ps) / 10;
/*
* CAS latency supported
@ -222,7 +232,8 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
* DDR3-1333H 108 MTB (13.5ns)
* DDR3-1600H 90 MTB (11.25ns)
*/
pdimm->tAA_ps = spd->tAA_min * mtb_ps;
pdimm->tAA_ps = spd->tAA_min * mtb_ps +
(spd->fine_tAA_min * ftb_10th_ps) / 10;
/*
* min write recovery time
@ -239,7 +250,8 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
* DDR3-1333H 108 MTB (13.5ns)
* DDR3-1600H 90 MTB (11.25)
*/
pdimm->tRCD_ps = spd->tRCD_min * mtb_ps;
pdimm->tRCD_ps = spd->tRCD_min * mtb_ps +
(spd->fine_tRCD_min * ftb_10th_ps) / 10;
/*
* min row active to row active delay time
@ -257,7 +269,8 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
* DDR3-1333H 108 MTB (13.5ns)
* DDR3-1600H 90 MTB (11.25ns)
*/
pdimm->tRP_ps = spd->tRP_min * mtb_ps;
pdimm->tRP_ps = spd->tRP_min * mtb_ps +
(spd->fine_tRP_min * ftb_10th_ps) / 10;
/* min active to precharge delay time
* eg: tRAS_min =
@ -277,7 +290,7 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
* DDR3-1600H 370 MTB (46.25ns)
*/
pdimm->tRC_ps = (((spd->tRAS_tRC_ext & 0xf0) << 4) | spd->tRC_min_lsb)
* mtb_ps;
* mtb_ps + (spd->fine_tRC_min * ftb_10th_ps) / 10;
/*
* min refresh recovery delay time
* eg: tRFC_min =

22
arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2010-2011 Freescale Semiconductor, Inc.
* Copyright 2010-2012 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@ -1047,7 +1047,7 @@ void ddr3_spd_dump(const ddr3_spd_eeprom_t *spd)
/* General Section: Bytes 0-59 */
#define PRINT_NXS(x, y, z...) printf("%-3d : %02x " z "\n", x, y);
#define PRINT_NXS(x, y, z...) printf("%-3d : %02x " z "\n", x, (u8)y);
#define PRINT_NNXXS(n0, n1, x0, x1, s) \
printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1);
@ -1121,11 +1121,21 @@ void ddr3_spd_dump(const ddr3_spd_eeprom_t *spd)
"therm_sensor SDRAM Thermal Sensor");
PRINT_NXS(33, spd->device_type,
"device_type SDRAM Device Type");
PRINT_NXS(34, spd->fine_tCK_min,
"fine_tCK_min Fine offset for tCKmin");
PRINT_NXS(35, spd->fine_tAA_min,
"fine_tAA_min Fine offset for tAAmin");
PRINT_NXS(36, spd->fine_tRCD_min,
"fine_tRCD_min Fine offset for tRCDmin");
PRINT_NXS(37, spd->fine_tRP_min,
"fine_tRP_min Fine offset for tRPmin");
PRINT_NXS(38, spd->fine_tRC_min,
"fine_tRC_min Fine offset for tRCmin");
printf("%-3d-%3d: ", 34, 59); /* Reserved, General Section */
printf("%-3d-%3d: ", 39, 59); /* Reserved, General Section */
for (i = 34; i <= 59; i++)
printf("%02x ", spd->res_34_59[i - 34]);
for (i = 39; i <= 59; i++)
printf("%02x ", spd->res_39_59[i - 39]);
puts("\n");
@ -1388,7 +1398,7 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo)
* No need to worry for buffer overflow here in
* this function; readline() maxes out at CFG_CBSIZE
*/
readline_into_buffer(prompt, buffer);
readline_into_buffer(prompt, buffer, 0);
argc = parse_line(buffer, argv);
if (argc == 0)
continue;

18
arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2008-2011 Freescale Semiconductor, Inc.
* Copyright 2008-2012 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@ -27,8 +27,10 @@ compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
/* compute the common CAS latency supported between slots */
tmp = dimm_params[0].caslat_X;
for (i = 1; i < number_of_dimms; i++)
tmp &= dimm_params[i].caslat_X;
for (i = 1; i < number_of_dimms; i++) {
if (dimm_params[i].n_ranks)
tmp &= dimm_params[i].caslat_X;
}
common_caslat = tmp;
/* compute the max tAAmin tCKmin between slots */
@ -491,5 +493,15 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
*/
outpdimm->additive_latency = additive_latency;
debug("tCKmin_ps = %u\n", outpdimm->tCKmin_X_ps);
debug("tRCD_ps = %u\n", outpdimm->tRCD_ps);
debug("tRP_ps = %u\n", outpdimm->tRP_ps);
debug("tRAS_ps = %u\n", outpdimm->tRAS_ps);
debug("tWR_ps = %u\n", outpdimm->tWR_ps);
debug("tWTR_ps = %u\n", outpdimm->tWTR_ps);
debug("tRFC_ps = %u\n", outpdimm->tRFC_ps);
debug("tRRD_ps = %u\n", outpdimm->tRRD_ps);
debug("tRC_ps = %u\n", outpdimm->tRC_ps);
return 0;
}

307
arch/powerpc/cpu/mpc8xxx/ddr/main.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2008-2011 Freescale Semiconductor, Inc.
* Copyright 2008-2012 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@ -15,13 +15,15 @@
#include <common.h>
#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_law.h>
#include "ddr.h"
extern void fsl_ddr_set_lawbar(
void fsl_ddr_set_lawbar(
const common_timing_params_t *memctl_common_params,
unsigned int memctl_interleaved,
unsigned int ctrl_num);
void fsl_ddr_set_intl3r(const unsigned int granule_size);
/* processor specific function */
extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
@ -51,6 +53,22 @@ u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
[1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
[1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */
};
#elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
[0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
[1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
[2][0] = SPD_EEPROM_ADDRESS3, /* controller 3 */
};
#elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
[0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
[0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
[1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
[1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */
[2][0] = SPD_EEPROM_ADDRESS5, /* controller 3 */
[2][1] = SPD_EEPROM_ADDRESS6, /* controller 3 */
};
#endif
static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
@ -156,12 +174,12 @@ const char * step_to_string(unsigned int step) {
return step_string_tbl[s];
}
int step_assign_addresses(fsl_ddr_info_t *pinfo,
unsigned int dbw_cap_adj[],
unsigned int *all_memctl_interleaving,
unsigned int *all_ctlr_rank_interleaving)
unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
unsigned int dbw_cap_adj[])
{
int i, j;
unsigned long long total_mem, current_mem_base, total_ctlr_mem;
unsigned long long rank_density, ctlr_density = 0;
/*
* If a reduced data width is requested, but the SPD
@ -220,86 +238,108 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo,
"specified controller %u\n", i);
return 1;
}
debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]);
}
j = 0;
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
if (pinfo->memctl_opts[i].memctl_interleaving)
j++;
/*
* Not support less than all memory controllers interleaving
* if more than two controllers
*/
if (j == CONFIG_NUM_DDR_CONTROLLERS)
*all_memctl_interleaving = 1;
/* Check that all controllers are rank interleaving. */
j = 0;
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
if (pinfo->memctl_opts[i].ba_intlv_ctl)
j++;
/*
* All memory controllers must be populated to qualify for
* all controller rank interleaving
*/
if (j == CONFIG_NUM_DDR_CONTROLLERS)
*all_ctlr_rank_interleaving = 1;
if (*all_memctl_interleaving) {
unsigned long long addr, total_mem_per_ctlr = 0;
/*
* If interleaving between memory controllers,
* make each controller start at a base address
* of 0.
*
* Also, if bank interleaving (chip select
* interleaving) is enabled on each memory
* controller, CS0 needs to be programmed to
* cover the entire memory range on that memory
* controller
*
* Bank interleaving also implies that each
* addressed chip select is identical in size.
*/
current_mem_base = 0ull;
total_mem = 0;
if (pinfo->memctl_opts[0].memctl_interleaving) {
rank_density = pinfo->dimm_params[0][0].rank_density >>
dbw_cap_adj[0];
switch (pinfo->memctl_opts[0].ba_intlv_ctl &
FSL_DDR_CS0_CS1_CS2_CS3) {
case FSL_DDR_CS0_CS1_CS2_CS3:
ctlr_density = 4 * rank_density;
break;
case FSL_DDR_CS0_CS1:
case FSL_DDR_CS0_CS1_AND_CS2_CS3:
ctlr_density = 2 * rank_density;
break;
case FSL_DDR_CS2_CS3:
default:
ctlr_density = rank_density;
break;
}
debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
rank_density, ctlr_density);
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
addr = 0;
pinfo->common_timing_params[i].base_address = 0ull;
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
unsigned long long cap
= pinfo->dimm_params[i][j].capacity;
pinfo->dimm_params[i][j].base_address = addr;
addr += cap >> dbw_cap_adj[i];
total_mem_per_ctlr += cap >> dbw_cap_adj[i];
if (pinfo->memctl_opts[i].memctl_interleaving) {
switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
case FSL_DDR_CACHE_LINE_INTERLEAVING:
case FSL_DDR_PAGE_INTERLEAVING:
case FSL_DDR_BANK_INTERLEAVING:
case FSL_DDR_SUPERBANK_INTERLEAVING:
total_ctlr_mem = 2 * ctlr_density;
break;
case FSL_DDR_3WAY_1KB_INTERLEAVING:
case FSL_DDR_3WAY_4KB_INTERLEAVING:
case FSL_DDR_3WAY_8KB_INTERLEAVING:
total_ctlr_mem = 3 * ctlr_density;
break;
case FSL_DDR_4WAY_1KB_INTERLEAVING:
case FSL_DDR_4WAY_4KB_INTERLEAVING:
case FSL_DDR_4WAY_8KB_INTERLEAVING:
total_ctlr_mem = 4 * ctlr_density;
break;
default:
panic("Unknown interleaving mode");
}
pinfo->common_timing_params[i].base_address =
current_mem_base;
pinfo->common_timing_params[i].total_mem =
total_ctlr_mem;
total_mem = current_mem_base + total_ctlr_mem;
debug("ctrl %d base 0x%llx\n", i, current_mem_base);
debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
} else {
/* when 3rd controller not interleaved */
current_mem_base = total_mem;
total_ctlr_mem = 0;
pinfo->common_timing_params[i].base_address =
current_mem_base;
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
unsigned long long cap =
pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
pinfo->dimm_params[i][j].base_address =
current_mem_base;
debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
current_mem_base += cap;
total_ctlr_mem += cap;
}
debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
pinfo->common_timing_params[i].total_mem =
total_ctlr_mem;
total_mem += total_ctlr_mem;
}
}
pinfo->common_timing_params[0].total_mem = total_mem_per_ctlr;
} else {
/*
* Simple linear assignment if memory
* controllers are not interleaved.
*/
unsigned long long cur_memsize = 0;
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
u64 total_mem_per_ctlr = 0;
total_ctlr_mem = 0;
pinfo->common_timing_params[i].base_address =
cur_memsize;
current_mem_base;
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
/* Compute DIMM base addresses. */
unsigned long long cap =
pinfo->dimm_params[i][j].capacity;
pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
pinfo->dimm_params[i][j].base_address =
cur_memsize;
cur_memsize += cap >> dbw_cap_adj[i];
total_mem_per_ctlr += cap >> dbw_cap_adj[i];
current_mem_base;
debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
current_mem_base += cap;
total_ctlr_mem += cap;
}
debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
pinfo->common_timing_params[i].total_mem =
total_mem_per_ctlr;
total_ctlr_mem;
total_mem += total_ctlr_mem;
}
}
debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
return 0;
return total_mem;
}
unsigned long long
@ -307,8 +347,6 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
unsigned int size_only)
{
unsigned int i, j;
unsigned int all_controllers_memctl_interleaving = 0;
unsigned int all_controllers_rank_interleaving = 0;
unsigned long long total_mem = 0;
fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
@ -345,9 +383,10 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
retval = compute_dimm_parameters(spd, pdimm, i);
#ifdef CONFIG_SYS_DDR_RAW_TIMING
if (retval != 0) {
printf("SPD error! Trying fallback to "
"raw timing calculation\n");
if (!i && !j && retval) {
printf("SPD error on controller %d! "
"Trying fallback to raw timing "
"calculation\n", i);
fsl_ddr_get_dimm_params(pdimm, i, j);
}
#else
@ -407,17 +446,14 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
&pinfo->memctl_opts[i],
pinfo->dimm_params[i], i);
}
check_interleaving_options(pinfo);
case STEP_ASSIGN_ADDRESSES:
/* STEP 5: Assign addresses to chip selects */
step_assign_addresses(pinfo,
dbw_capacity_adjust,
&all_controllers_memctl_interleaving,
&all_controllers_rank_interleaving);
check_interleaving_options(pinfo);
total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust);
case STEP_COMPUTE_REGS:
/* STEP 6: compute controller register values */
debug("FSL Memory ctrl cg register computation\n");
debug("FSL Memory ctrl register computation\n");
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
if (timing_params[i].ndimms_present == 0) {
memset(&ddr_reg[i], 0,
@ -437,21 +473,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
break;
}
/* Compute the total amount of memory. */
/*
* If bank interleaving but NOT memory controller interleaving
* CS_BNDS describe the quantity of memory on each memory
* controller, so the total is the sum across.
*/
if (!all_controllers_memctl_interleaving
&& all_controllers_rank_interleaving) {
total_mem = 0;
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
total_mem += timing_params[i].total_mem;
}
} else {
{
/*
* Compute the amount of memory available just by
* looking for the highest valid CSn_BNDS value.
@ -489,7 +511,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
phys_size_t fsl_ddr_sdram(void)
{
unsigned int i;
unsigned int memctl_interleaved;
unsigned int law_memctl = LAW_TRGT_IF_DDR_1;
unsigned long long total_memory;
fsl_ddr_info_t info;
@ -504,34 +526,6 @@ phys_size_t fsl_ddr_sdram(void)
#endif
total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0);
/* Check for memory controller interleaving. */
memctl_interleaved = 0;
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
memctl_interleaved +=
info.memctl_opts[i].memctl_interleaving;
}
if (memctl_interleaved) {
if (memctl_interleaved == CONFIG_NUM_DDR_CONTROLLERS) {
debug("memctl interleaving\n");
/*
* Change the meaning of memctl_interleaved
* to be "boolean".
*/
memctl_interleaved = 1;
} else {
printf("Warning: memctl interleaving not "
"properly configured on all controllers\n");
memctl_interleaved = 0;
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
info.memctl_opts[i].memctl_interleaving = 0;
debug("Recomputing with memctl_interleaving off.\n");
total_memory = fsl_ddr_compute(&info,
STEP_ASSIGN_ADDRESSES,
0);
}
}
/* Program configuration registers. */
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
debug("Programming controller %u\n", i);
@ -544,24 +538,69 @@ phys_size_t fsl_ddr_sdram(void)
fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i);
}
if (memctl_interleaved) {
const unsigned int ctrl_num = 0;
/* Only set LAWBAR1 if memory controller interleaving is on. */
fsl_ddr_set_lawbar(&info.common_timing_params[0],
memctl_interleaved, ctrl_num);
} else {
/*
* Memory controller interleaving is NOT on;
* set each lawbar individually.
*/
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
/* program LAWs */
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
if (info.memctl_opts[i].memctl_interleaving) {
switch (info.memctl_opts[i].memctl_interleaving_mode) {
case FSL_DDR_CACHE_LINE_INTERLEAVING:
case FSL_DDR_PAGE_INTERLEAVING:
case FSL_DDR_BANK_INTERLEAVING:
case FSL_DDR_SUPERBANK_INTERLEAVING:
if (i == 0) {
law_memctl = LAW_TRGT_IF_DDR_INTRLV;
fsl_ddr_set_lawbar(&info.common_timing_params[i],
law_memctl, i);
} else if (i == 2) {
law_memctl = LAW_TRGT_IF_DDR_INTLV_34;
fsl_ddr_set_lawbar(&info.common_timing_params[i],
law_memctl, i);
}
break;
case FSL_DDR_3WAY_1KB_INTERLEAVING:
case FSL_DDR_3WAY_4KB_INTERLEAVING:
case FSL_DDR_3WAY_8KB_INTERLEAVING:
law_memctl = LAW_TRGT_IF_DDR_INTLV_123;
if (i == 0) {
fsl_ddr_set_intl3r(info.memctl_opts[i].memctl_interleaving_mode);
fsl_ddr_set_lawbar(&info.common_timing_params[i],
law_memctl, i);
}
break;
case FSL_DDR_4WAY_1KB_INTERLEAVING:
case FSL_DDR_4WAY_4KB_INTERLEAVING:
case FSL_DDR_4WAY_8KB_INTERLEAVING:
law_memctl = LAW_TRGT_IF_DDR_INTLV_1234;
if (i == 0)
fsl_ddr_set_lawbar(&info.common_timing_params[i],
law_memctl, i);
/* place holder for future 4-way interleaving */
break;
default:
break;
}
} else {
switch (i) {
case 0:
law_memctl = LAW_TRGT_IF_DDR_1;
break;
case 1:
law_memctl = LAW_TRGT_IF_DDR_2;
break;
case 2:
law_memctl = LAW_TRGT_IF_DDR_3;
break;
case 3:
law_memctl = LAW_TRGT_IF_DDR_4;
break;
default:
break;
}
fsl_ddr_set_lawbar(&info.common_timing_params[i],
0, i);
law_memctl, i);
}
}
debug("total_memory = %llu\n", total_memory);
debug("total_memory by %s = %llu\n", __func__, total_memory);
#if !defined(CONFIG_PHYS_64BIT)
/* Check for 4G or more. Bad. */

212
arch/powerpc/cpu/mpc8xxx/ddr/options.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2008, 2010-2011 Freescale Semiconductor, Inc.
* Copyright 2008, 2010-2012 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
@ -19,7 +19,6 @@
* This is pretty fragile on both the use of stack and if the buffer is big
* enough. However we will get a warning from getenv_f for the later.
*/
#define HWCONFIG_BUFFER_SIZE 128
/* Board-specific functions defined in each board's ddr.c */
extern void fsl_ddr_board_options(memctl_options_t *popts,
@ -790,46 +789,97 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
* should be a subset of the requested configuration.
*/
#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
if (hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf)) {
if (pdimm[0].n_ranks == 0) {
printf("There is no rank on CS0 for controller %d. Because only"
" rank on CS0 and ranks chip-select interleaved with CS0"
" are controller interleaved, force non memory "
"controller interleaving\n", ctrl_num);
popts->memctl_interleaving = 0;
} else {
popts->memctl_interleaving = 1;
/*
* test null first. if CONFIG_HWCONFIG is not defined
* hwconfig_arg_cmp returns non-zero
*/
if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
"null", buf)) {
popts->memctl_interleaving = 0;
debug("memory controller interleaving disabled.\n");
} else if (hwconfig_subarg_cmp_f("fsl_ddr",
"ctlr_intlv",
"cacheline", buf))
popts->memctl_interleaving_mode =
FSL_DDR_CACHE_LINE_INTERLEAVING;
else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
"page", buf))
popts->memctl_interleaving_mode =
FSL_DDR_PAGE_INTERLEAVING;
else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
"bank", buf))
popts->memctl_interleaving_mode =
FSL_DDR_BANK_INTERLEAVING;
else if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
"superbank", buf))
popts->memctl_interleaving_mode =
FSL_DDR_SUPERBANK_INTERLEAVING;
else {
popts->memctl_interleaving = 0;
printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
}
}
if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf))
goto done;
if (pdimm[0].n_ranks == 0) {
printf("There is no rank on CS0 for controller %d.\n", ctrl_num);
popts->memctl_interleaving = 0;
goto done;
}
popts->memctl_interleaving = 1;
/*
* test null first. if CONFIG_HWCONFIG is not defined
* hwconfig_arg_cmp returns non-zero
*/
if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
"null", buf)) {
popts->memctl_interleaving = 0;
debug("memory controller interleaving disabled.\n");
} else if (hwconfig_subarg_cmp_f("fsl_ddr",
"ctlr_intlv",
"cacheline", buf)) {
popts->memctl_interleaving_mode =
((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
0 : FSL_DDR_CACHE_LINE_INTERLEAVING;
popts->memctl_interleaving =
((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
0 : 1;
} else if (hwconfig_subarg_cmp_f("fsl_ddr",
"ctlr_intlv",
"page", buf)) {
popts->memctl_interleaving_mode =
((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
0 : FSL_DDR_PAGE_INTERLEAVING;
popts->memctl_interleaving =
((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
0 : 1;
} else if (hwconfig_subarg_cmp_f("fsl_ddr",
"ctlr_intlv",
"bank", buf)) {
popts->memctl_interleaving_mode =
((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
0 : FSL_DDR_BANK_INTERLEAVING;
popts->memctl_interleaving =
((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
0 : 1;
} else if (hwconfig_subarg_cmp_f("fsl_ddr",
"ctlr_intlv",
"superbank", buf)) {
popts->memctl_interleaving_mode =
((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
0 : FSL_DDR_SUPERBANK_INTERLEAVING;
popts->memctl_interleaving =
((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
0 : 1;
#if (CONFIG_NUM_DDR_CONTROLLERS == 3)
} else if (hwconfig_subarg_cmp_f("fsl_ddr",
"ctlr_intlv",
"3way_1KB", buf)) {
popts->memctl_interleaving_mode =
FSL_DDR_3WAY_1KB_INTERLEAVING;
} else if (hwconfig_subarg_cmp_f("fsl_ddr",
"ctlr_intlv",
"3way_4KB", buf)) {
popts->memctl_interleaving_mode =
FSL_DDR_3WAY_4KB_INTERLEAVING;
} else if (hwconfig_subarg_cmp_f("fsl_ddr",
"ctlr_intlv",
"3way_8KB", buf)) {
popts->memctl_interleaving_mode =
FSL_DDR_3WAY_8KB_INTERLEAVING;
#elif (CONFIG_NUM_DDR_CONTROLLERS == 4)
} else if (hwconfig_subarg_cmp_f("fsl_ddr",
"ctlr_intlv",
"4way_1KB", buf)) {
popts->memctl_interleaving_mode =
FSL_DDR_4WAY_1KB_INTERLEAVING;
} else if (hwconfig_subarg_cmp_f("fsl_ddr",
"ctlr_intlv",
"4way_4KB", buf)) {
popts->memctl_interleaving_mode =
FSL_DDR_4WAY_4KB_INTERLEAVING;
} else if (hwconfig_subarg_cmp_f("fsl_ddr",
"ctlr_intlv",
"4way_8KB", buf)) {
popts->memctl_interleaving_mode =
FSL_DDR_4WAY_8KB_INTERLEAVING;
#endif
} else {
popts->memctl_interleaving = 0;
printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
}
done:
#endif
if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) &&
(CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
@ -859,20 +909,20 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
popts->ba_intlv_ctl = 0;
printf("Not enough bank(chip-select) for "
"CS0+CS1+CS2+CS3 on controller %d, "
"force non-interleaving!\n", ctrl_num);
"interleaving disabled!\n", ctrl_num);
}
#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) {
popts->ba_intlv_ctl = 0;
printf("Not enough bank(chip-select) for "
"CS0+CS1+CS2+CS3 on controller %d, "
"force non-interleaving!\n", ctrl_num);
"interleaving disabled!\n", ctrl_num);
}
if (pdimm[0].capacity != pdimm[1].capacity) {
popts->ba_intlv_ctl = 0;
printf("Not identical DIMM size for "
"CS0+CS1+CS2+CS3 on controller %d, "
"force non-interleaving!\n", ctrl_num);
"interleaving disabled!\n", ctrl_num);
}
#endif
break;
@ -881,7 +931,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
popts->ba_intlv_ctl = 0;
printf("Not enough bank(chip-select) for "
"CS0+CS1 on controller %d, "
"force non-interleaving!\n", ctrl_num);
"interleaving disabled!\n", ctrl_num);
}
break;
case FSL_DDR_CS2_CS3:
@ -889,13 +939,13 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
if (pdimm[0].n_ranks < 4) {
popts->ba_intlv_ctl = 0;
printf("Not enough bank(chip-select) for CS2+CS3 "
"on controller %d, force non-interleaving!\n", ctrl_num);
"on controller %d, interleaving disabled!\n", ctrl_num);
}
#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
if (pdimm[1].n_ranks < 2) {
popts->ba_intlv_ctl = 0;
printf("Not enough bank(chip-select) for CS2+CS3 "
"on controller %d, force non-interleaving!\n", ctrl_num);
"on controller %d, interleaving disabled!\n", ctrl_num);
}
#endif
break;
@ -905,14 +955,14 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
popts->ba_intlv_ctl = 0;
printf("Not enough bank(CS) for CS0+CS1 and "
"CS2+CS3 on controller %d, "
"force non-interleaving!\n", ctrl_num);
"interleaving disabled!\n", ctrl_num);
}
#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) {
popts->ba_intlv_ctl = 0;
printf("Not enough bank(CS) for CS0+CS1 and "
"CS2+CS3 on controller %d, "
"force non-interleaving!\n", ctrl_num);
"interleaving disabled!\n", ctrl_num);
}
#endif
break;
@ -954,33 +1004,73 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
void check_interleaving_options(fsl_ddr_info_t *pinfo)
{
int i, j, check_n_ranks, intlv_fixed = 0;
int i, j, k, check_n_ranks, intlv_invalid = 0;
unsigned int check_intlv, check_n_row_addr, check_n_col_addr;
unsigned long long check_rank_density;
struct dimm_params_s *dimm;
/*
* Check if all controllers are configured for memory
* controller interleaving. Identical dimms are recommended. At least
* the size should be checked.
* the size, row and col address should be checked.
*/
j = 0;
check_n_ranks = pinfo->dimm_params[0][0].n_ranks;
check_rank_density = pinfo->dimm_params[0][0].rank_density;
check_n_row_addr = pinfo->dimm_params[0][0].n_row_addr;
check_n_col_addr = pinfo->dimm_params[0][0].n_col_addr;
check_intlv = pinfo->memctl_opts[0].memctl_interleaving_mode;
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
if ((pinfo->memctl_opts[i].memctl_interleaving) && \
(check_rank_density == pinfo->dimm_params[i][0].rank_density) && \
(check_n_ranks == pinfo->dimm_params[i][0].n_ranks)) {
dimm = &pinfo->dimm_params[i][0];
if (!pinfo->memctl_opts[i].memctl_interleaving) {
continue;
} else if (((check_rank_density != dimm->rank_density) ||
(check_n_ranks != dimm->n_ranks) ||
(check_n_row_addr != dimm->n_row_addr) ||
(check_n_col_addr != dimm->n_col_addr) ||
(check_intlv !=
pinfo->memctl_opts[i].memctl_interleaving_mode))){
intlv_invalid = 1;
break;
} else {
j++;
}
}
if (j != CONFIG_NUM_DDR_CONTROLLERS) {
if (intlv_invalid) {
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
if (pinfo->memctl_opts[i].memctl_interleaving) {
pinfo->memctl_opts[i].memctl_interleaving = 0;
printf("Not all DIMMs are identical. "
"Memory controller interleaving disabled.\n");
} else {
switch (check_intlv) {
case FSL_DDR_CACHE_LINE_INTERLEAVING:
case FSL_DDR_PAGE_INTERLEAVING:
case FSL_DDR_BANK_INTERLEAVING:
case FSL_DDR_SUPERBANK_INTERLEAVING:
if (3 == CONFIG_NUM_DDR_CONTROLLERS)
k = 2;
else
k = CONFIG_NUM_DDR_CONTROLLERS;
break;
case FSL_DDR_3WAY_1KB_INTERLEAVING:
case FSL_DDR_3WAY_4KB_INTERLEAVING:
case FSL_DDR_3WAY_8KB_INTERLEAVING:
case FSL_DDR_4WAY_1KB_INTERLEAVING:
case FSL_DDR_4WAY_4KB_INTERLEAVING:
case FSL_DDR_4WAY_8KB_INTERLEAVING:
default:
k = CONFIG_NUM_DDR_CONTROLLERS;
break;
}
debug("%d of %d controllers are interleaving.\n", j, k);
if (j != k) {
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
pinfo->memctl_opts[i].memctl_interleaving = 0;
intlv_fixed = 1;
}
if (intlv_fixed)
printf("Not all DIMMs are identical in size. "
"Memory controller interleaving disabled.\n");
printf("Not all controllers have compatible "
"interleaving mode. All disabled.\n");
}
}
debug("Checking interleaving options completed\n");
}
int fsl_use_spd(void)

67
arch/powerpc/cpu/mpc8xxx/ddr/util.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2008-2011 Freescale Semiconductor, Inc.
* Copyright 2008-2012 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@ -79,7 +79,7 @@ unsigned int mclk_to_picos(unsigned int mclk)
void
__fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
unsigned int memctl_interleaved,
unsigned int law_memctl,
unsigned int ctrl_num)
{
unsigned long long base = memctl_common_params->base_address;
@ -98,28 +98,13 @@ __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
if ((base + size) >= CONFIG_MAX_MEM_MAPPED)
size = CONFIG_MAX_MEM_MAPPED - base;
#endif
if (ctrl_num == 0) {
/*
* Set up LAW for DDR controller 1 space.
*/
unsigned int lawbar1_target_id = memctl_interleaved
? LAW_TRGT_IF_DDR_INTRLV : LAW_TRGT_IF_DDR_1;
if (set_ddr_laws(base, size, lawbar1_target_id) < 0) {
printf("%s: ERROR (ctrl #0, intrlv=%d)\n", __func__,
memctl_interleaved);
return ;
}
} else if (ctrl_num == 1) {
if (set_ddr_laws(base, size, LAW_TRGT_IF_DDR_2) < 0) {
printf("%s: ERROR (ctrl #1)\n", __func__);
return ;
}
} else {
printf("%s: unexpected DDR controller number (%u)\n", __func__,
ctrl_num);
if (set_ddr_laws(base, size, law_memctl) < 0) {
printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num,
law_memctl);
return ;
}
debug("setup ddr law base = 0x%llx, size 0x%llx, TRGT_ID 0x%x\n",
base, size, law_memctl);
}
__attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void
@ -127,6 +112,15 @@ fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
unsigned int memctl_interleaved,
unsigned int ctrl_num);
void fsl_ddr_set_intl3r(const unsigned int granule_size)
{
#ifdef CONFIG_E6500
u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
*mcintl3r = 0x80000000 | (granule_size & 0x1f);
debug("Enable MCINTL3R with granule size 0x%x\n", granule_size);
#endif
}
void board_add_ram_info(int use_default)
{
#if defined(CONFIG_MPC83xx)
@ -137,6 +131,9 @@ void board_add_ram_info(int use_default)
#elif defined(CONFIG_MPC86xx)
ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC86xx_DDR_ADDR);
#endif
#if defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3)
u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
#endif
#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
uint32_t cs0_config = in_be32(&ddr->cs0_config);
#endif
@ -180,7 +177,29 @@ void board_add_ram_info(int use_default)
else
puts(", ECC off)");
#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
#if (CONFIG_NUM_DDR_CONTROLLERS == 3)
#ifdef CONFIG_E6500
if (*mcintl3r & 0x80000000) {
puts("\n");
puts(" DDR Controller Interleaving Mode: ");
switch (*mcintl3r & 0x1f) {
case FSL_DDR_3WAY_1KB_INTERLEAVING:
puts("3-way 1KB");
break;
case FSL_DDR_3WAY_4KB_INTERLEAVING:
puts("3-way 4KB");
break;
case FSL_DDR_3WAY_8KB_INTERLEAVING:
puts("3-way 8KB");
break;
default:
puts("3-way UNKNOWN");
break;
}
}
#endif
#endif
#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
if (cs0_config & 0x20000000) {
puts("\n");
puts(" DDR Controller Interleaving Mode: ");

3
arch/powerpc/cpu/mpc8xxx/fdt.c
View File

@ -62,8 +62,9 @@ void ft_fixup_num_cores(void *blob) {
off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
while (off != -FDT_ERR_NOTFOUND) {
u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
u32 phys_cpu_id = thread_to_core(*reg);
if (!is_core_valid(*reg) || is_core_disabled(*reg)) {
if (!is_core_valid(phys_cpu_id) || is_core_disabled(phys_cpu_id)) {
int ph = fdt_get_phandle(blob, off);
/* Delete the cpu node once there are no cpu handles */

12
arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
View File

@ -44,12 +44,18 @@ void init_early_memctl_regs(void)
set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3);
#if !defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) || defined(CONFIG_SYS_RAMBOOT)
#ifdef CONFIG_SYS_CSPR0_EXT
set_ifc_cspr_ext(IFC_CS0, CONFIG_SYS_CSPR0_EXT);
#endif
set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0);
set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0);
#endif
#endif
#ifdef CONFIG_SYS_CSPR1_EXT
set_ifc_cspr_ext(IFC_CS1, CONFIG_SYS_CSPR1_EXT);
#endif
#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1)
set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0);
set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1);
@ -61,6 +67,9 @@ void init_early_memctl_regs(void)
set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1);
#endif
#ifdef CONFIG_SYS_CSPR2_EXT
set_ifc_cspr_ext(IFC_CS2, CONFIG_SYS_CSPR2_EXT);
#endif
#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2)
set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0);
set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1);
@ -72,6 +81,9 @@ void init_early_memctl_regs(void)
set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2);
#endif
#ifdef CONFIG_SYS_CSPR3_EXT
set_ifc_cspr_ext(IFC_CS3, CONFIG_SYS_CSPR3_EXT);
#endif
#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3)
set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0);
set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1);

153
arch/powerpc/cpu/mpc8xxx/srio.c
View File

@ -95,126 +95,92 @@ void srio_init(void)
}
}
#ifdef CONFIG_SRIOBOOT_MASTER
void srio_boot_master(void)
#ifdef CONFIG_FSL_CORENET
void srio_boot_master(int port)
{
struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
/* set port accept-all */
out_be32((void *)&srio->impl.port[CONFIG_SRIOBOOT_MASTER_PORT].ptaacr,
out_be32((void *)&srio->impl.port[port - 1].ptaacr,
SRIO_PORT_ACCEPT_ALL);
debug("SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n",
CONFIG_SRIOBOOT_MASTER_PORT);
debug("SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n", port);
/* configure inbound window for slave's u-boot image */
debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1,
(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1,
CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwtar,
CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 >> 12);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwbar,
CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 >> 12);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwar,
(u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
(u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwtar,
CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12);
out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwbar,
CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 >> 12);
out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwar,
SRIO_IB_ATMU_AR
| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE));
| atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE));
/* configure inbound window for slave's u-boot image */
debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2,
(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2,
CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwtar,
CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2 >> 12);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwbar,
CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 >> 12);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwar,
(u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
(u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwtar,
CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12);
out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwbar,
CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 >> 12);
out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwar,
SRIO_IB_ATMU_AR
| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE));
| atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE));
/* configure inbound window for slave's ucode */
debug("SRIOBOOT - MASTER: Inbound window for slave's ucode; "
/* configure inbound window for slave's ucode and ENV */
debug("SRIOBOOT - MASTER: Inbound window for slave's ucode and ENV; "
"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
(u64)CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS,
(u64)CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS,
CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwtar,
CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS >> 12);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwbar,
CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS >> 12);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[2].riwar,
(u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
(u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwtar,
CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS >> 12);
out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwbar,
CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS >> 12);
out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwar,
SRIO_IB_ATMU_AR
| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE));
/* configure inbound window for slave's ENV */
debug("SRIOBOOT - MASTER: Inbound window for slave's ENV; "
"Local = 0x%llx, Siro = 0x%llx, Size = 0x%x\n",
CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS,
CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS,
CONFIG_SRIOBOOT_SLAVE_ENV_SIZE);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwtar,
CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS >> 12);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwbar,
CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS >> 12);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[3].riwar,
SRIO_IB_ATMU_AR
| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_ENV_SIZE));
| atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE));
}
#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF
void srio_boot_master_release_slave(void)
void srio_boot_master_release_slave(int port)
{
struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
u32 escsr;
debug("SRIOBOOT - MASTER: "
"Check the port status and release slave core ...\n");
escsr = in_be32((void *)&srio->lp_serial
.port[CONFIG_SRIOBOOT_MASTER_PORT].pescsr);
escsr = in_be32((void *)&srio->lp_serial.port[port - 1].pescsr);
if (escsr & 0x2) {
if (escsr & 0x10100) {
debug("SRIOBOOT - MASTER: Port [ %d ] is error.\n",
CONFIG_SRIOBOOT_MASTER_PORT);
port);
} else {
debug("SRIOBOOT - MASTER: "
"Port [ %d ] is ready, now release slave's core ...\n",
CONFIG_SRIOBOOT_MASTER_PORT);
"Port [ %d ] is ready, now release slave's core ...\n",
port);
/*
* configure outbound window
* with maintenance attribute to set slave's LCSBA1CSR
*/
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT]
out_be32((void *)&srio->atmu.port[port - 1]
.outbw[1].rowtar, 0);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT]
out_be32((void *)&srio->atmu.port[port - 1]
.outbw[1].rowtear, 0);
if (CONFIG_SRIOBOOT_MASTER_PORT)
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT]
if (port - 1)
out_be32((void *)&srio->atmu.port[port - 1]
.outbw[1].rowbar,
CONFIG_SYS_SRIO2_MEM_PHYS >> 12);
else
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT]
out_be32((void *)&srio->atmu.port[port - 1]
.outbw[1].rowbar,
CONFIG_SYS_SRIO1_MEM_PHYS >> 12);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT]
out_be32((void *)&srio->atmu.port[port - 1]
.outbw[1].rowar,
SRIO_OB_ATMU_AR_MAINT
| atmu_size_mask(SRIO_MAINT_WIN_SIZE));
@ -223,27 +189,22 @@ void srio_boot_master_release_slave(void)
* configure outbound window
* with R/W attribute to set slave's BRR
*/
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT]
out_be32((void *)&srio->atmu.port[port - 1]
.outbw[2].rowtar,
SRIO_LCSBA1CSR >> 9);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT]
out_be32((void *)&srio->atmu.port[port - 1]
.outbw[2].rowtear, 0);
if (CONFIG_SRIOBOOT_MASTER_PORT)
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT]
if (port - 1)
out_be32((void *)&srio->atmu.port[port - 1]
.outbw[2].rowbar,
(CONFIG_SYS_SRIO2_MEM_PHYS
+ SRIO_MAINT_WIN_SIZE) >> 12);
else
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT]
out_be32((void *)&srio->atmu.port[port - 1]
.outbw[2].rowbar,
(CONFIG_SYS_SRIO1_MEM_PHYS
+ SRIO_MAINT_WIN_SIZE) >> 12);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT]
out_be32((void *)&srio->atmu.port[port - 1]
.outbw[2].rowar,
SRIO_OB_ATMU_AR_RW
| atmu_size_mask(SRIO_RW_WIN_SIZE));
@ -252,7 +213,7 @@ void srio_boot_master_release_slave(void)
* Set the LCSBA1CSR register in slave
* by the maint-outbound window
*/
if (CONFIG_SRIOBOOT_MASTER_PORT) {
if (port - 1) {
out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
+ SRIO_LCSBA1CSR_OFFSET,
SRIO_LCSBA1CSR);
@ -266,8 +227,8 @@ void srio_boot_master_release_slave(void)
*/
out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
+ SRIO_MAINT_WIN_SIZE
+ CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET,
CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK);
+ CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET,
CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK);
} else {
out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
+ SRIO_LCSBA1CSR_OFFSET,
@ -282,15 +243,13 @@ void srio_boot_master_release_slave(void)
*/
out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
+ SRIO_MAINT_WIN_SIZE
+ CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET,
CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK);
+ CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET,
CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK);
}
debug("SRIOBOOT - MASTER: "
"Release slave successfully! Now the slave should start up!\n");
}
} else
debug("SRIOBOOT - MASTER: Port [ %d ] is not ready.\n",
CONFIG_SRIOBOOT_MASTER_PORT);
debug("SRIOBOOT - MASTER: Port [ %d ] is not ready.\n", port);
}
#endif
#endif

4
arch/powerpc/include/asm/config.h
View File

@ -29,6 +29,10 @@
#include <asm/config_mpc86xx.h>
#endif
#ifndef HWCONFIG_BUFFER_SIZE
#define HWCONFIG_BUFFER_SIZE 256
#endif
/* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */
#if defined(CONFIG_MPC8XXX_SPI) || defined(CONFIG_FSL_ESPI)
# ifndef CONFIG_HARD_SPI

133
arch/powerpc/include/asm/config_mpc85xx.h
View File

@ -37,6 +37,7 @@
#if defined(CONFIG_MPC8536)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
@ -54,12 +55,14 @@
#elif defined(CONFIG_MPC8544)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 10
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#elif defined(CONFIG_MPC8548)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 10
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
@ -113,6 +116,7 @@
#elif defined(CONFIG_MPC8572)
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_DDR_115
@ -191,33 +195,6 @@
#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
/* P1015 is single core version of P1024 */
#elif defined(CONFIG_P1015)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
/* P1016 is single core version of P1025 */
#elif defined(CONFIG_P1016)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
/* P1017 is single core version of P1023 */
#elif defined(CONFIG_P1017)
#define CONFIG_MAX_CPUS 1
@ -333,30 +310,7 @@
#define CONFIG_SYS_FSL_RMU
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_PPC_P2040)
#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 32
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#elif defined(CONFIG_PPC_P2041)
#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_NUM_LAWS 32
@ -380,6 +334,10 @@
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_ERRATUM_A004510
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_PPC_P3041)
#define CONFIG_MAX_CPUS 4
@ -399,47 +357,18 @@
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_ERRATUM_A004510
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_PPC_P3060)
#define CONFIG_MAX_CPUS 8
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_NUM_FMAN 2
#define CONFIG_SYS_NUM_FM1_DTSEC 4
#define CONFIG_SYS_NUM_FM2_DTSEC 4
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#elif defined(CONFIG_PPC_P4040)
#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#elif defined(CONFIG_PPC_P4080)
#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
#define CONFIG_MAX_CPUS 8
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
#define CONFIG_SYS_FSL_NUM_LAWS 32
@ -474,32 +403,11 @@
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_RMU
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#define CONFIG_SYS_FSL_ERRATUM_A004510
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
/* P5010 is single core version of P5020 */
#elif defined(CONFIG_PPC_P5010)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_FSL_SATA_V2
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 32
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#elif defined(CONFIG_PPC_P5020)
#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_NUM_LAWS 32
@ -521,6 +429,9 @@
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_ERRATUM_A004510
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
#elif defined(CONFIG_BSC9131)
#define CONFIG_MAX_CPUS 1

1
arch/powerpc/include/asm/fsl_ddr_dimm_params.h
View File

@ -43,6 +43,7 @@ typedef struct dimm_params_s {
/* DIMM timing parameters */
unsigned int mtb_ps; /* medium timebase ps, only for ddr3 */
unsigned int ftb_10th_ps; /* fine timebase, in 1/10 ps, only for ddr3 */
unsigned int tAA_ps; /* minimum CAS latency time, only for ddr3 */
unsigned int tFAW_ps; /* four active window delay, only for ddr3 */

8
arch/powerpc/include/asm/fsl_ddr_sdram.h
View File

@ -76,6 +76,13 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
#define FSL_DDR_PAGE_INTERLEAVING 0x1
#define FSL_DDR_BANK_INTERLEAVING 0x2
#define FSL_DDR_SUPERBANK_INTERLEAVING 0x3
#define FSL_DDR_3WAY_1KB_INTERLEAVING 0xA
#define FSL_DDR_3WAY_4KB_INTERLEAVING 0xC
#define FSL_DDR_3WAY_8KB_INTERLEAVING 0xD
/* placeholder for 4-way interleaving */
#define FSL_DDR_4WAY_1KB_INTERLEAVING 0x1A
#define FSL_DDR_4WAY_4KB_INTERLEAVING 0x1C
#define FSL_DDR_4WAY_8KB_INTERLEAVING 0x1D
/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
*/
@ -88,6 +95,7 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
#define SDRAM_CFG_DYN_PWR 0x00200000
#define SDRAM_CFG_DBW_MASK 0x00180000
#define SDRAM_CFG_32_BE 0x00080000
#define SDRAM_CFG_16_BE 0x00100000
#define SDRAM_CFG_8_BE 0x00040000

18
arch/powerpc/include/asm/fsl_ifc.h
View File

@ -783,12 +783,16 @@ extern void init_early_memctl_regs(void);
#define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR)
#define get_ifc_cspr_ext(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext))
#define get_ifc_cspr(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr))
#define get_ifc_csor_ext(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext))
#define get_ifc_csor(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor))
#define get_ifc_amask(i) (in_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask))
#define get_ifc_ftim(i, j) (in_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j]))
#define set_ifc_cspr_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v))
#define set_ifc_cspr(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v))
#define set_ifc_csor_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v))
#define set_ifc_csor(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v))
#define set_ifc_amask(i, v) (out_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v))
#define set_ifc_ftim(i, j, v) \
@ -909,22 +913,24 @@ struct fsl_ifc_gpcm {
*/
struct fsl_ifc {
u32 ifc_rev;
u32 res1[0x3];
u32 res1[0x2];
struct {
u32 cspr_ext;
u32 cspr;
u32 res2[0x2];
u32 res2;
} cspr_cs[FSL_IFC_BANK_COUNT];
u32 res3[0x18];
u32 res3[0x19];
struct {
u32 amask;
u32 res4[0x2];
} amask_cs[FSL_IFC_BANK_COUNT];
u32 res5[0x18];
u32 res5[0x17];
struct {
u32 csor_ext;
u32 csor;
u32 res6[0x2];
u32 res6;
} csor_cs[FSL_IFC_BANK_COUNT];
u32 res7[0x18];
u32 res7[0x19];
struct {
u32 ftim[4];
u32 res8[0x8];

13
arch/powerpc/include/asm/fsl_law.h
View File

@ -60,14 +60,19 @@ enum law_trgt_if {
LAW_TRGT_IF_DDR_1 = 0x10,
LAW_TRGT_IF_DDR_2 = 0x11, /* 2nd controller */
LAW_TRGT_IF_DDR_3 = 0x12,
LAW_TRGT_IF_DDR_4 = 0x13,
LAW_TRGT_IF_DDR_INTRLV = 0x14,
LAW_TRGT_IF_DDR_INTLV_34 = 0x15,
LAW_TRGT_IF_DDR_INTLV_123 = 0x17,
LAW_TRGT_IF_DDR_INTLV_1234 = 0x16,
LAW_TRGT_IF_BMAN = 0x18,
LAW_TRGT_IF_DCSR = 0x1d,
LAW_TRGT_IF_LBC = 0x1f,
LAW_TRGT_IF_QMAN = 0x3c,
};
#define LAW_TRGT_IF_DDR LAW_TRGT_IF_DDR_1
#define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC
#else
enum law_trgt_if {
LAW_TRGT_IF_PCI = 0x00,
@ -86,6 +91,12 @@ enum law_trgt_if {
LAW_TRGT_IF_DPAA_SWP_SRAM = 0x0e,
LAW_TRGT_IF_DDR = 0x0f,
LAW_TRGT_IF_DDR_2 = 0x16, /* 2nd controller */
/* place holder for 3-way and 4-way interleaving */
LAW_TRGT_IF_DDR_3,
LAW_TRGT_IF_DDR_4,
LAW_TRGT_IF_DDR_INTLV_34,
LAW_TRGT_IF_DDR_INTLV_123,
LAW_TRGT_IF_DDR_INTLV_1234,
};
#define LAW_TRGT_IF_DDR_1 LAW_TRGT_IF_DDR
#define LAW_TRGT_IF_PCI_1 LAW_TRGT_IF_PCI

1
arch/powerpc/include/asm/fsl_serdes.h
View File

@ -41,6 +41,7 @@ enum srds_prtcl {
SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3,
SGMII_FM2_DTSEC4,
SGMII_FM2_DTSEC5,
SGMII_TSEC1,
SGMII_TSEC2,
SGMII_TSEC3,

8
arch/powerpc/include/asm/fsl_srio.h
View File

@ -55,10 +55,8 @@ enum atmu_size {
#define atmu_size_bytes(x) (1ULL << ((x & 0x3f) + 1))
extern void srio_init(void);
#ifdef CONFIG_SRIOBOOT_MASTER
extern void srio_boot_master(void);
#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF
extern void srio_boot_master_release_slave(void);
#endif
#ifdef CONFIG_FSL_CORENET
extern void srio_boot_master(int port);
extern void srio_boot_master_release_slave(int port);
#endif
#endif

101
arch/powerpc/include/asm/immap_85xx.h
View File

@ -1729,6 +1729,7 @@ typedef struct ccsr_gur {
#define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000
#define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000
#define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000
#define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00000800
#define FSL_CORENET_NUM_DEVDISR 2
u8 res7[8];
u32 powmgtcsr; /* Power management status & control */
@ -1758,13 +1759,14 @@ typedef struct ccsr_gur {
#define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080
#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7
#define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000
#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
#define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c000000 /* bits 162..165 */
#define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c0000 /* bits 170..173 */
#define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000
#define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
#define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
#define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */
#if defined(CONFIG_PPC_P4080) || defined(CONFIG_PPC_P3060)
#ifdef CONFIG_PPC_P4080
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000
#define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000
#define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */
@ -1772,7 +1774,7 @@ typedef struct ccsr_gur {
#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000
#define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000
#endif
#if defined(CONFIG_PPC_P2040) || defined(CONFIG_PPC_P2041) \
#if defined(CONFIG_PPC_P2041) \
|| defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P5020)
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000
@ -1836,7 +1838,13 @@ typedef struct ccsr_gur {
u8 res31[184];
u32 sriopstecr; /* SRIO prescaler timer enable control */
u32 dcsrcr; /* DCSR Control register */
u8 res32[1784];
u8 res31a[56];
u32 tp_ityp[64]; /* Topology Initiator Type Register */
struct {
u32 upper;
u32 lower;
} tp_cluster[16]; /* Core Cluster n Topology Register */
u8 res32[1344];
u32 pmuxcr; /* Pin multiplexing control */
u8 res33[60];
u32 iovselsr; /* I/O voltage selection status */
@ -1849,6 +1857,18 @@ typedef struct ccsr_gur {
u8 res37[380];
} ccsr_gur_t;
#define TP_ITYP_AV 0x00000001 /* Initiator available */
#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
#define TP_ITYP_TYPE_OTHER 0x0
#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
#define TP_ITYP_TYPE_SC 0x2 /* StarCore DSP */
#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
#define FSL_CORENET_DCSR_SZ_MASK 0x00000003
#define FSL_CORENET_DCSR_SZ_4M 0x0
#define FSL_CORENET_DCSR_SZ_1G 0x3
@ -1890,6 +1910,73 @@ typedef struct ccsr_clk {
u8 res15[0x3dc];
} ccsr_clk_t;
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
typedef struct ccsr_rcpm {
u8 res_00[12];
u32 tph10sr0; /* Thread PH10 Status Register */
u8 res_10[12];
u32 tph10setr0; /* Thread PH10 Set Control Register */
u8 res_20[12];
u32 tph10clrr0; /* Thread PH10 Clear Control Register */
u8 res_30[12];
u32 tph10psr0; /* Thread PH10 Previous Status Register */
u8 res_40[12];
u32 twaitsr0; /* Thread Wait Status Register */
u8 res_50[96];
u32 pcph15sr; /* Physical Core PH15 Status Register */
u32 pcph15setr; /* Physical Core PH15 Set Control Register */
u32 pcph15clrr; /* Physical Core PH15 Clear Control Register */
u32 pcph15psr; /* Physical Core PH15 Prev Status Register */
u8 res_c0[16];
u32 pcph20sr; /* Physical Core PH20 Status Register */
u32 pcph20setr; /* Physical Core PH20 Set Control Register */
u32 pcph20clrr; /* Physical Core PH20 Clear Control Register */
u32 pcph20psr; /* Physical Core PH20 Prev Status Register */
u32 pcpw20sr; /* Physical Core PW20 Status Register */
u8 res_e0[12];
u32 pcph30sr; /* Physical Core PH30 Status Register */
u32 pcph30setr; /* Physical Core PH30 Set Control Register */
u32 pcph30clrr; /* Physical Core PH30 Clear Control Register */
u32 pcph30psr; /* Physical Core PH30 Prev Status Register */
u8 res_100[32];
u32 ippwrgatecr; /* IP Power Gating Control Register */
u8 res_124[12];
u32 powmgtcsr; /* Power Management Control & Status Reg */
u8 res_134[12];
u32 ippdexpcr[4]; /* IP Powerdown Exception Control Reg */
u8 res_150[12];
u32 tpmimr0; /* Thread PM Interrupt Mask Reg */
u8 res_160[12];
u32 tpmcimr0; /* Thread PM Crit Interrupt Mask Reg */
u8 res_170[12];
u32 tpmmcmr0; /* Thread PM Machine Check Interrupt Mask Reg */
u8 res_180[12];
u32 tpmnmimr0; /* Thread PM NMI Mask Reg */
u8 res_190[12];
u32 tmcpmaskcr0; /* Thread Machine Check Mask Control Reg */
u32 pctbenr; /* Physical Core Time Base Enable Reg */
u32 pctbclkselr; /* Physical Core Time Base Clock Select */
u32 tbclkdivr; /* Time Base Clock Divider Register */
u8 res_1ac[4];
u32 ttbhltcr[4]; /* Thread Time Base Halt Control Register */
u32 clpcl10sr; /* Cluster PCL10 Status Register */
u32 clpcl10setr; /* Cluster PCL30 Set Control Register */
u32 clpcl10clrr; /* Cluster PCL30 Clear Control Register */
u32 clpcl10psr; /* Cluster PCL30 Prev Status Register */
u32 cddslpsetr; /* Core Domain Deep Sleep Set Register */
u32 cddslpclrr; /* Core Domain Deep Sleep Clear Register */
u32 cdpwroksetr; /* Core Domain Power OK Set Register */
u32 cdpwrokclrr; /* Core Domain Power OK Clear Register */
u32 cdpwrensr; /* Core Domain Power Enable Status Register */
u32 cddslsr; /* Core Domain Deep Sleep Status Register */
u8 res_1e8[8];
u32 dslpcntcr[8]; /* Deep Sleep Counter Cfg Register */
u8 res_300[3568];
} ccsr_rcpm_t;
#define ctbenrl pctbenr
#else
typedef struct ccsr_rcpm {
u8 res1[4];
u32 cdozsrl; /* Core Doze Status */
@ -1926,6 +2013,7 @@ typedef struct ccsr_rcpm {
u32 ctbhltcrl; /* Core Time Base Halt Control */
u8 res18[0xf68];
} ccsr_rcpm_t;
#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
#else
typedef struct ccsr_gur {
@ -2259,8 +2347,7 @@ typedef struct ccsr_gur {
u8 res11a[76];
par_io_t qe_par_io[7];
u8 res11b[1600];
#elif defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
defined(CONFIG_P1021) || defined(CONFIG_P1025)
#elif defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
u8 res11a[12];
u32 iovselsr;
u8 res11b[60];
@ -2534,6 +2621,7 @@ struct ccsr_rman {
#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000
#define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x9000
#define CONFIG_SYS_MPC85xx_DDR3_OFFSET 0xA000
#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
@ -2544,6 +2632,7 @@ struct ccsr_rman {
#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000
#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000
#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000
@ -2652,6 +2741,8 @@ struct ccsr_rman {
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET)
#define CONFIG_SYS_MPC85xx_DDR2_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET)
#define CONFIG_SYS_MPC85xx_DDR3_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR3_OFFSET)
#define CONFIG_SYS_LBC_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
#define CONFIG_SYS_IFC_ADDR \

20
arch/powerpc/include/asm/io.h
View File

@ -162,7 +162,7 @@ static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
* is actually performed (i.e. the data has come back) before we start
* executing any following instructions.
*/
static inline u8 in_8(const volatile unsigned char __iomem *addr)
extern inline u8 in_8(const volatile unsigned char __iomem *addr)
{
u8 ret;
@ -173,7 +173,7 @@ static inline u8 in_8(const volatile unsigned char __iomem *addr)
return ret;
}
static inline void out_8(volatile unsigned char __iomem *addr, u8 val)
extern inline void out_8(volatile unsigned char __iomem *addr, u8 val)
{
__asm__ __volatile__("sync;\n"
"stb%U0%X0 %1,%0;\n"
@ -181,7 +181,7 @@ static inline void out_8(volatile unsigned char __iomem *addr, u8 val)
: "r" (val));
}
static inline u16 in_le16(const volatile unsigned short __iomem *addr)
extern inline u16 in_le16(const volatile unsigned short __iomem *addr)
{
u16 ret;
@ -192,7 +192,7 @@ static inline u16 in_le16(const volatile unsigned short __iomem *addr)
return ret;
}
static inline u16 in_be16(const volatile unsigned short __iomem *addr)
extern inline u16 in_be16(const volatile unsigned short __iomem *addr)
{
u16 ret;
@ -202,18 +202,18 @@ static inline u16 in_be16(const volatile unsigned short __iomem *addr)
return ret;
}
static inline void out_le16(volatile unsigned short __iomem *addr, u16 val)
extern inline void out_le16(volatile unsigned short __iomem *addr, u16 val)
{
__asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) :
"r" (val), "r" (addr));
}
static inline void out_be16(volatile unsigned short __iomem *addr, u16 val)
extern inline void out_be16(volatile unsigned short __iomem *addr, u16 val)
{
__asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
}
static inline u32 in_le32(const volatile unsigned __iomem *addr)
extern inline u32 in_le32(const volatile unsigned __iomem *addr)
{
u32 ret;
@ -224,7 +224,7 @@ static inline u32 in_le32(const volatile unsigned __iomem *addr)
return ret;
}
static inline u32 in_be32(const volatile unsigned __iomem *addr)
extern inline u32 in_be32(const volatile unsigned __iomem *addr)
{
u32 ret;
@ -234,13 +234,13 @@ static inline u32 in_be32(const volatile unsigned __iomem *addr)
return ret;
}
static inline void out_le32(volatile unsigned __iomem *addr, u32 val)
extern inline void out_le32(volatile unsigned __iomem *addr, u32 val)
{
__asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) :
"r" (val), "r" (addr));
}
static inline void out_be32(volatile unsigned __iomem *addr, u32 val)
extern inline void out_be32(volatile unsigned __iomem *addr, u32 val)
{
__asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
}

4
arch/powerpc/include/asm/mmu.h
View File

@ -475,6 +475,10 @@ extern void print_bats(void);
#define BOOKE_PAGESZ_256GB 14
#define BOOKE_PAGESZ_1TB 15
#define TLBIVAX_ALL 4
#define TLBIVAX_TLB0 0
#define TLBIVAX_TLB1 8
#ifdef CONFIG_E500
#ifndef __ASSEMBLY__
extern void set_tlb(u8 tlb, u32 epn, u64 rpn,

6
arch/powerpc/include/asm/mp.h
View File

@ -28,4 +28,10 @@ void cpu_mp_lmb_reserve(struct lmb *lmb);
u32 determine_mp_bootpg(void);
int is_core_disabled(int nr);
#ifdef CONFIG_E6500
#define thread_to_core(x) (x >> 1)
#else
#define thread_to_core(x) (x)
#endif
#endif

8
arch/powerpc/include/asm/processor.h
View File

@ -486,11 +486,13 @@
#define SPRN_L2CFG0 0x207 /* L2 Cache Configuration Register 0 */
#define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */
#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
#define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */
#define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */
#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
#define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */
#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
#define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */
#define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */
#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
@ -513,6 +515,7 @@
#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */
#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */
#define TLBnCFG_NENTRY_MASK 0x00000fff
#define SPRN_TLB0PS 0x158 /* TLB 0 Page Size Register */
#define SPRN_TLB1PS 0x159 /* TLB 1 Page Size Register */
#define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */
@ -948,6 +951,7 @@
#define PVR_VER_E500_V2 0x8021
#define PVR_VER_E500MC 0x8023
#define PVR_VER_E5500 0x8024
#define PVR_VER_E6500 0x8040
#define PVR_86xx 0x80040000
@ -1075,8 +1079,6 @@
#define SVR_P1012 0x80E501
#define SVR_P1013 0x80E700
#define SVR_P1014 0x80F101
#define SVR_P1015 0x80E502
#define SVR_P1016 0x80E503
#define SVR_P1017 0x80F700
#define SVR_P1020 0x80E400
#define SVR_P1021 0x80E401
@ -1089,7 +1091,6 @@
#define SVR_P2040 0x821000
#define SVR_P2041 0x821001
#define SVR_P3041 0x821103
#define SVR_P3060 0x820002
#define SVR_P4040 0x820100
#define SVR_P4080 0x820000
#define SVR_P5010 0x822100
@ -1158,6 +1159,7 @@ struct cpu_type {
};
struct cpu_type *identify_cpu(u32 ver);
int fixup_cpu(void);
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
#define CPU_TYPE_ENTRY(n, v, nc) \

18
arch/powerpc/lib/board.c
View File

@ -345,6 +345,13 @@ ulong get_effective_memsize(void)
#endif
}
int __fixup_cpu(void)
{
return 0;
}
int fixup_cpu(void) __attribute__((weak, alias("__fixup_cpu")));
/*
* This is the first part of the initialization sequence that is
* implemented in C, but still running from ROM.
@ -521,9 +528,8 @@ void board_init_f(ulong bootflag)
addr_sp -= 16;
addr_sp &= ~0xF;
s = (ulong *) addr_sp;
*s-- = 0;
*s-- = 0;
addr_sp = (ulong) s;
*s = 0; /* Terminate back chain */
*++s = 0; /* NULL return address */
debug("Stack Pointer at: %08lx\n", addr_sp);
/*
@ -647,6 +653,12 @@ void board_init_r(gd_t *id, ulong dest_addr)
* We need to update it to point to the same CPU entry in RAM.
*/
gd->cpu += dest_addr - CONFIG_SYS_MONITOR_BASE;
/*
* If we didn't know the cpu mask & # cores, we can save them of
* now rather than 'computing' them constantly
*/
fixup_cpu();
#endif
#ifdef CONFIG_SYS_EXTRA_ENV_RELOC

2
board/freescale/common/Makefile
View File

@ -51,14 +51,12 @@ COBJS-$(CONFIG_MPC8572DS) += ics307_clk.o
COBJS-$(CONFIG_P1022DS) += ics307_clk.o
COBJS-$(CONFIG_P2020DS) += ics307_clk.o
COBJS-$(CONFIG_P3041DS) += ics307_clk.o
COBJS-$(CONFIG_P3060QDS) += ics307_clk.o
COBJS-$(CONFIG_P4080DS) += ics307_clk.o
COBJS-$(CONFIG_P5020DS) += ics307_clk.o
# deal with common files for P-series corenet based devices
SUBLIB-$(CONFIG_P2041RDB) += p_corenet/libp_corenet.o
SUBLIB-$(CONFIG_P3041DS) += p_corenet/libp_corenet.o
SUBLIB-$(CONFIG_P3060QDS) += p_corenet/libp_corenet.o
SUBLIB-$(CONFIG_P4080DS) += p_corenet/libp_corenet.o
SUBLIB-$(CONFIG_P5020DS) += p_corenet/libp_corenet.o

31
board/freescale/common/fman.c
View File

@ -25,6 +25,9 @@
#include <libfdt_env.h>
#include <fdt_support.h>
#include <fm_eth.h>
#include <asm/fsl_serdes.h>
/*
* Given the following ...
*
@ -67,3 +70,31 @@ int fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr,
return fdt_setprop(fdt, offset, "phy-handle", &ph, sizeof(ph));
}
/*
* Return the SerDes device enum for a given Fman port
*
* This function just maps the fm_port namespace to the srds_prtcl namespace.
*/
enum srds_prtcl serdes_device_from_fm_port(enum fm_port port)
{
static const enum srds_prtcl srds_table[] = {
[FM1_DTSEC1] = SGMII_FM1_DTSEC1,
[FM1_DTSEC2] = SGMII_FM1_DTSEC2,
[FM1_DTSEC3] = SGMII_FM1_DTSEC3,
[FM1_DTSEC4] = SGMII_FM1_DTSEC4,
[FM1_DTSEC5] = SGMII_FM1_DTSEC5,
[FM1_10GEC1] = XAUI_FM1,
[FM2_DTSEC1] = SGMII_FM2_DTSEC1,
[FM2_DTSEC2] = SGMII_FM2_DTSEC2,
[FM2_DTSEC3] = SGMII_FM2_DTSEC3,
[FM2_DTSEC4] = SGMII_FM2_DTSEC4,
[FM2_DTSEC5] = SGMII_FM2_DTSEC5,
[FM2_10GEC1] = XAUI_FM2,
};
if ((port < FM1_DTSEC1) || (port > FM2_10GEC1))
return NONE;
else
return srds_table[port];
}

2
board/freescale/common/fman.h
View File

@ -23,4 +23,6 @@
int fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr,
const char *alias);
enum srds_prtcl serdes_device_from_fm_port(enum fm_port port);
#endif

13
board/freescale/common/p_corenet/law.c
View File

@ -48,19 +48,6 @@ struct law_entry law_table[] = {
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#endif
#ifdef CONFIG_SRIOBOOT_SLAVE
#if defined(CONFIG_SRIOBOOT_SLAVE_PORT0)
SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
#elif defined(CONFIG_SRIOBOOT_SLAVE_PORT1)
SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
#endif
#endif
};
int num_law_entries = ARRAY_SIZE(law_table);

18
board/freescale/common/p_corenet/tlb.c
View File

@ -66,13 +66,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
#elif defined(CONFIG_SRIOBOOT_SLAVE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* SRIOBOOT-SLAVE. When slave boot, the address of the
* SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
* space is at 0xfff00000, it covered the 0xfffff000.
*/
SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_SLAVE_ADDR,
CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
#else
@ -147,13 +147,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 16, BOOKE_PAGESZ_1M, 1),
#endif
#ifdef CONFIG_SRIOBOOT_SLAVE
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
/*
* SRIOBOOT-SLAVE. 1M space from 0xffe00000 for fetching ucode
* and ENV from master
* SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
* fetching ucode and ENV from master
*/
SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR,
CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
0, 17, BOOKE_PAGESZ_1M, 1),
#endif

59
board/freescale/corenet_ds/eth_p4080.c
View File

@ -68,6 +68,15 @@ static char *mdio_names[16] = {
NULL, NULL, NULL,
};
/*
* Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
* that the mapping must be determined dynamically, or that the lane maps to
* something other than a board slot.
*/
static u8 lane_to_slot[] = {
1, 1, 2, 2, 3, 3, 3, 3, 6, 6, 4, 4, 4, 4, 5, 5, 5, 5
};
static char *p4080ds_mdio_name_for_muxval(u32 muxval)
{
return mdio_names[(muxval & EMI_MASK) >> 28];
@ -290,15 +299,6 @@ void fdt_fixup_board_enet(void *fdt)
}
}
enum board_slots {
SLOT1 = 1,
SLOT2,
SLOT3,
SLOT4,
SLOT5,
SLOT6,
};
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FMAN_ENET
@ -307,27 +307,6 @@ int board_eth_init(bd_t *bis)
struct fsl_pq_mdio_info dtsec_mdio_info;
struct tgec_mdio_info tgec_mdio_info;
u8 lane_to_slot[] = {
SLOT1, /* 0 - Bank 1:A */
SLOT1, /* 1 - Bank 1:B */
SLOT2, /* 2 - Bank 1:C */
SLOT2, /* 3 - Bank 1:D */
SLOT3, /* 4 - Bank 1:E */
SLOT3, /* 5 - Bank 1:F */
SLOT3, /* 6 - Bank 1:G */
SLOT3, /* 7 - Bank 1:H */
SLOT6, /* 8 - Bank 1:I */
SLOT6, /* 9 - Bank 1:J */
SLOT4, /* 10 - Bank 2:A */
SLOT4, /* 11 - Bank 2:B */
SLOT4, /* 12 - Bank 2:C */
SLOT4, /* 13 - Bank 2:D */
SLOT5, /* 14 - Bank 3:A */
SLOT5, /* 15 - Bank 3:B */
SLOT5, /* 16 - Bank 3:C */
SLOT5, /* 17 - Bank 3:D */
};
/* Initialize the mdio_mux array so we can recognize empty elements */
for (i = 0; i < NUM_FM_PORTS; i++)
mdio_mux[i] = EMI_NONE;
@ -380,17 +359,17 @@ int board_eth_init(bd_t *bis)
break;
slot = lane_to_slot[lane];
switch (slot) {
case SLOT3:
case 3:
mdio_mux[i] = EMI1_SLOT3;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
case SLOT4:
case 4:
mdio_mux[i] = EMI1_SLOT4;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
case SLOT5:
case 5:
mdio_mux[i] = EMI1_SLOT5;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
@ -417,12 +396,12 @@ int board_eth_init(bd_t *bis)
break;
slot = lane_to_slot[lane];
switch (slot) {
case SLOT4:
case 4:
mdio_mux[i] = EMI2_SLOT4;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
case SLOT5:
case 5:
mdio_mux[i] = EMI2_SLOT5;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
@ -444,17 +423,17 @@ int board_eth_init(bd_t *bis)
break;
slot = lane_to_slot[lane];
switch (slot) {
case SLOT3:
case 3:
mdio_mux[i] = EMI1_SLOT3;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
case SLOT4:
case 4:
mdio_mux[i] = EMI1_SLOT4;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
case SLOT5:
case 5:
mdio_mux[i] = EMI1_SLOT5;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
@ -481,12 +460,12 @@ int board_eth_init(bd_t *bis)
break;
slot = lane_to_slot[lane];
switch (slot) {
case SLOT4:
case 4:
mdio_mux[i] = EMI2_SLOT4;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
case SLOT5:
case 5:
mdio_mux[i] = EMI2_SLOT5;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));

51
board/freescale/corenet_ds/pbi.cfg 100644
View File

@ -0,0 +1,51 @@
#
# Copyright 2012 Freescale Semiconductor, Inc.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
# MA 02110-1301 USA
#
# Refer docs/README.pblimage for more details about how-to configure
# and create PBL boot image
#
#PBI commands
#Initialize CPC1 as 1MB SRAM
09010000 00200400
09138000 00000000
091380c0 00000100
09010100 00000000
09010104 fff0000b
09010f00 08000000
09010000 80000000
#Configure LAW for CPC1
09000d00 00000000
09000d04 fff00000
09000d08 81000013
09000010 00000000
09000014 ff000000
09000018 81000000
#Initialize eSPI controller, default configuration is slow for eSPI to
#load data, this configuration comes from u-boot eSPI driver.
09110000 80000403
09110020 2d170008
09110024 00100008
09110028 00100008
0911002c 00100008
#Flush PBL data
09138000 00000000
091380c0 00000000

11
board/freescale/corenet_ds/rcw_p3041ds.cfg 100644
View File

@ -0,0 +1,11 @@
#
# Default RCW for P3041DS.
#
#PBL preamble and RCW header
aa55aa55 010e0100
#64 bytes RCW data
12600000 00000000 241C0000 00000000
D8984A01 03002000 58000000 41000000
00000000 00000000 00000000 10070000
00000000 00000000 00000000 00000000

11
board/freescale/corenet_ds/rcw_p4080ds.cfg 100644
View File

@ -0,0 +1,11 @@
#
# Default RCW for P4080DS.
#
#PBL preamble and RCW header
aa55aa55 010e0100
#64 bytes RCW data
105a0000 00000000 1e1e181e 0000cccc
58400000 3c3c2000 58000000 e1000000
00000000 00000000 00000000 008b6000
00000000 00000000 00000000 00000000

11
board/freescale/corenet_ds/rcw_p5020ds.cfg 100644
View File

@ -0,0 +1,11 @@
#
# Default RCW for P5020DS.
#
#PBL preamble and RCW header
aa55aa55 010e0100
#64 bytes RCW data
0C540000 00000000 1E120000 00000000
D8984A01 03002000 58000000 41000000
00000000 00000000 00000000 10070000
00000000 00000000 00000000 00000000

6
board/freescale/mpc8540ads/mpc8540ads.c
View File

@ -87,10 +87,10 @@ local_bus_init(void)
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {
lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000; /* DLL Bypass */
lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */
} else if (lbc_hz >= 133) {
lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
} else {
/*
@ -105,7 +105,7 @@ local_bus_init(void)
lbc->lcrr = 0x10000004;
}
lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
udelay(200);
/*

6
board/freescale/mpc8541cds/mpc8541cds.c
View File

@ -269,13 +269,13 @@ local_bus_init(void)
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {
lbc->lcrr |= 0x80000000; /* DLL Bypass */
lbc->lcrr |= LCRR_DBYP; /* DLL Bypass */
} else if (lbc_hz >= 133) {
lbc->lcrr &= (~0x80000000); /* DLL Enabled */
lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */
} else {
lbc->lcrr &= (~0x80000000); /* DLL Enabled */
lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */
udelay(200);
/*

6
board/freescale/mpc8555cds/mpc8555cds.c
View File

@ -267,13 +267,13 @@ local_bus_init(void)
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {
lbc->lcrr |= 0x80000000; /* DLL Bypass */
lbc->lcrr |= LCRR_DBYP; /* DLL Bypass */
} else if (lbc_hz >= 133) {
lbc->lcrr &= (~0x80000000); /* DLL Enabled */
lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */
} else {
lbc->lcrr &= (~0x80000000); /* DLL Enabled */
lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */
udelay(200);
/*

6
board/freescale/mpc8560ads/mpc8560ads.c
View File

@ -292,10 +292,10 @@ local_bus_init(void)
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {
lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000; /* DLL Bypass */
lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */
} else if (lbc_hz >= 133) {
lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
} else {
/*
@ -310,7 +310,7 @@ local_bus_init(void)
lbc->lcrr = 0x10000004;
}
lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000);/* DLL Enabled */
lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP);/* DLL Enabled */
udelay(200);
/*

7
board/freescale/p1010rdb/ddr.c
View File

@ -147,10 +147,11 @@ phys_size_t fixed_sdram(void)
cpu = gd->cpu;
/* P1014 and it's derivatives support max 16bit DDR width */
if (cpu->soc_ver == SVR_P1014) {
ddr_cfg_regs.ddr_sdram_cfg &= ~SDRAM_CFG_DBW_MASK;
ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_16_BE;
ddr_cfg_regs.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS >> 1;
ddr_cfg_regs.ddr_sdram_cfg &= ~0x00180000;
ddr_cfg_regs.ddr_sdram_cfg |= 0x001080000;
/* divide SA and EA by two and then mask the rest so we don't
* write to reserved fields */
ddr_cfg_regs.cs[0].bnds = (CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff;
}
ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;

2
board/freescale/p1_p2_rdb_pc/law.c
View File

@ -25,12 +25,10 @@
#include <asm/mmu.h>
struct law_entry law_table[] = {
#ifndef CONFIG_NAND_SPL
SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PMC_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
#ifdef CONFIG_VSC7385_ENET
SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#endif
#endif
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
#ifdef CONFIG_SYS_NAND_BASE_PHYS

54
board/freescale/p3060qds/Makefile
View File

@ -1,54 +0,0 @@
#
# Copyright 2011 Freescale Semiconductor, Inc.
# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
COBJS-y += ddr.o
COBJS-y += eth.o
COBJS-y += fixed_ddr.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS))
clean:
rm -f $(OBJS) $(SOBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

110
board/freescale/p3060qds/README
View File

@ -1,110 +0,0 @@
Overview
=========
The P3060QDS is a Freescale reference board that hosts the six-core P3060 SOC.
The P3060 Processor combines six e500mc Power Architecture processor
cores(1.2GHz) with high-performance datapath acceleration
architecture(DPAA), CoreNet fabric infrastructure, as well as network
and peripheral bus interfaces required for networking, telecom/datacom,
wireless infrastructure, and military/aerospace applications.
P3060QDS Board Specifications:
==============================
Memory subsystem:
* 2G Bytes UDIMM DDR3(64bit bus) with ECC on
* 128M Bytes NOR flash single-chip memory
* 16M Bytes SPI flash
* 8K Bytes AT24C64 I2C EEPROM for RCW
Ethernet(Default SERDES 0x19):
* FM1-dTSEC1: connected to RGMII PHY1 (Vitesse VSC8641 on board,Bottom of dual RJ45)
* FM1-dTSEC2: connected to RGMII PHY2 (Vitesse VSC8641 on board,Top of dual RJ45)
* FM1-dTSEC3: connected to SGMII PHY (Vitesse VSC8234 port1 in slot1)
* FM1-dTSEC4: connected to SGMII PHY (Vitesse VSC8234 port3 in slot1)
* FM2-dTSEC1: connected to SGMII PHY (Vitesse VSC8234 port0 in slot2)
* FM2-dTSEC2: connected to SGMII PHY (Vitesse VSC8234 port2 in slot2)
* FM2-dTSEC3: connected to SGMII PHY (Vitesse VSC8234 port0 in slot1)
* FM2-dTSEC4: connected to SGMII PHY (Vitesse VSC8234 port2 in slot1)
PCIe:
* PCIe1: Lanes A, B, C and D of Bank1 are connected to one x4 PCIe SLOT4
* PCIe2: Lanes E, F, G and H of Bank1 are connected to one x4 PCIe SLOT3
RapidIO:
* sRIO1: Lanes E, F, G and H of Bank1 are connected to sRIO1 (SLOT3)
* sRIO2: Lanes A, B, C and D of Bank1 are connected to sRIO2 (SLOT4)
USB:
* USB1: connected via an external ULPI PHY SMC3315 to a TYPE-A interface
* USB2: connected via an external ULPI PHY SMC3315 to a TYPE-AB interface
I2C:
* I2C1_CH0: EEPROM AT24C64(0x50) RCW, AT24C02(0x51) DDR SPD,
AT24C02(0x53) DDR SPD, AT24C02(0x57) SystemID, RTC DS3232(0x68)
* I2C1_CH1: 1588 RiserCard(0x55), HSLB Testport, TempMon
ADT7461(0x4C), SerDesMux DS64MB201(0x51/59/5C/5D)
* I2C1_CH2: VDD/GVDD/GIDD ZL6100 (0x21/0x22/0x23/0x24/0x40)
* I2C1_CH3: OCM CFG AT24C02(0x55), OCM IPL AT24C64(0x56)
* I2C1_CH4: PCIe SLOT1
* I2C1_CH5: PCIe SLOT2
* I2C1_CH6: PCIe SLOT3
* I2C1_CH7: PCIe SLOT4
* I2C2: NULL
* I2C3: NULL
UART:
* Supports two UARTs up to 115200 bps for console
Boot from NOR flash
===================
1. Build image
export ARCH=powerpc
export CROSS_COMPILE=/your_path/gcc-4.5.xx-eglibc-2.11.xx/powerpc-linux-gnu/bin/powerpc-linux-gnu-
make P3060QDS_config
make
2. Program image
=> tftp 1000000 u-boot.bin
=> protect off all
=> erase eff80000 efffffff
=> cp.b 1000000 eff80000 80000
3. Program RCW
=> tftp 1000000 rcw.bin
=> protect off all
=> erase e8000000 e801ffff
=> cp.b 1000000 e8000000 50
4. Program FMAN Firmware ucode
=> tftp 1000000 ucode.bin
=> protect off all
=> erase ef000000 ef0fffff
=> cp.b 1000000 ef000000 2000
5. Change DIP-switch
RCW Location: SW1[1-5] = 01101 (eLBC 16bit NOR flash)
Note: 1 stands for 'on', 0 stands for 'off'
Using the Device Tree Source File
=================================
To create the DTB (Device Tree Binary) image file, use a command
similar to this:
dtc -O dtb -b 0 -p 1024 p3060qds.dts > p3060qds.dtb
Or use the following command:
{linux-2.6}/make p3060qds.dtb ARCH=powerpc
then the dtb file will be generated under the following directory:
{linux-2.6}/arch/powerpc/boot/p3060qds.dtb
Booting Linux
=============
Place a linux uImage in the TFTP disk area.
tftp 1000000 uImage
tftp 2000000 rootfs.ext2.gz.uboot
tftp 3000000 p3060rdb.dtb
bootm 1000000 2000000 3000000

248
board/freescale/p3060qds/ddr.c
View File

@ -1,248 +0,0 @@
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*/
#include <common.h>
#include <i2c.h>
#include <hwconfig.h>
#include <asm/mmu.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
#include "p3060qds.h"
/*
* Fixed sdram init -- doesn't use serial presence detect.
*/
phys_size_t fixed_sdram(void)
{
int i;
char buf[32];
fsl_ddr_cfg_regs_t ddr_cfg_regs;
phys_size_t ddr_size;
unsigned int lawbar1_target_id;
ulong ddr_freq, ddr_freq_mhz;
ddr_freq = get_ddr_freq(0);
ddr_freq_mhz = ddr_freq / 1000000;
printf("Configuring DDR for %s MT/s data rate\n",
strmhz(buf, ddr_freq));
for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
(ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
memcpy(&ddr_cfg_regs,
fixed_ddr_parm_0[i].ddr_settings,
sizeof(ddr_cfg_regs));
break;
}
}
if (fixed_ddr_parm_0[i].max_freq == 0)
panic("Unsupported DDR data rate %s MT/s data rate\n",
strmhz(buf, ddr_freq));
ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
/*
* setup laws for DDR. If not interleaving, presuming half memory on
* DDR1 and the other half on DDR2
*/
if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) {
if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
ddr_size,
LAW_TRGT_IF_DDR_INTRLV) < 0) {
printf("ERROR setting Local Access Windows for DDR\n");
return 0;
}
} else {
lawbar1_target_id = LAW_TRGT_IF_DDR_1;
if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
ddr_size,
lawbar1_target_id) < 0) {
printf("ERROR setting Local Access Windows for DDR\n");
return 0;
}
}
return ddr_size;
}
struct board_specific_params {
u32 n_ranks;
u32 datarate_mhz_high;
u32 clk_adjust;
u32 wrlvl_start;
u32 cpo;
u32 write_data_delay;
u32 force_2T;
};
/*
* This table contains all valid speeds we want to override with board
* specific parameters. datarate_mhz_high values need to be in ascending order
* for each n_ranks group.
*/
static const struct board_specific_params udimm[] = {
/*
* memory controller 0
* num| hi| clk| wrlvl | cpo |wrdata|2T
* ranks| mhz|adjst| start | |delay |
*/
{4, 850, 4, 6, 0xff, 2, 0},
{4, 950, 5, 7, 0xff, 2, 0},
{4, 1050, 5, 8, 0xff, 2, 0},
{4, 1250, 5, 10, 0xff, 2, 0},
{4, 1350, 5, 11, 0xff, 2, 0},
{4, 1666, 5, 12, 0xff, 2, 0},
{2, 850, 5, 6, 0xff, 2, 0},
{2, 950, 5, 7, 0xff, 2, 0},
{2, 1250, 4, 6, 0xff, 2, 0},
{2, 1350, 5, 7, 0xff, 2, 0},
{2, 1666, 5, 8, 0xff, 2, 0},
{1, 850, 4, 5, 0xff, 2, 0},
{1, 950, 4, 7, 0xff, 2, 0},
{1, 1666, 4, 8, 0xff, 2, 0},
{}
};
static const struct board_specific_params rdimm[] = {
/*
* memory controller 0
* num| hi| clk| wrlvl | cpo |wrdata|2T
* ranks| mhz|adjst| start | |delay |
*/
{4, 850, 4, 6, 0xff, 2, 0},
{4, 950, 5, 7, 0xff, 2, 0},
{4, 1050, 5, 8, 0xff, 2, 0},
{4, 1250, 5, 10, 0xff, 2, 0},
{4, 1350, 5, 11, 0xff, 2, 0},
{4, 1666, 5, 12, 0xff, 2, 0},
{2, 850, 4, 6, 0xff, 2, 0},
{2, 1050, 4, 7, 0xff, 2, 0},
{2, 1666, 4, 8, 0xff, 2, 0},
{1, 850, 4, 5, 0xff, 2, 0},
{1, 950, 4, 7, 0xff, 2, 0},
{1, 1666, 4, 8, 0xff, 2, 0},
{}
};
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
const struct board_specific_params *pbsp, *pbsp_highest = NULL;
ulong ddr_freq;
if (ctrl_num) {
printf("Wrong parameter for controller number %d", ctrl_num);
return;
}
if (!pdimm->n_ranks)
return;
if (popts->registered_dimm_en)
pbsp = rdimm;
else
pbsp = udimm;
/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.
*/
ddr_freq = get_ddr_freq(0) / 1000000;
while (pbsp->datarate_mhz_high) {
if (pbsp->n_ranks == pdimm->n_ranks) {
if (ddr_freq <= pbsp->datarate_mhz_high) {
popts->cpo_override = pbsp->cpo;
popts->write_data_delay =
pbsp->write_data_delay;
popts->clk_adjust = pbsp->clk_adjust;
popts->wrlvl_start = pbsp->wrlvl_start;
popts->twoT_en = pbsp->force_2T;
goto found;
}
pbsp_highest = pbsp;
}
pbsp++;
}
if (pbsp_highest) {
printf("Error: board specific timing not found "
"for data rate %lu MT/s!\n"
"Trying to use the highest speed (%u) parameters\n",
ddr_freq, pbsp_highest->datarate_mhz_high);
popts->cpo_override = pbsp_highest->cpo;
popts->write_data_delay = pbsp_highest->write_data_delay;
popts->clk_adjust = pbsp_highest->clk_adjust;
popts->wrlvl_start = pbsp_highest->wrlvl_start;
popts->twoT_en = pbsp_highest->force_2T;
} else {
panic("DIMM is not supported by this board");
}
found:
/*
* The datasheet of HMT125U7BFR8C-H9 blocks CL=7 as reservered.
* However SPD still claims CL=7 is supported. Extensive tests
* confirmed this board cannot work stably with CL=7 with this
* particular DIMM.
*/
if (ddr_freq >= 800 && ddr_freq < 1066 && \
!strncmp(pdimm[0].mpart, "HMT125U7BFR8C-H9", 16)) {
popts->cas_latency_override = 1;
popts->cas_latency_override_value = 8;
debug("Override CL to 8\n");
}
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
*/
popts->half_strength_driver_enable = 0;
/*
* Write leveling override
*/
popts->wrlvl_override = 1;
popts->wrlvl_sample = 0xf;
/*
* Rtt and Rtt_WR override
*/
popts->rtt_override = 0;
/* Enable ZQ calibration */
popts->zq_en = 1;
/* DHC_EN =1, ODT = 60 Ohm */
popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
}
phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
puts("Initializing....");
if (fsl_use_spd()) {
puts("using SPD\n");
dram_size = fsl_ddr_sdram();
} else {
puts("using fixed parameters\n");
dram_size = fixed_sdram();
}
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
debug(" DDR: ");
return dram_size;
}

482
board/freescale/p3060qds/eth.c
View File

@ -1,482 +0,0 @@
/*
* Copyright 2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <netdev.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <malloc.h>
#include <fm_eth.h>
#include <fsl_mdio.h>
#include <miiphy.h>
#include <phy.h>
#include <asm/fsl_dtsec.h>
#include "../common/qixis.h"
#include "../common/fman.h"
#include "p3060qds_qixis.h"
#define EMI_NONE 0xffffffff
#define EMI1_RGMII1 0
#define EMI1_SLOT1 1
#define EMI1_SLOT2 2
#define EMI1_SLOT3 3
#define EMI1_RGMII2 4
static int mdio_mux[NUM_FM_PORTS];
static char *mdio_names[5] = {
"P3060QDS_MDIO0",
"P3060QDS_MDIO1",
"P3060QDS_MDIO2",
"P3060QDS_MDIO3",
"P3060QDS_MDIO4",
};
/*
* Mapping of all 18 SERDES lanes to board slots.
* A value of '0' here means that the mapping must be determined
* dynamically, Lane 8/9/16/17 map to Slot1 or Aurora debug
*/
static u8 lane_to_slot[] = {
4, 4, 4, 4, 3, 3, 3, 3, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0
};
static char *p3060qds_mdio_name_for_muxval(u32 muxval)
{
return mdio_names[muxval];
}
struct mii_dev *mii_dev_for_muxval(u32 muxval)
{
struct mii_dev *bus;
char *name = p3060qds_mdio_name_for_muxval(muxval);
if (!name) {
printf("No bus for muxval %x\n", muxval);
return NULL;
}
bus = miiphy_get_dev_by_name(name);
if (!bus) {
printf("No bus by name %s\n", name);
return NULL;
}
return bus;
}
struct p3060qds_mdio {
u32 muxval;
struct mii_dev *realbus;
};
static void p3060qds_mux_mdio(u32 muxval)
{
u8 brdcfg4;
brdcfg4 = QIXIS_READ(brdcfg[4]);
brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
brdcfg4 |= (muxval << 4);
QIXIS_WRITE(brdcfg[4], brdcfg4);
}
static int p3060qds_mdio_read(struct mii_dev *bus, int addr, int devad,
int regnum)
{
struct p3060qds_mdio *priv = bus->priv;
p3060qds_mux_mdio(priv->muxval);
return priv->realbus->read(priv->realbus, addr, devad, regnum);
}
static int p3060qds_mdio_write(struct mii_dev *bus, int addr, int devad,
int regnum, u16 value)
{
struct p3060qds_mdio *priv = bus->priv;
p3060qds_mux_mdio(priv->muxval);
return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
}
static int p3060qds_mdio_reset(struct mii_dev *bus)
{
struct p3060qds_mdio *priv = bus->priv;
return priv->realbus->reset(priv->realbus);
}
static int p3060qds_mdio_init(char *realbusname, u32 muxval)
{
struct p3060qds_mdio *pmdio;
struct mii_dev *bus = mdio_alloc();
if (!bus) {
printf("Failed to allocate P3060QDS MDIO bus\n");
return -1;
}
pmdio = malloc(sizeof(*pmdio));
if (!pmdio) {
printf("Failed to allocate P3060QDS private data\n");
free(bus);
return -1;
}
bus->read = p3060qds_mdio_read;
bus->write = p3060qds_mdio_write;
bus->reset = p3060qds_mdio_reset;
sprintf(bus->name, p3060qds_mdio_name_for_muxval(muxval));
pmdio->realbus = miiphy_get_dev_by_name(realbusname);
if (!pmdio->realbus) {
printf("No bus with name %s\n", realbusname);
free(bus);
free(pmdio);
return -1;
}
pmdio->muxval = muxval;
bus->priv = pmdio;
return mdio_register(bus);
}
void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
enum fm_port port, int offset)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
if (mdio_mux[port] == EMI1_RGMII1)
fdt_set_phy_handle(blob, prop, pa, "phy_rgmii1");
if (mdio_mux[port] == EMI1_RGMII2)
fdt_set_phy_handle(blob, prop, pa, "phy_rgmii2");
if ((mdio_mux[port] == EMI1_SLOT1) && ((srds_prtcl == 0x3)
|| (srds_prtcl == 0x6))) {
switch (port) {
case FM2_DTSEC4:
fdt_set_phy_handle(blob, prop, pa, "phy2_slot1");
break;
case FM1_DTSEC4:
fdt_set_phy_handle(blob, prop, pa, "phy3_slot1");
break;
default:
break;
}
}
if (mdio_mux[port] == EMI1_SLOT3) {
switch (port) {
case FM2_DTSEC3:
fdt_set_phy_handle(blob, prop, pa, "phy0_slot3");
break;
case FM1_DTSEC3:
fdt_set_phy_handle(blob, prop, pa, "phy1_slot3");
break;
default:
break;
}
}
}
void fdt_fixup_board_enet(void *fdt)
{
int i, lane, idx;
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
idx = i - FM1_DTSEC1;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_SGMII:
lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
if (lane < 0)
break;
switch (mdio_mux[i]) {
case EMI1_SLOT1:
if (lane >= 14) {
fdt_status_okay_by_alias(fdt,
"emi1_slot1");
fdt_status_disabled_by_alias(fdt,
"emi1_slot1_bk1");
} else {
fdt_status_disabled_by_alias(fdt,
"emi1_slot1");
fdt_status_okay_by_alias(fdt,
"emi1_slot1_bk1");
}
break;
case EMI1_SLOT2:
fdt_status_okay_by_alias(fdt, "emi1_slot2");
break;
case EMI1_SLOT3:
fdt_status_okay_by_alias(fdt, "emi1_slot3");
break;
}
break;
case PHY_INTERFACE_MODE_RGMII:
if (i == FM1_DTSEC1)
fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
if (i == FM1_DTSEC2)
fdt_status_okay_by_alias(fdt, "emi1_rgmii2");
break;
default:
break;
}
}
#if (CONFIG_SYS_NUM_FMAN == 2)
for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
idx = i - FM2_DTSEC1;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_SGMII:
lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
if (lane >= 0) {
switch (mdio_mux[i]) {
case EMI1_SLOT1:
if (lane >= 14)
fdt_status_okay_by_alias(fdt,
"emi1_slot1");
else
fdt_status_okay_by_alias(fdt,
"emi1_slot1_bk1");
break;
case EMI1_SLOT2:
fdt_status_okay_by_alias(fdt,
"emi1_slot2");
break;
case EMI1_SLOT3:
fdt_status_okay_by_alias(fdt,
"emi1_slot3");
break;
}
}
break;
default:
break;
}
}
#endif
}
static void initialize_lane_to_slot(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
int sdprtl = (in_be32(&gur->rcwsr[4]) &
FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
switch (sdprtl) {
case 0x03:
case 0x06:
lane_to_slot[8] = 1;
lane_to_slot[9] = lane_to_slot[8];
lane_to_slot[16] = 5;
lane_to_slot[17] = lane_to_slot[16];
break;
case 0x16:
case 0x19:
case 0x1C:
lane_to_slot[8] = 5;
lane_to_slot[9] = lane_to_slot[8];
lane_to_slot[16] = 1;
lane_to_slot[17] = lane_to_slot[16];
break;
default:
puts("Invalid SerDes protocol for P3060QDS\n");
break;
}
}
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FMAN_ENET
struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
int i;
struct fsl_pq_mdio_info dtsec_mdio_info;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
int srds_cfg = (in_be32(&gur->rcwsr[4]) &
FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
initialize_lane_to_slot();
/*
* Set TBIPA on FM1@DTSEC1. This is needed for configurations
* where FM1@DTSEC1 isn't used directly, since it provides
* MDIO for other ports.
*/
out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE);
/* Initialize the mdio_mux array so we can recognize empty elements */
for (i = 0; i < NUM_FM_PORTS; i++)
mdio_mux[i] = EMI_NONE;
dtsec_mdio_info.regs =
(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the 1G MDIO bus */
fsl_pq_mdio_init(bis, &dtsec_mdio_info);
/* Register the 5 muxing front-ends to the MDIO buses */
if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_RGMII)
p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
if (fm_info_get_enet_if(FM1_DTSEC2) == PHY_INTERFACE_MODE_RGMII)
p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_RGMII)
fm_info_set_phy_address(FM1_DTSEC1, 1); /* RGMII1 */
else if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_SGMII)
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT2_PHY_ADDR);
if (fm_info_get_enet_if(FM1_DTSEC2) == PHY_INTERFACE_MODE_RGMII)
fm_info_set_phy_address(FM1_DTSEC2, 2); /* RGMII2 */
else if (fm_info_get_enet_if(FM1_DTSEC2) == PHY_INTERFACE_MODE_SGMII)
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT3_PHY_ADDR);
switch (srds_cfg) {
case 0x03:
case 0x06:
fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT4_PHY_ADDR);
fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT2_PHY_ADDR);
break;
case 0x16:
case 0x19:
case 0x1C:
fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT2_PHY_ADDR);
fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
break;
default:
puts("Invalid SerDes protocol for P3060QDS\n");
break;
}
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
int idx = i - FM1_DTSEC1, lane, slot;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_SGMII:
lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
if (lane < 0)
break;
slot = lane_to_slot[lane];
if (QIXIS_READ(present) & (1 << (slot - 1)))
fm_disable_port(i);
switch (slot) {
case 1:
mdio_mux[i] = EMI1_SLOT1;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
case 2:
mdio_mux[i] = EMI1_SLOT2;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
case 3:
mdio_mux[i] = EMI1_SLOT3;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
};
break;
case PHY_INTERFACE_MODE_RGMII:
if (i == FM1_DTSEC1) {
mdio_mux[i] = EMI1_RGMII1;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
} else if (i == FM1_DTSEC2) {
mdio_mux[i] = EMI1_RGMII2;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
}
break;
default:
break;
}
}
#if (CONFIG_SYS_NUM_FMAN == 2)
for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
int idx = i - FM2_DTSEC1, lane, slot;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_SGMII:
lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
if (lane < 0)
break;
slot = lane_to_slot[lane];
if (QIXIS_READ(present) & (1 << (slot - 1)))
fm_disable_port(i);
switch (slot) {
case 1:
mdio_mux[i] = EMI1_SLOT1;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
case 2:
mdio_mux[i] = EMI1_SLOT2;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
case 3:
mdio_mux[i] = EMI1_SLOT3;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
};
break;
default:
break;
}
}
#endif /* CONFIG_SYS_NUM_FMAN */
cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */
return pci_eth_init(bis);
}

214
board/freescale/p3060qds/fixed_ddr.c
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@ -1,214 +0,0 @@
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*/
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000
#define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104
#define CONFIG_SYS_DDR_TIMING_1_1200 0x868FAA45
#define CONFIG_SYS_DDR_TIMING_2_1200 0x0FB8A912
#define CONFIG_SYS_DDR_MODE_1_1200 0x00441A40
#define CONFIG_SYS_DDR_MODE_2_1200 0x00100000
#define CONFIG_SYS_DDR_INTERVAL_1200 0x12480100
#define CONFIG_SYS_DDR_CLK_CTRL_1200 0x02800000
#define CONFIG_SYS_DDR_TIMING_3_1000 0x00020000
#define CONFIG_SYS_DDR_TIMING_0_1000 0xCC440104
#define CONFIG_SYS_DDR_TIMING_1_1000 0x727DF944
#define CONFIG_SYS_DDR_TIMING_2_1000 0x0FB088CF
#define CONFIG_SYS_DDR_MODE_1_1000 0x00441830
#define CONFIG_SYS_DDR_MODE_2_1000 0x00080000
#define CONFIG_SYS_DDR_INTERVAL_1000 0x0F3C0100
#define CONFIG_SYS_DDR_CLK_CTRL_1000 0x02800000
#define CONFIG_SYS_DDR_TIMING_3_900 0x00020000
#define CONFIG_SYS_DDR_TIMING_0_900 0xCC440104
#define CONFIG_SYS_DDR_TIMING_1_900 0x616ba844
#define CONFIG_SYS_DDR_TIMING_2_900 0x0fb088ce
#define CONFIG_SYS_DDR_MODE_1_900 0x00441620
#define CONFIG_SYS_DDR_MODE_2_900 0x00080000
#define CONFIG_SYS_DDR_INTERVAL_900 0x0db60100
#define CONFIG_SYS_DDR_CLK_CTRL_900 0x02800000
#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
#define CONFIG_SYS_DDR_TIMING_0_800 0xcc330104
#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b4744
#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cc
#define CONFIG_SYS_DDR_MODE_1_800 0x00441420
#define CONFIG_SYS_DDR_MODE_2_800 0x00000000
#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000
#define CONFIG_SYS_DDR_CS0_BNDS 0x000000FF
#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
#define CONFIG_SYS_DDR_CS2_BNDS 0x000000FF
#define CONFIG_SYS_DDR_CS3_BNDS 0x000000FF
#define CONFIG_SYS_DDR2_CS0_BNDS 0x000000FF
#define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000
#define CONFIG_SYS_DDR2_CS2_BNDS 0x000000FF
#define CONFIG_SYS_DDR2_CS3_BNDS 0x000000FF
#define CONFIG_SYS_DDR_CS0_CONFIG 0xA0044202
#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202
#define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000
#define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000
#define CONFIG_SYS_DDR2_CS0_CONFIG 0x80044202
#define CONFIG_SYS_DDR2_CS1_CONFIG 0x80004202
#define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000
#define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000
#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202
#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
#define CONFIG_SYS_DDR_TIMING_4 0x00000001
#define CONFIG_SYS_DDR_TIMING_5 0x02401400
#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607
#define CONFIG_SYS_DDR_SDRAM_CFG 0xE7044000
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x24401031
#define CONFIG_SYS_DDR_RCW_1 0x00000000
#define CONFIG_SYS_DDR_RCW_2 0x00000000
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
fsl_ddr_cfg_regs_t ddr_cfg_regs_900 = {
.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900,
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
fsl_ddr_cfg_regs_t ddr_cfg_regs_1000 = {
.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000,
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
fsl_ddr_cfg_regs_t ddr_cfg_regs_1200 = {
.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200,
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
fixed_ddr_parm_t fixed_ddr_parm_0[] = {
{750, 850, &ddr_cfg_regs_800},
{850, 950, &ddr_cfg_regs_900},
{950, 1050, &ddr_cfg_regs_1000},
{1050, 1250, &ddr_cfg_regs_1200},
{0, 0, NULL}
};

342
board/freescale/p3060qds/p3060qds.c
View File

@ -1,342 +0,0 @@
/*
* Copyright 2011-2012 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <netdev.h>
#include <linux/compiler.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include <configs/P3060QDS.h>
#include <libfdt.h>
#include <fdt_support.h>
#include "../common/qixis.h"
#include "p3060qds.h"
#include "p3060qds_qixis.h"
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
u8 sw;
struct cpu_type *cpu = gd->cpu;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
unsigned int i;
printf("Board: %s", cpu->name);
puts("QDS, ");
printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
sw = QIXIS_READ(brdcfg[0]);
sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
if (sw < 0x8)
printf("vBank: %d\n", sw);
else if (sw == 0x8)
puts("Promjet\n");
else if (sw == 0x9)
puts("NAND\n");
else
printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH);
puts("Reset Configuration Word (RCW):");
for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
u32 rcw = in_be32(&gur->rcwsr[i]);
if ((i % 4) == 0)
printf("\n %08x:", i * 4);
printf(" %08x", rcw);
}
puts("\n");
puts("SERDES Reference Clocks: ");
sw = QIXIS_READ(brdcfg[2]);
for (i = 0; i < 3; i++) {
static const char * const freq[] = {"100", "125", "Reserved",
"156.25"};
unsigned int clock = (sw >> (2 * i)) & 3;
printf("Bank%u=%sMhz ", i+1, freq[clock]);
}
puts("\n");
return 0;
}
int board_early_init_f(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
/* only single DDR controller on QDS board, disable DDR1_MCK4/5 */
setbits_be32(&gur->ddrclkdr, 0x00030000);
return 0;
}
void board_config_serdes_mux(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
int cfg = (in_be32(&gur->rcwsr[4]) &
FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
switch (cfg) {
case 0x03:
case 0x06:
/* set Lane I,J as SGMII */
QIXIS_WRITE(brdcfg[6], BRDCFG6_SD4MX_B | BRDCFG6_SD3MX_A |
BRDCFG6_SD2MX_B | BRDCFG6_SD1MX_A);
break;
case 0x16:
case 0x19:
case 0x1c:
/* set Lane I,J as Aurora Debug */
QIXIS_WRITE(brdcfg[6], BRDCFG6_SD4MX_A | BRDCFG6_SD3MX_B |
BRDCFG6_SD2MX_A | BRDCFG6_SD1MX_B);
break;
default:
puts("Invalid SerDes protocol for P3060QDS\n");
break;
}
}
void board_config_usb_mux(void)
{
u8 brdcfg4, brdcfg5, brdcfg7;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
u32 ec1 = rcwsr11 & FSL_CORENET_RCWSR11_EC1;
u32 ec2 = rcwsr11 & FSL_CORENET_RCWSR11_EC2;
brdcfg4 = QIXIS_READ(brdcfg[4]);
brdcfg4 &= ~BRDCFG4_EC_MODE_MASK;
if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_USB1) &&
(ec2 == FSL_CORENET_RCWSR11_EC2_USB2)) {
brdcfg4 |= BRDCFG4_EC2_USB_EC1_USB;
} else if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_USB1) &&
((ec2 == FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2) ||
(ec2 == FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))) {
brdcfg4 |= BRDCFG4_EC2_RGMII_EC1_USB;
} else if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1) &&
(ec2 == FSL_CORENET_RCWSR11_EC2_USB2)) {
brdcfg4 |= BRDCFG4_EC2_USB_EC1_RGMII;
} else if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1) &&
((ec2 == FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2) ||
(ec2 == FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))) {
brdcfg4 |= BRDCFG4_EC2_RGMII_EC1_RGMII;
} else {
brdcfg4 |= BRDCFG4_EC2_MII_EC1_MII;
}
QIXIS_WRITE(brdcfg[4], brdcfg4);
brdcfg5 = QIXIS_READ(brdcfg[5]);
brdcfg5 &= ~(BRDCFG5_USB1ID_MASK | BRDCFG5_USB2ID_MASK);
brdcfg5 |= (BRDCFG5_USB1ID_CTRL | BRDCFG5_USB2ID_CTRL);
QIXIS_WRITE(brdcfg[5], brdcfg5);
brdcfg7 = BRDCFG7_JTAGMX_COP_JTAG | BRDCFG7_IQ1MX_IRQ_EVT |
BRDCFG7_G1MX_USB1 | BRDCFG7_D1MX_TSEC3USB | BRDCFG7_I3MX_USB1;
QIXIS_WRITE(brdcfg[7], brdcfg7);
}
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
* so that flash can be erased properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
set_liodns();
#ifdef CONFIG_SYS_DPAA_QBMAN
setup_portals();
#endif
board_config_serdes_mux();
board_config_usb_mux();
return 0;
}
static const char *serdes_clock_to_string(u32 clock)
{
switch (clock) {
case SRDS_PLLCR0_RFCK_SEL_100:
return "100";
case SRDS_PLLCR0_RFCK_SEL_125:
return "125";
case SRDS_PLLCR0_RFCK_SEL_156_25:
return "156.25";
default:
return "150";
}
}
#define NUM_SRDS_BANKS 3
int misc_init_r(void)
{
serdes_corenet_t *srds_regs;
u32 actual[NUM_SRDS_BANKS];
unsigned int i;
u8 sw;
sw = QIXIS_READ(brdcfg[2]);
for (i = 0; i < 3; i++) {
unsigned int clock = (sw >> (2 * i)) & 3;
switch (clock) {
case 0:
actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
break;
case 1:
actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
break;
case 3:
actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
break;
default:
printf("Warning: SDREFCLK%u switch setting of '10' is "
"unsupported\n", i + 1);
break;
}
}
srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
for (i = 0; i < NUM_SRDS_BANKS; i++) {
u32 pllcr0 = in_be32(&srds_regs->bank[i].pllcr0);
u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
if (expected != actual[i]) {
printf("Warning: SERDES bank %u expects reference clock"
" %sMHz, but actual is %sMHz\n", i + 1,
serdes_clock_to_string(expected),
serdes_clock_to_string(actual[i]));
}
}
return 0;
}
/*
* This is map of CVDD values. 33 means CVDD is 3.3v, 25 means CVDD is 2.5v,
* 18 means CVDD is 1.8v.
*/
static u8 IO_VSEL[] = {
33, 33, 33, 25, 25, 25, 18, 18, 18,
33, 33, 33, 25, 25, 25, 18, 18, 18,
33, 33, 33, 25, 25, 25, 18, 18, 18,
33, 33, 33, 33, 33
};
#define IO_VSEL_MASK 0x1f
/*
* different CVDD selects diffenert spi flashs, read dutcfg[3] to get CVDD,
* then set status of spi flash nodes to 'disabled' according to CVDD.
* CVDD '33' will select spi flash0 and flash1, CVDD '25' will select spi
* flash2, CVDD '18' will select spi flash3.
*/
void fdt_fixup_board_spi(void *blob)
{
u8 sw5 = QIXIS_READ(dutcfg[3]);
switch (IO_VSEL[sw5 & IO_VSEL_MASK]) {
/* 3.3v */
case 33:
do_fixup_by_compat(blob, "atmel,at45db081d", "status",
"disabled", strlen("disabled") + 1, 1);
do_fixup_by_compat(blob, "spansion,sst25wf040", "status",
"disabled", strlen("disabled") + 1, 1);
break;
/* 2.5v */
case 25:
do_fixup_by_compat(blob, "spansion,s25sl12801", "status",
"disabled", strlen("disabled") + 1, 1);
do_fixup_by_compat(blob, "spansion,en25q32", "status",
"disabled", strlen("disabled") + 1, 1);
do_fixup_by_compat(blob, "spansion,sst25wf040", "status",
"disabled", strlen("disabled") + 1, 1);
break;
/* 1.8v */
case 18:
do_fixup_by_compat(blob, "spansion,s25sl12801", "status",
"disabled", strlen("disabled") + 1, 1);
do_fixup_by_compat(blob, "spansion,en25q32", "status",
"disabled", strlen("disabled") + 1, 1);
do_fixup_by_compat(blob, "atmel,at45db081d", "status",
"disabled", strlen("disabled") + 1, 1);
break;
}
}
void ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
ft_cpu_setup(blob, bd);
base = getenv_bootm_low();
size = getenv_bootm_size();
fdt_fixup_memory(blob, (u64)base, (u64)size);
#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
fdt_fixup_dr_usb(blob, bd);
#endif
#ifdef CONFIG_PCI
pci_of_setup(blob, bd);
#endif
fdt_fixup_liodn(blob);
fdt_fixup_dr_usb(blob, bd);
fdt_fixup_board_spi(blob);
#ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_ethernet(blob);
fdt_fixup_board_enet(blob);
#endif
}

74
board/freescale/p3060qds/p3060qds_qixis.h
View File

@ -1,74 +0,0 @@
/*
* Copyright 2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __P3060QDS_QIXIS_H__
#define __P3060QDS_QIXIS_H__
/* Definitions of QIXIS Registers for P3060QDS */
/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
#define BRDCFG4_EC_MODE_MASK 0x0F
#define BRDCFG4_EC2_MII_EC1_MII 0x00
#define BRDCFG4_EC2_MII_EC1_USB 0x03
#define BRDCFG4_EC2_USB_EC1_MII 0x0C
#define BRDCFG4_EC2_USB_EC1_USB 0x0F
#define BRDCFG4_EC2_USB_EC1_RGMII 0x0E
#define BRDCFG4_EC2_RGMII_EC1_USB 0x0B
#define BRDCFG4_EC2_RGMII_EC1_RGMII 0x0A
#define BRDCFG4_EMISEL_MASK 0xF0
#define BRDCFG5_ECLKS_MASK 0x80
#define BRDCFG5_USB1ID_MASK 0x40
#define BRDCFG5_USB2ID_MASK 0x20
#define BRDCFG5_GC2MX_MASK 0x0C
#define BRDCFG5_T15MX_MASK 0x03
#define BRDCFG5_ECLKS_IEEE1588_CM 0x80
#define BRDCFG5_USB1ID_CTRL 0x40
#define BRDCFG5_USB2ID_CTRL 0x20
#define BRDCFG6_SD1MX_A 0x01
#define BRDCFG6_SD1MX_B 0x00
#define BRDCFG6_SD2MX_A 0x02
#define BRDCFG6_SD2MX_B 0x00
#define BRDCFG6_SD3MX_A 0x04
#define BRDCFG6_SD3MX_B 0x00
#define BRDCFG6_SD4MX_A 0x08
#define BRDCFG6_SD4MX_B 0x00
#define BRDCFG7_JTAGMX_MASK 0xC0
#define BRDCFG7_IQ1MX_MASK 0x20
#define BRDCFG7_G1MX_MASK 0x10
#define BRDCFG7_D1MX_MASK 0x0C
#define BRDCFG7_I3MX_MASK 0x03
#define BRDCFG7_JTAGMX_AURORA 0x00
#define BRDCFG7_JTAGMX_FPGA 0x80
#define BRDCFG7_JTAGMX_COP_JTAG 0xC0
#define BRDCFG7_IQ1MX_IRQ_EVT 0x00
#define BRDCFG7_IQ1MX_USB2 0x20
#define BRDCFG7_G1MX_USB1 0x00
#define BRDCFG7_G1MX_TSEC3 0x10
#define BRDCFG7_D1MX_DMA 0x00
#define BRDCFG7_D1MX_TSEC3USB 0x04
#define BRDCFG7_D1MX_HDLC2 0x08
#define BRDCFG7_I3MX_UART2_I2C34 0x00
#define BRDCFG7_I3MX_GPIO_EVT 0x01
#define BRDCFG7_I3MX_USB1 0x02
#define BRDCFG7_I3MX_TSEC3 0x03
#endif

13
boards.cfg
View File

@ -809,29 +809,24 @@ P2041RDB_NAND powerpc mpc85xx p2041rdb freescale
P2041RDB_SDCARD powerpc mpc85xx p2041rdb freescale - P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
P2041RDB_SECURE_BOOT powerpc mpc85xx p2041rdb freescale - P2041RDB:SECURE_BOOT
P2041RDB_SPIFLASH powerpc mpc85xx p2041rdb freescale - P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
P2041RDB_SRIO_PCIE_BOOT powerpc mpc85xx p2041rdb freescale - P2041RDB:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
P3041DS powerpc mpc85xx corenet_ds freescale
P3041DS_NAND powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
P3041DS_SDCARD powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
P3041DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P3041DS:SECURE_BOOT
P3041DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
P3041DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P3041DS:SRIOBOOT_MASTER
P3041DS_SRIOBOOT_SLAVE powerpc mpc85xx corenet_ds freescale - P3041DS:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
P3060QDS powerpc mpc85xx p3060qds freescale
P3060QDS_NAND powerpc mpc85xx p3060qds freescale - P3060QDS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
P3060QDS_SECURE_BOOT powerpc mpc85xx p3060qds freescale - P3060QDS:SECURE_BOOT
P3041DS_SRIO_PCIE_BOOT powerpc mpc85xx corenet_ds freescale - P3041DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
P4080DS powerpc mpc85xx corenet_ds freescale
P4080DS_SDCARD powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
P4080DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P4080DS:SECURE_BOOT
P4080DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
P4080DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P4080DS:SRIOBOOT_MASTER
P4080DS_SRIOBOOT_SLAVE powerpc mpc85xx corenet_ds freescale - P4080DS:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
P4080DS_SRIO_PCIE_BOOT powerpc mpc85xx corenet_ds freescale - P4080DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
P5020DS powerpc mpc85xx corenet_ds freescale
P5020DS_NAND powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
P5020DS_SDCARD powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
P5020DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SECURE_BOOT
P5020DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
P5020DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P5020DS:SRIOBOOT_MASTER
P5020DS_SRIOBOOT_SLAVE powerpc mpc85xx corenet_ds freescale - P5020DS:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
P5020DS_SRIO_PCIE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
BSC9131RDB_SPIFLASH powerpc mpc85xx bsc9131rdb freescale - BSC9131RDB:BSC9131RDB,SPIFLASH
stxgp3 powerpc mpc85xx stxgp3 stx
stxssa powerpc mpc85xx stxssa stx - stxssa

4
common/env_remote.c
View File

@ -62,8 +62,8 @@ int env_init(void)
#ifdef CONFIG_CMD_SAVEENV
int saveenv(void)
{
#ifdef CONFIG_SRIOBOOT_SLAVE
printf("Can not support the 'saveenv' when boot from SRIO!\n");
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
printf("Can not support the 'saveenv' when boot from SRIO or PCIE!\n");
return 1;
#else
return 0;

1
common/image.c
View File

@ -143,6 +143,7 @@ static const table_entry_t uimage_type[] = {
{ IH_TYPE_INVALID, NULL, "Invalid Image", },
{ IH_TYPE_MULTI, "multi", "Multi-File Image", },
{ IH_TYPE_OMAPIMAGE, "omapimage", "TI OMAP SPL With GP CH",},
{ IH_TYPE_PBLIMAGE, "pblimage", "Freescale PBL Boot Image",},
{ IH_TYPE_RAMDISK, "ramdisk", "RAMDisk Image", },
{ IH_TYPE_SCRIPT, "script", "Script", },
{ IH_TYPE_STANDALONE, "standalone", "Standalone Program", },

34
doc/README.fsl-ddr
View File

@ -1,5 +1,28 @@
Table of interleaving 2-4 controllers
=====================================
+--------------+-----------------------------------------------------------+
|Configuration | Memory Controller |
| | 1 2 3 4 |
|--------------+--------------+--------------+-----------------------------+
| Two memory | Not Intlv'ed | Not Intlv'ed | |
| complexes +--------------+--------------+ |
| | 2-way Intlv'ed | |
|--------------+--------------+--------------+--------------+ |
| | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed | |
| Three memory +--------------+--------------+--------------+ |
| complexes | 2-way Intlv'ed | Not Intlv'ed | |
| +-----------------------------+--------------+ |
| | 3-way Intlv'ed | |
+--------------+--------------+--------------+--------------+--------------+
| | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed |
| Four memory +--------------+--------------+--------------+--------------+
| complexes | 2-way Intlv'ed | 2-way Intlv'ed |
| +-----------------------------+-----------------------------+
| | 4-way Intlv'ed |
+--------------+-----------------------------------------------------------+
Table of interleaving modes supported in cpu/8xxx/ddr/
Table of 2-way interleaving modes supported in cpu/8xxx/ddr/
======================================================
+-------------+---------------------------------------------------------+
| | Rank Interleaving |
@ -56,6 +79,15 @@ The ways to configure the ddr interleaving mode
# superbank
setenv hwconfig "fsl_ddr:ctlr_intlv=superbank"
# 1KB 3-way interleaving
setenv hwconfig "fsl_ddr:ctlr_intlv=3way_1KB"
# 4KB 3-way interleaving
setenv hwconfig "fsl_ddr:ctlr_intlv=3way_4KB"
# 8KB 3-way interleaving
setenv hwconfig "fsl_ddr:ctlr_intlv=3way_8KB"
# disable bank (chip-select) interleaving
setenv hwconfig "fsl_ddr:bank_intlv=null"

114
doc/README.pblimage 100644
View File

@ -0,0 +1,114 @@
------------------------------------------------------------------
Freescale PBL(pre-boot loader) Boot Image generation using mkimage
------------------------------------------------------------------
The CoreNet SoC's can boot directly from eSPI FLASH, SD/MMC and
NAND, etc. These SoCs use PBL to load RCW and/or pre-initialization
instructions. For more details refer section 5 Pre-boot loader
specifications of reference manual P3041RM/P4080RM/P5020RM at link:
http://www.freescale.com/webapp/search/Serp.jsp?Reference+Manuals
Building PBL Boot Image and boot steps
--------------------------------------
1. Building PBL Boot Image.
The default Image is u-boot.pbl.
For eSPI boot(available on P3041/P4080/P5020):
To build the eSPI boot image:
make <board_name>_SPIFLASH_config
make u-boot.pbl
For SD boot(available on P3041/P4080/P5020):
To build the SD boot image:
make <board_name>_SDCARD_config
make u-boot.pbl
For Nand boot(available on P3041/P5020):
To build the NAND boot image:
make <board_name>_NAND_config
make u-boot.pbl
2. pblimage support available with mkimage utility will generate Freescale PBL
boot image that can be flashed on the board eSPI flash, SD/MMC and NAND.
Following steps describe it in detail.
1). Boot from eSPI flash
Write u-boot.pbl to eSPI flash from offset 0x0.
for ex in u-boot:
=>tftp 100000 u-boot.pbl
=>sf probe 0
=>sf erase 0 100000
=>sf write 100000 0 $filesize
Change SW1[1:5] = off off on off on.
2). Boot from SD/MMC
Write u-boot.pbl to SD/MMC from offset 0x1000.
for ex in u-boot:
=>tftp 100000 u-boot.pbl
=>mmcinfo
=>mmc write 100000 8 441
Change SW1[1:5] = off off on on off.
3). Boot from Nand
Write u-boot.pbl to Nand from offset 0x0.
for ex in u-boot:
=>tftp 100000 u-boot.pbl
=>nand info
=>nand erase 0 100000
=>nand write 100000 0 $filesize
Change SW1[1:5] = off on off off on
Change SW7[1:4] = on off off on
Board specific configuration file specifications:
------------------------------------------------
1. Configuration files rcw.cfg and pbi.cfg must present in the
board/freescale/corenet_ds/, rcw.cfg is for RCW, pbi.cfg is for
PBI instructions. File name must not be changed since they are used
in Makefile.
2. These files can have empty lines and lines starting with "#" as first
character to put comments
Typical example of rcw.cfg file:
-----------------------------------
#PBL preamble and RCW header
aa55aa55 010e0100
#64 bytes RCW data
4c580000 00000000 18185218 0000cccc
40464000 3c3c2000 58000000 61000000
00000000 00000000 00000000 008b6000
00000000 00000000 00000000 00000000
Typical example of pbi.cfg file:
-----------------------------------
#PBI commands
#Initialize CPC1
09010000 00200400
09138000 00000000
091380c0 00000100
09010100 00000000
09010104 fff0000b
09010f00 08000000
09010000 80000000
#Configure LAW for CPC1
09000d00 00000000
09000d04 fff00000
09000d08 81000013
09000010 00000000
09000014 ff000000
09000018 81000000
#Initialize eSPI controller
09110000 80000403
09110020 2d170008
09110024 00100008
09110028 00100008
0911002c 00100008
#Flush PBL data
09138000 00000000
091380c0 00000000
------------------------------------------------
Author: Shaohui Xie<Shaohui.Xie@freescale.com>

103
doc/README.srio-boot-corenet
View File

@ -1,103 +0,0 @@
------------------------------
SRIO Boot on Corenet Platforms
------------------------------
For some PowerPC processors with SRIO interface, boot location can be configured
to SRIO by RCW. The processor booting from SRIO can do without flash for u-boot
image, ucode and ENV. All the images can be fetched from another processor's
memory space by SRIO link connected between them.
This document describes the processes based on an example implemented on P4080DS
platforms and a RCW example with boot from SRIO configuration.
Environment of the SRIO boot:
a) Master and slave can be SOCs in one board or SOCs in separate boards.
b) They are connected with SRIO links, whether 1x or 4x, and directly or
through switch system.
c) Only Master has NorFlash for booting, and all the Master's and Slave's
U-Boot images, UCodes will be stored in this flash.
d) Slave has its own EEPROM for RCW and PBI.
e) Slave's RCW should configure the SerDes for SRIO boot port, set the boot
location to SRIO, and holdoff all the cores if needed.
---------- ----------- -----------
| | | | | |
| | | | | |
| NorFlash|<----->| Master | SRIO | Slave |<---->[EEPROM]
| | | |<===========>| |
| | | | | |
---------- ----------- -----------
The example based on P4080DS platform:
Two P4080DS platforms can be used to implement the boot from SRIO. Their SRIO
ports 0 will be connected directly and will be used for the boot from SRIO.
1. Slave's RCW example for boot from SRIO port 0 and core 0 not in holdoff.
00000000: aa55 aa55 010e 0100 0c58 0000 0000 0000
00000010: 1818 1818 0000 8888 7440 4000 0000 2000
00000020: f400 0000 0100 0000 0000 0000 0000 0000
00000030: 0000 0000 0083 0000 0000 0000 0000 0000
00000040: 0000 0000 0000 0000 0813 8040 698b 93fe
2. Slave's RCW example for boot from SRIO port 0 and all cores in holdoff.
00000000: aa55 aa55 010e 0100 0c58 0000 0000 0000
00000010: 1818 1818 0000 8888 7440 4000 0000 2000
00000020: f440 0000 0100 0000 0000 0000 0000 0000
00000030: 0000 0000 0083 0000 0000 0000 0000 0000
00000040: 0000 0000 0000 0000 0813 8040 063c 778f
3. Sequence in Step by Step.
a) Update RCW for slave with boot from SRIO port 0 configuration.
b) Program slave's U-Boot image, UCode, and ENV parameters into master's
NorFlash.
c) Start up master and it will boot up normally from its NorFlash.
Then, it will finish necessary configurations for slave's boot from
SRIO port 0.
d) Master will set inbound SRIO windows covered slave's U-Boot image stored
in master's NorFlash.
e) Master will set an inbound SRIO window covered slave's UCode stored in
master's NorFlash.
f) Master will set an inbound SRIO window covered slave's ENV stored in
master's NorFlash.
g) If need to release slave's core, master will set outbound SRIO windows
in order to configure slave's registers for the core's releasing.
h) If all cores of slave in holdoff, slave should be powered on before all
the above master's steps, and wait to be released by master. If not all
cores in holdoff, that means core 0 will start up normally, slave should
be powered on after all the above master's steps. In the startup phase
of the slave from SRIO, it will finish some necessary configurations.
i) Slave will set a specific TLB entry for the boot process.
j) Slave will set a LAW entry with the TargetID SRIO port 0 for the boot.
k) Slave will set a specific TLB entry in order to fetch UCode and ENV
from master.
l) Slave will set a LAW entry with the TargetID SRIO port 0 for UCode and ENV.
How to use this feature:
To use this feature, you need to focus three points.
1. Slave's RCW with SRIO boot configurations, and all cores in holdoff
configurations if needed.
Please refer to the examples given above.
2. U-Boot image's compilation.
For master, U-Boot image should be generated specifically by
make xxxx_SRIOBOOT_MASTER_config.
For example, master U-Boot image used on P4080DS should be compiled with
make P4080DS_SRIOBOOT_MASTER_config.
For slave, U-Boot image should be generated specifically by
make xxxx_SRIOBOOT_SLAVE_config.
For example, slave U-Boot image used on P4080DS should be compiled with
make P4080DS_SRIOBOOT_SLAVE_config.
3. Necessary modifications based on a specific environment.
For a specific environment, the SRIO port for boot, the addresses of the
slave's U-Boot image, UCode, ENV stored in master's NorFlash, and any other
configurations can be modified in the file:
include/configs/corenet_ds.h.

112
doc/README.srio-pcie-boot-corenet 100644
View File

@ -0,0 +1,112 @@
---------------------------------------
SRIO and PCIE Boot on Corenet Platforms
---------------------------------------
For some PowerPC processors with SRIO or PCIE interface, boot location can be
configured to SRIO or PCIE by RCW. The processor booting from SRIO or PCIE can
do without flash for u-boot image, ucode and ENV. All the images can be fetched
from another processor's memory space by SRIO or PCIE link connected between
them.
This document describes the processes based on an example implemented on P4080DS
platforms and a RCW example with boot from SRIO or PCIE configuration.
Environment of the SRIO or PCIE boot:
a) Master and slave can be SOCs in one board or SOCs in separate boards.
b) They are connected with SRIO or PCIE links, whether 1x, 2x or 4x, and
directly or through switch system.
c) Only Master has NorFlash for booting, and all the Master's and Slave's
U-Boot images, UCodes will be stored in this flash.
d) Slave has its own EEPROM for RCW and PBI.
e) Slave's RCW should configure the SerDes for SRIO or PCIE boot port, set
the boot location to SRIO or PCIE, and holdoff all the cores.
---------- ----------- -----------
| | | | | |
| | | | | |
| NorFlash|<----->| Master |SRIO or PCIE | Slave |<---->[EEPROM]
| | | |<===========>| |
| | | | | |
---------- ----------- -----------
The example based on P4080DS platform:
Two P4080DS platforms can be used to implement the boot from SRIO or PCIE.
Their SRIO or PCIE ports 1 will be connected directly and will be used for
the boot from SRIO or PCIE.
1. Slave's RCW example for boot from SRIO port 1 and all cores in holdoff.
00000000: aa55 aa55 010e 0100 0c58 0000 0000 0000
00000010: 1818 1818 0000 8888 7440 4000 0000 2000
00000020: f440 0000 0100 0000 0000 0000 0000 0000
00000030: 0000 0000 0083 0000 0000 0000 0000 0000
00000040: 0000 0000 0000 0000 0813 8040 063c 778f
2. Slave's RCW example for boot from PCIE port 1 and all cores in holdoff.
00000000: aa55 aa55 010e 0100 0c58 0000 0000 0000
00000010: 1818 1818 0000 8888 1440 4000 0000 2000
00000020: f040 0000 0100 0000 0020 0000 0000 0000
00000030: 0000 0000 0083 0000 0000 0000 0000 0000
00000040: 0000 0000 0000 0000 0813 8040 547e ffc9
3. Sequence in Step by Step.
a) Update RCW for slave with boot from SRIO or PCIE port 1 configuration.
b) Program slave's U-Boot image, UCode, and ENV parameters into master's
NorFlash.
c) Set environment variable "bootmaster" to "SRIO1" or "PCIE1" and save
environment for master.
setenv bootmaster SRIO1
or
setenv bootmaster PCIE1
saveenv
d) Restart up master and it will boot up normally from its NorFlash.
Then, it will finish necessary configurations for slave's boot from
SRIO or PCIE port 1.
e) Master will set inbound SRIO or PCIE windows covered slave's U-Boot
image stored in master's NorFlash.
f) Master will set an inbound SRIO or PCIE window covered slave's UCode
and ENV stored in master's NorFlash.
g) Master will set outbound SRIO or PCIE windows in order to configure
slave's registers for the core's releasing.
h) Since all cores of slave in holdoff, slave should be powered on before
all the above master's steps, and wait to be released by master. In the
startup phase of the slave from SRIO or PCIE, it will finish some
necessary configurations.
i) Slave will set a specific TLB entry for the boot process.
j) Slave will set a LAW entry with the TargetID SRIO or PCIE port 1 for
the boot.
k) Slave will set a specific TLB entry in order to fetch UCode and ENV
from master.
l) Slave will set a LAW entry with the TargetID SRIO or PCIE port 1 for
UCode and ENV.
How to use this feature:
To use this feature, you need to focus those points.
1. Slave's RCW with SRIO or PCIE boot configurations, and all cores in holdoff
configurations.
Please refer to the examples given above.
2. U-Boot image's compilation.
For master, U-Boot image should be generated normally.
For example, master U-Boot image used on P4080DS should be compiled with
make P4080DS_config.
For slave, U-Boot image should be generated specifically by
make xxxx_SRIO_PCIE_BOOT_config.
For example, slave U-Boot image used on P4080DS should be compiled with
make P4080DS_SRIO_PCIE_BOOT_config.
3. Necessary modifications based on a specific environment.
For a specific environment, the addresses of the slave's U-Boot image,
UCode, ENV stored in master's NorFlash, and any other configurations
can be modified in the file:
include/configs/corenet_ds.h.
4. Set and save the environment variable "bootmaster" with "SRIO1", "SRIO2"
or "PCIE1", "PCIE2", "PCIE3" for master, and then restart it in order to
perform the role as a master for boot from SRIO or PCIE.

54
drivers/misc/fsl_law.c
View File

@ -275,5 +275,59 @@ void init_laws(void)
law_table[i].size, law_table[i].trgt_id);
}
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
/* check RCW to get which port is used for boot */
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
u32 bootloc = in_be32(&gur->rcwsr[6]);
/*
* in SRIO or PCIE boot we need to set specail LAWs for
* SRIO or PCIE interfaces.
*/
switch ((bootloc & FSL_CORENET_RCWSR6_BOOT_LOC) >> 23) {
case 0x0: /* boot from PCIE1 */
set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
LAW_SIZE_1M,
LAW_TRGT_IF_PCIE_1);
set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
LAW_SIZE_1M,
LAW_TRGT_IF_PCIE_1);
break;
case 0x1: /* boot from PCIE2 */
set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
LAW_SIZE_1M,
LAW_TRGT_IF_PCIE_2);
set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
LAW_SIZE_1M,
LAW_TRGT_IF_PCIE_2);
break;
case 0x2: /* boot from PCIE3 */
set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
LAW_SIZE_1M,
LAW_TRGT_IF_PCIE_3);
set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
LAW_SIZE_1M,
LAW_TRGT_IF_PCIE_3);
break;
case 0x8: /* boot from SRIO1 */
set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
LAW_SIZE_1M,
LAW_TRGT_IF_RIO_1);
set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
LAW_SIZE_1M,
LAW_TRGT_IF_RIO_1);
break;
case 0x9: /* boot from SRIO2 */
set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
LAW_SIZE_1M,
LAW_TRGT_IF_RIO_2);
set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
LAW_SIZE_1M,
LAW_TRGT_IF_RIO_2);
break;
default:
break;
}
#endif
return ;
}

2
drivers/net/fm/Makefile
View File

@ -36,10 +36,8 @@ COBJS-y += tgec_phy.o
COBJS-$(CONFIG_P1017) += p1023.o
COBJS-$(CONFIG_P1023) += p1023.o
# The P204x, P304x, and P5020 are the same
COBJS-$(CONFIG_PPC_P2040) += p5020.o
COBJS-$(CONFIG_PPC_P2041) += p5020.o
COBJS-$(CONFIG_PPC_P3041) += p5020.o
COBJS-$(CONFIG_PPC_P3060) += p3060.o
COBJS-$(CONFIG_PPC_P4080) += p4080.o
COBJS-$(CONFIG_PPC_P5020) += p5020.o
endif

30
drivers/net/fm/init.c
View File

@ -50,6 +50,9 @@ struct fm_eth_info fm_info[] = {
#if (CONFIG_SYS_NUM_FM2_DTSEC >= 4)
FM_DTSEC_INFO_INITIALIZER(2, 4),
#endif
#if (CONFIG_SYS_NUM_FM2_DTSEC >= 5)
FM_DTSEC_INFO_INITIALIZER(2, 5),
#endif
#if (CONFIG_SYS_NUM_FM1_10GEC >= 1)
FM_TGEC_INFO_INITIALIZER(1, 1),
#endif
@ -151,6 +154,22 @@ void fm_info_set_phy_address(enum fm_port port, int address)
fm_info[i].phy_addr = address;
}
/*
* Returns the PHY address for a given Fman port
*
* The port must be set via a prior call to fm_info_set_phy_address().
* A negative error code is returned if the port is invalid.
*/
int fm_info_get_phy_address(enum fm_port port)
{
int i = fm_port_to_index(port);
if (i == -1)
return -1;
return fm_info[i].phy_addr;
}
/*
* Returns the type of the data interface between the given MAC and its PHY.
* This is typically determined by the RCW.
@ -181,7 +200,8 @@ void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop)
{
int off, ph;
int off;
uint32_t ph;
phys_addr_t paddr = CONFIG_SYS_CCSRBAR_PHYS + info->compat_offset;
u64 dtsec1_addr = (u64)CONFIG_SYS_CCSRBAR_PHYS +
CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET;
@ -198,12 +218,10 @@ static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop)
off = fdt_node_offset_by_compat_reg(blob, prop, paddr);
/* Don't disable FM1-DTSEC1 MAC as its used for MDIO */
if (paddr != dtsec1_addr) {
/* disable the mac node */
fdt_setprop_string(blob, off, "status", "disabled");
}
if (paddr != dtsec1_addr)
fdt_status_disabled(blob, off); /* disable the MAC node */
/* disable the node point to the mac */
/* disable the fsl,dpa-ethernet node that points to the MAC */
ph = fdt_get_phandle(blob, off);
do_fixup_by_prop(blob, "fsl,fman-mac", &ph, sizeof(ph),
"status", "disabled", strlen("disabled") + 1, 1);

97
drivers/net/fm/p3060.c
View File

@ -1,97 +0,0 @@
/*
* Copyright 2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <phy.h>
#include <fm_eth.h>
#include <asm/io.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
u32 port_to_devdisr[] = {
[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
[FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
[FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1,
[FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2,
[FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3,
[FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4,
};
static int is_device_disabled(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2;
}
void fman_disable_port(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
/* don't allow disabling of DTSEC1 as its needed for MDIO */
if (port == FM1_DTSEC1)
return;
setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
phy_interface_t fman_port_enet_if(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
if (is_device_disabled(port))
return PHY_INTERFACE_MODE_NONE;
/* handle RGMII/MII first */
if ((port == FM1_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1))
return PHY_INTERFACE_MODE_RGMII;
if ((port == FM1_DTSEC2) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2))
return PHY_INTERFACE_MODE_RGMII;
if ((port == FM2_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))
return PHY_INTERFACE_MODE_RGMII;
switch (port) {
case FM1_DTSEC1:
case FM1_DTSEC2:
case FM1_DTSEC3:
case FM1_DTSEC4:
if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
return PHY_INTERFACE_MODE_SGMII;
break;
case FM2_DTSEC1:
case FM2_DTSEC2:
case FM2_DTSEC3:
case FM2_DTSEC4:
if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1))
return PHY_INTERFACE_MODE_SGMII;
break;
default:
return PHY_INTERFACE_MODE_NONE;
}
return PHY_INTERFACE_MODE_NONE;
}

116
drivers/pci/fsl_pci_init.c
View File

@ -211,6 +211,95 @@ static int fsl_pci_setup_inbound_windows(struct pci_controller *hose,
return 1;
}
#ifdef CONFIG_FSL_CORENET
static void fsl_pcie_boot_master(pit_t *pi)
{
/* configure inbound window for slave's u-boot image */
debug("PCIEBOOT - MASTER: Inbound window for slave's image; "
"Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
(u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
(u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
struct pci_region r_inbound;
u32 sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE)
- 1;
pci_set_region(&r_inbound,
CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
sz_inbound,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
set_inbound_window(pi--, &r_inbound,
CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
/* configure inbound window for slave's u-boot image */
debug("PCIEBOOT - MASTER: Inbound window for slave's image; "
"Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
(u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
(u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
pci_set_region(&r_inbound,
CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
sz_inbound,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
set_inbound_window(pi--, &r_inbound,
CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
/* configure inbound window for slave's ucode and ENV */
debug("PCIEBOOT - MASTER: Inbound window for slave's "
"ucode and ENV; "
"Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
(u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
(u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE)
- 1;
pci_set_region(&r_inbound,
CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
sz_inbound,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
set_inbound_window(pi--, &r_inbound,
CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
}
static void fsl_pcie_boot_master_release_slave(int port)
{
unsigned long release_addr;
/* now release slave's core 0 */
switch (port) {
case 1:
release_addr = CONFIG_SYS_PCIE1_MEM_VIRT
+ CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
break;
case 2:
release_addr = CONFIG_SYS_PCIE2_MEM_VIRT
+ CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
break;
case 3:
release_addr = CONFIG_SYS_PCIE3_MEM_VIRT
+ CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
break;
default:
release_addr = 0;
break;
}
if (release_addr != 0) {
out_be32((void *)release_addr,
CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK);
debug("PCIEBOOT - MASTER: "
"Release slave successfully! Now the slave should start up!\n");
} else {
debug("PCIEBOOT - MASTER: "
"Release slave failed!\n");
}
}
#endif
void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
{
u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr;
@ -295,8 +384,25 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
/* see if we are a PCIe or PCI controller */
pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
#ifdef CONFIG_FSL_CORENET
/* boot from PCIE --master */
char *s = getenv("bootmaster");
char pcie[6];
sprintf(pcie, "PCIE%d", pci_info->pci_num);
if (s && (strcmp(s, pcie) == 0)) {
debug("PCIEBOOT - MASTER: Master port [ %d ] for pcie boot.\n",
pci_info->pci_num);
fsl_pcie_boot_master((pit_t *)pi);
} else {
/* inbound */
inbound = fsl_pci_setup_inbound_windows(hose,
out_lo, pcie_cap, pi);
}
#else
/* inbound */
inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi);
#endif
for (r = 0; r < hose->region_count; r++)
debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n", r,
@ -488,6 +594,16 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info,
if (fsl_is_pci_agent(hose)) {
fsl_pci_config_unlock(hose);
hose->last_busno = hose->first_busno;
#ifdef CONFIG_FSL_CORENET
} else {
/* boot from PCIE --master releases slave's core 0 */
char *s = getenv("bootmaster");
char pcie[6];
sprintf(pcie, "PCIE%d", pci_info->pci_num);
if (s && (strcmp(s, pcie) == 0))
fsl_pcie_boot_master_release_slave(pci_info->pci_num);
#endif
}
pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);

15
drivers/qe/uec.c
View File

@ -580,8 +580,7 @@ static void phy_change(struct eth_device *dev)
{
uec_private_t *uec = (uec_private_t *)dev->priv;
#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
defined(CONFIG_P1021) || defined(CONFIG_P1025)
#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
/* QE9 and QE12 need to be set for enabling QE MII managment signals */
@ -592,8 +591,7 @@ static void phy_change(struct eth_device *dev)
/* Update the link, speed, duplex */
uec->mii_info->phyinfo->read_status(uec->mii_info);
#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
defined(CONFIG_P1021) || defined(CONFIG_P1025)
#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
/*
* QE12 is muxed with LBCTL, it needs to be released for enabling
* LBCTL signal for LBC usage.
@ -1208,16 +1206,14 @@ static int uec_init(struct eth_device* dev, bd_t *bd)
uec_private_t *uec;
int err, i;
struct phy_info *curphy;
#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
defined(CONFIG_P1021) || defined(CONFIG_P1025)
#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif
uec = (uec_private_t *)dev->priv;
if (uec->the_first_run == 0) {
#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
defined(CONFIG_P1021) || defined(CONFIG_P1025)
#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
/* QE9 and QE12 need to be set for enabling QE MII managment signals */
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
@ -1249,8 +1245,7 @@ static int uec_init(struct eth_device* dev, bd_t *bd)
udelay(100000);
} while (1);
#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
defined(CONFIG_P1021) || defined(CONFIG_P1025)
#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
/* QE12 needs to be released for enabling LBCTL signal*/
clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
#endif

58
include/configs/P2041RDB.h
View File

@ -22,7 +22,7 @@
/*
* P2041 RDB board configuration file
*
* Also supports P2040 RDB
*/
#ifndef __CONFIG_H
#define __CONFIG_H
@ -36,6 +36,15 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
/* Set 1M boot space */
#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CONFIG_SYS_NO_FLASH
#endif
/* High Level Configuration Options */
#define CONFIG_BOOKE
#define CONFIG_E500 /* BOOKE e500 family */
@ -73,7 +82,7 @@
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_SYS_NO_FLASH
#ifndef CONFIG_RAMBOOT_PBL
#if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
#define CONFIG_ENV_IS_NOWHERE
#endif
#else
@ -104,8 +113,12 @@
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
#define CONFIG_ENV_IS_IN_REMOTE
#define CONFIG_ENV_ADDR 0xffe20000
#define CONFIG_ENV_SIZE 0x2000
#elif defined(CONFIG_ENV_IS_NOWHERE)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SIZE 0x2000
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
@ -373,6 +386,35 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#endif
#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
/*
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
/*
* for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
/* slave core release by master*/
#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
/*
* SRIO_PCIE_BOOT - SLAVE
*/
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
#endif
/*
* eSPI - Enhanced SPI
*/
@ -485,6 +527,16 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* Slave has no ucode locally, it can fetch this from remote. When implementing
* in two corenet boards, slave's ucode could be stored in master's memory
* space, the address can be mapped from slave TLB->slave LAW->
* slave SRIO or PCIE outbound window->master inbound window->
* master LAW->the ucode address in master's memory space.
*/
#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000

48
include/configs/P3060QDS.h
View File

@ -1,48 +0,0 @@
/*
* Copyright 2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* P3060 QDS board configuration file
*/
#define CONFIG_P3060QDS
#define CONFIG_PHYS_64BIT
#define CONFIG_PPC_P3060
#define CONFIG_FSL_QIXIS
#define CONFIG_NAND_FSL_ELBC
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#define CONFIG_SPI_FLASH_ATMEL
#define CONFIG_SPI_FLASH_EON
#define CONFIG_SPI_FLASH_SST
#include "corenet_ds.h"
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
/* There is a PCA9547 8-channel I2C-bus multiplexer on P3060QDS board */
#define CONFIG_I2C_MUX
#define CONFIG_I2C_MULTI_BUS

1
include/configs/P4080DS.h
View File

@ -22,6 +22,7 @@
/*
* P4080 DS board configuration file
* Also supports P4040 DS
*/
#define CONFIG_P4080DS
#define CONFIG_PHYS_64BIT

2
include/configs/P5020DS.h
View File

@ -22,7 +22,7 @@
/*
* P5020 DS board configuration file
*
* Also supports P5010 DS
*/
#define CONFIG_P5020DS
#define CONFIG_PHYS_64BIT

83
include/configs/corenet_ds.h
View File

@ -31,13 +31,21 @@
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg
#if defined(CONFIG_P3041DS)
#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p3041ds.cfg
#elif defined(CONFIG_P4080DS)
#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p4080ds.cfg
#elif defined(CONFIG_P5020DS)
#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5020ds.cfg
#endif
#endif
#ifdef CONFIG_SRIOBOOT_SLAVE
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
/* Set 1M boot space */
#define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
#define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS \
(0x300000000ull | CONFIG_SYS_SRIOBOOT_SLAVE_ADDR)
#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CONFIG_SYS_NO_FLASH
#endif
@ -77,7 +85,7 @@
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_SYS_NO_FLASH
#if !defined(CONFIG_SRIOBOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
#define CONFIG_ENV_IS_NOWHERE
#endif
#else
@ -108,7 +116,7 @@
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIOBOOT_SLAVE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
#define CONFIG_ENV_IS_IN_REMOTE
#define CONFIG_ENV_ADDR 0xffe20000
#define CONFIG_ENV_SIZE 0x2000
@ -186,11 +194,7 @@
#define CONFIG_DDR_SPD
#define CONFIG_FSL_DDR3
#ifdef CONFIG_P3060QDS
#define CONFIG_SYS_SPD_BUS_NUM 0
#else
#define CONFIG_SYS_SPD_BUS_NUM 1
#endif
#define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS2 0x52
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
@ -388,52 +392,33 @@
#endif
#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
/*
* SRIOBOOT - MASTER
*/
#ifdef CONFIG_SRIOBOOT_MASTER
/* master port for srioboot*/
#define CONFIG_SRIOBOOT_MASTER_PORT 0
/* #define CONFIG_SRIOBOOT_MASTER_PORT 1 */
/*
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
#define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 0xfef080000ull
#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 0xfff80000ull
#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE 0x80000 /* 512K */
#define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2 0xfef080000ull
#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 0x3fff80000ull
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
/*
* for slave UCODE instored in master memory space,
* for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
#define CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS 0xfef020000ull
#define CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS 0x3ffe00000ull
#define CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE 0x10000 /* 64K */
/*
* for slave ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
#define CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS 0xfef060000ull
#define CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS 0x3ffe20000ull
#define CONFIG_SRIOBOOT_SLAVE_ENV_SIZE 0x20000 /* 128K */
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
/* slave core release by master*/
#define CONFIG_SRIOBOOT_SLAVE_HOLDOFF
#define CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET 0xe00e4
#define CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK 0x00000001 /* release core 0 */
#endif
#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
/*
* SRIOBOOT - SLAVE
* SRIO_PCIE_BOOT - SLAVE
*/
#ifdef CONFIG_SRIOBOOT_SLAVE
/* slave port for srioboot */
#define CONFIG_SRIOBOOT_SLAVE_PORT0
/* #define CONFIG_SRIOBOOT_SLAVE_PORT1 */
#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR 0xFFE00000
#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS \
(0x300000000ull | CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR)
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
#endif
/*
@ -556,13 +541,13 @@
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIOBOOT_SLAVE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* Slave has no ucode locally, it can fetch this from remote. When implementing
* in two corenet boards, slave's ucode could be stored in master's memory
* space, the address can be mapped from slave TLB->slave LAW->
* slave SRIO outbound window->master inbound window->master LAW->
* the ucode address in master's NOR flash.
* slave SRIO or PCIE outbound window->master inbound window->
* master LAW->the ucode address in master's memory space.
*/
#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
@ -724,7 +709,7 @@
#define CONFIG_BAUDRATE 115200
#if defined(CONFIG_P4080DS) || defined(CONFIG_P3060QDS)
#ifdef CONFIG_P4080DS
#define __USB_PHY_TYPE ulpi
#else
#define __USB_PHY_TYPE utmi

10
include/configs/p1_p2_rdb_pc.h
View File

@ -31,7 +31,7 @@
#endif
#if defined(CONFIG_P1020MBG)
#define CONFIG_BOARDNAME "P1020MBG"
#define CONFIG_BOARDNAME "P1020MBG-PC"
#define CONFIG_P1020
#define CONFIG_VSC7385_ENET
#define CONFIG_SLIC
@ -41,7 +41,7 @@
#endif
#if defined(CONFIG_P1020UTM)
#define CONFIG_BOARDNAME "P1020UTM"
#define CONFIG_BOARDNAME "P1020UTM-PC"
#define CONFIG_P1020
#define __SW_BOOT_MASK 0x03
#define __SW_BOOT_NOR 0xe0
@ -49,7 +49,7 @@
#endif
#if defined(CONFIG_P1020RDB)
#define CONFIG_BOARDNAME "P1020RDB"
#define CONFIG_BOARDNAME "P1020RDB-PC"
#define CONFIG_NAND_FSL_ELBC
#define CONFIG_P1020
#define CONFIG_SPI_FLASH
@ -64,7 +64,7 @@
#endif
#if defined(CONFIG_P1021RDB)
#define CONFIG_BOARDNAME "P1021RDB"
#define CONFIG_BOARDNAME "P1021RDB-PC"
#define CONFIG_NAND_FSL_ELBC
#define CONFIG_P1021
#define CONFIG_QE
@ -111,7 +111,7 @@
#endif
#if defined(CONFIG_P2020RDB)
#define CONFIG_BOARDNAME "P2020RDB"
#define CONFIG_BOARDNAME "P2020RDB-PCA"
#define CONFIG_NAND_FSL_ELBC
#define CONFIG_P2020
#define CONFIG_SPI_FLASH

7
include/ddr_spd.h
View File

@ -221,7 +221,12 @@ typedef struct ddr3_spd_eeprom_s {
unsigned char therm_ref_opt; /* 31 SDRAM Thermal and Refresh Opts */
unsigned char therm_sensor; /* 32 Module Thermal Sensor */
unsigned char device_type; /* 33 SDRAM device type */
unsigned char res_34_59[26]; /* 34-59 Reserved, General Section */
int8_t fine_tCK_min; /* 34 Fine offset for tCKmin */
int8_t fine_tAA_min; /* 35 Fine offset for tAAmin */
int8_t fine_tRCD_min; /* 36 Fine offset for tRCDmin */
int8_t fine_tRP_min; /* 37 Fine offset for tRPmin */
int8_t fine_tRC_min; /* 38 Fine offset for tRCmin */
unsigned char res_39_59[21]; /* 39-59 Reserved, General Section */
/* Module-Specific Section: Bytes 60-116 */
union {

2
include/fm_eth.h
View File

@ -35,6 +35,7 @@ enum fm_port {
FM2_DTSEC2,
FM2_DTSEC3,
FM2_DTSEC4,
FM2_DTSEC5,
FM2_10GEC1,
NUM_FM_PORTS,
};
@ -109,6 +110,7 @@ void fman_enet_init(void);
void fdt_fixup_fman_ethernet(void *fdt);
phy_interface_t fm_info_get_enet_if(enum fm_port port);
void fm_info_set_phy_address(enum fm_port port, int address);
int fm_info_get_phy_address(enum fm_port port);
void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus);
void fm_disable_port(enum fm_port port);

1
include/image.h
View File

@ -164,6 +164,7 @@
#define IH_TYPE_OMAPIMAGE 12 /* TI OMAP Config Header Image */
#define IH_TYPE_AISIMAGE 13 /* TI Davinci AIS Image */
#define IH_TYPE_KERNEL_NOLOAD 14 /* OS Kernel Image, can run from any load address */
#define IH_TYPE_PBLIMAGE 15 /* Freescale PBL Boot Image */
/*
* Compression Types

40
nand_spl/board/freescale/common.c 100644
View File

@ -0,0 +1,40 @@
/*
* Copyright 2012 Freescale Semiconductor, Inc.
* Author: Matthew McClintock <msm@freescale.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <asm/processor.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_FSL_TBCLK_DIV
#define CONFIG_SYS_FSL_TBCLK_DIV 8
#endif
void udelay(unsigned long usec)
{
u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000);
u32 ticks = ticks_per_usec * usec;
u32 s = mfspr(SPRN_TBRL);
while ((mfspr(SPRN_TBRL) - s) < ticks);
}

6
nand_spl/board/freescale/p1010rdb/Makefile
View File

@ -39,7 +39,8 @@ CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o resetvec.o ticks.o
COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o
nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o \
../common.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
@ -123,6 +124,9 @@ ifneq ($(OBJTREE), $(SRCTREE))
$(obj)nand_boot.c:
@rm -f $(obj)nand_boot.c
ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
$(obj)../common.c:
@rm -f $(obj)../common.c
ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c
endif
#########################################################################

77
nand_spl/board/freescale/p1010rdb/nand_boot.c
View File

@ -27,51 +27,61 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_law.h>
#include <asm/global_data.h>
#define udelay(x) { int j; for (j = 0; j < x * 10000; j++) isync(); }
DECLARE_GLOBAL_DATA_PTR;
unsigned long ddr_freq_mhz;
void sdram_init(void)
{
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
/* mask off E bit */
u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR));
out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE);
out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL_2);
out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
__raw_writel(CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE, &ddr->sdram_cfg);
__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
__raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
if (ddr_freq_mhz < 700) {
out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3_667);
out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0_667);
out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_667);
out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_667);
out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_667);
out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_667);
out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_667);
out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_667);
out_be32(&ddr->ddr_wrlvl_cntl,
CONFIG_SYS_DDR_WRLVL_CONTROL_667);
__raw_writel(CONFIG_SYS_DDR_TIMING_3_667, &ddr->timing_cfg_3);
__raw_writel(CONFIG_SYS_DDR_TIMING_0_667, &ddr->timing_cfg_0);
__raw_writel(CONFIG_SYS_DDR_TIMING_1_667, &ddr->timing_cfg_1);
__raw_writel(CONFIG_SYS_DDR_TIMING_2_667, &ddr->timing_cfg_2);
__raw_writel(CONFIG_SYS_DDR_MODE_1_667, &ddr->sdram_mode);
__raw_writel(CONFIG_SYS_DDR_MODE_2_667, &ddr->sdram_mode_2);
__raw_writel(CONFIG_SYS_DDR_INTERVAL_667, &ddr->sdram_interval);
__raw_writel(CONFIG_SYS_DDR_CLK_CTRL_667, &ddr->sdram_clk_cntl);
__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_667, &ddr->ddr_wrlvl_cntl);
} else {
out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3_800);
out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0_800);
out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_800);
out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_800);
out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_800);
out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_800);
out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_800);
out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_800);
out_be32(&ddr->ddr_wrlvl_cntl,
CONFIG_SYS_DDR_WRLVL_CONTROL_800);
__raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
__raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
__raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
__raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
__raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
__raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
__raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
__raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
}
out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CONTROL);
__raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
__raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
__raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
/* mimic 500us delay, with busy isync() loop */
udelay(100);
/* P1014 and it's derivatives support max 16bit DDR width */
if (svr == SVR_P1014) {
__raw_writel(ddr->sdram_cfg & ~SDRAM_CFG_DBW_MASK, &ddr->sdram_cfg);
__raw_writel(ddr->sdram_cfg | SDRAM_CFG_16_BE, &ddr->sdram_cfg);
/* For CS0_BNDS we divide the start and end address by 2, so we can just
* shift the entire register to achieve the desired result and the mask
* the value so we don't write reserved fields */
__raw_writel((CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff, &ddr->cs0_bnds);
}
udelay(500);
/* Let the controller go */
out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
@ -82,20 +92,19 @@ void sdram_init(void)
void board_init_f(ulong bootflag)
{
u32 plat_ratio, ddr_ratio;
unsigned long bus_clk;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
/* initialize selected port with appropriate baud rate */
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
plat_ratio >>= 1;
bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 0x1000000;
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
bus_clk / 16 / CONFIG_BAUDRATE);
gd->bus_clk / 16 / CONFIG_BAUDRATE);
puts("\nNAND boot... ");

6
nand_spl/board/freescale/p1023rds/Makefile
View File

@ -34,7 +34,8 @@ CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o resetvec.o
COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o \
../common.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
@ -114,6 +115,9 @@ ifneq ($(OBJTREE), $(SRCTREE))
$(obj)nand_boot.c:
@rm -f $(obj)nand_boot.c
ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
$(obj)../common.c:
@rm -f $(obj)../common.c
ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c
endif
#########################################################################

59
nand_spl/board/freescale/p1023rds/nand_boot.c
View File

@ -25,6 +25,10 @@
#include <asm/io.h>
#include <nand.h>
#include <asm/fsl_law.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
/* Fixed sdram init -- doesn't use serial presence detect. */
void sdram_init(void)
@ -33,40 +37,47 @@ void sdram_init(void)
set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1);
out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
out_be32(&ddr->cs1_bnds, CONFIG_SYS_DDR_CS1_BNDS);
out_be32(&ddr->cs1_config, CONFIG_SYS_DDR_CS1_CONFIG);
out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2);
out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1);
out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2);
out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL);
out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL);
out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
out_be32(&ddr->ddr_cdr1, CONFIG_SYS_DDR_CDR_1);
out_be32(&ddr->ddr_cdr2, CONFIG_SYS_DDR_CDR_2);
out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
__raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
__raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
__raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
__raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
__raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
__raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
__raw_writel(CONFIG_SYS_DDR_CONTROL2, &ddr->sdram_cfg_2);
__raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
__raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
__raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
__raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
__raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
__raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
__raw_writel(CONFIG_SYS_DDR_ZQ_CNTL, &ddr->ddr_zq_cntl);
__raw_writel(CONFIG_SYS_DDR_WRLVL_CNTL, &ddr->ddr_wrlvl_cntl);
__raw_writel(CONFIG_SYS_DDR_CDR_1, &ddr->ddr_cdr1);
__raw_writel(CONFIG_SYS_DDR_CDR_2, &ddr->ddr_cdr2);
/* Set, but do not enable the memory */
__raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
asm volatile("sync;isync");
udelay(500);
/* Let the controller go */
out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
}
void board_init_f(ulong bootflag)
{
u32 plat_ratio, bus_clk;
u32 plat_ratio;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
/* initialize selected port with appropriate baud rate */
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
plat_ratio >>= 1;
bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
bus_clk / 16 / CONFIG_BAUDRATE);
gd->bus_clk / 16 / CONFIG_BAUDRATE);
puts("\nNAND boot... ");
/* Initialize the DDR3 */

6
nand_spl/board/freescale/p1_p2_rdb_pc/Makefile
View File

@ -39,7 +39,8 @@ CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o resetvec.o
COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o \
../common.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
@ -119,6 +120,9 @@ ifneq ($(OBJTREE), $(SRCTREE))
$(obj)nand_boot.c:
@rm -f $(obj)nand_boot.c
ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
$(obj)../common.c:
@rm -f $(obj)../common.c
ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c
endif
#########################################################################

60
nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c
View File

@ -25,11 +25,9 @@
#include <nand.h>
#include <asm/fsl_law.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/global_data.h>
#define udelay(x) {int i, j; \
for (i = 0; i < x; i++) \
for (j = 0; j < 10000; j++) \
; }
DECLARE_GLOBAL_DATA_PTR;
/*
* Fixed sdram init -- doesn't use serial presence detect.
@ -38,32 +36,32 @@ void sdram_init(void)
{
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
out_be32(&ddr->cs1_bnds, CONFIG_SYS_DDR_CS1_BNDS);
out_be32(&ddr->cs1_config, CONFIG_SYS_DDR_CS1_CONFIG);
__raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
__raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
#endif
out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
__raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
__raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
__raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
__raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL_2);
out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1);
out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2);
__raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
__raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
__raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL);
out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL);
__raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
__raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CONTROL);
out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CONTROL);
__raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
__raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
__raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl);
/* Set, but do not enable the memory */
out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN);
__raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
asm volatile("sync;isync");
udelay(500);
@ -76,7 +74,7 @@ void sdram_init(void)
void board_init_f(ulong bootflag)
{
u32 plat_ratio, bus_clk;
u32 plat_ratio;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
#ifndef CONFIG_QE
ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
@ -85,22 +83,22 @@ void board_init_f(ulong bootflag)
/* initialize selected port with appropriate baud rate */
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
plat_ratio >>= 1;
bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
bus_clk / 16 / CONFIG_BAUDRATE);
gd->bus_clk / 16 / CONFIG_BAUDRATE);
puts("\nNAND boot... ");
#ifndef CONFIG_QE
/* init DDR3 reset signal */
out_be32(&pgpio->gpdir, 0x02000000);
out_be32(&pgpio->gpodr, 0x00200000);
out_be32(&pgpio->gpdat, 0x00000000);
__raw_writel(0x02000000, &pgpio->gpdir);
__raw_writel(0x00200000, &pgpio->gpodr);
__raw_writel(0x00000000, &pgpio->gpdat);
udelay(1000);
out_be32(&pgpio->gpdat, 0x00200000);
__raw_writel(0x00200000, &pgpio->gpdat);
udelay(1000);
out_be32(&pgpio->gpdir, 0x00000000);
__raw_writel(0x00000000, &pgpio->gpdir);
#endif
/* Initialize the DDR3 */

47
nand_spl/nand_boot_fsl_elbc.c
View File

@ -66,39 +66,42 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
if (large) {
fmr |= FMR_ECCM;
out_be32(&regs->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
(NAND_CMD_READSTART << FCR_CMD1_SHIFT));
out_be32(&regs->fir,
(FIR_OP_CW0 << FIR_OP0_SHIFT) |
(FIR_OP_CA << FIR_OP1_SHIFT) |
(FIR_OP_PA << FIR_OP2_SHIFT) |
(FIR_OP_CW1 << FIR_OP3_SHIFT) |
(FIR_OP_RBW << FIR_OP4_SHIFT));
__raw_writel((NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
(NAND_CMD_READSTART << FCR_CMD1_SHIFT),
&regs->fcr);
__raw_writel(
(FIR_OP_CW0 << FIR_OP0_SHIFT) |
(FIR_OP_CA << FIR_OP1_SHIFT) |
(FIR_OP_PA << FIR_OP2_SHIFT) |
(FIR_OP_CW1 << FIR_OP3_SHIFT) |
(FIR_OP_RBW << FIR_OP4_SHIFT),
&regs->fir);
} else {
out_be32(&regs->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
out_be32(&regs->fir,
(FIR_OP_CW0 << FIR_OP0_SHIFT) |
(FIR_OP_CA << FIR_OP1_SHIFT) |
(FIR_OP_PA << FIR_OP2_SHIFT) |
(FIR_OP_RBW << FIR_OP3_SHIFT));
__raw_writel(NAND_CMD_READ0 << FCR_CMD0_SHIFT, &regs->fcr);
__raw_writel(
(FIR_OP_CW0 << FIR_OP0_SHIFT) |
(FIR_OP_CA << FIR_OP1_SHIFT) |
(FIR_OP_PA << FIR_OP2_SHIFT) |
(FIR_OP_RBW << FIR_OP3_SHIFT),
&regs->fir);
}
out_be32(&regs->fbcr, 0);
clrsetbits_be32(&regs->bank[0].br, BR_DECC, BR_DECC_CHK_GEN);
__raw_writel(0, &regs->fbcr);
while (pos < uboot_size) {
int i = 0;
out_be32(&regs->fbar, offs >> block_shift);
__raw_writel(offs >> block_shift, &regs->fbar);
do {
int j;
unsigned int page_offs = (offs & (block_size - 1)) << 1;
out_be32(&regs->ltesr, ~0);
out_be32(&regs->lteatr, 0);
out_be32(&regs->fpar, page_offs);
out_be32(&regs->fmr, fmr);
out_be32(&regs->lsor, 0);
__raw_writel(~0, &regs->ltesr);
__raw_writel(0, &regs->lteatr);
__raw_writel(page_offs, &regs->fpar);
__raw_writel(fmr, &regs->fmr);
sync();
__raw_writel(0, &regs->lsor);
nand_wait();
page_offs %= WINDOW_SIZE;

2
tools/Makefile
View File

@ -92,6 +92,7 @@ OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o
OBJ_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes.o
NOPED_OBJ_FILES-y += aisimage.o
NOPED_OBJ_FILES-y += kwbimage.o
NOPED_OBJ_FILES-y += pblimage.o
NOPED_OBJ_FILES-y += imximage.o
NOPED_OBJ_FILES-y += omapimage.o
NOPED_OBJ_FILES-y += mkenvimage.o
@ -208,6 +209,7 @@ $(obj)mkimage$(SFX): $(obj)aisimage.o \
$(obj)image.o \
$(obj)imximage.o \
$(obj)kwbimage.o \
$(obj)pblimage.o \
$(obj)md5.o \
$(obj)mkimage.o \
$(obj)os_support.o \

15
tools/mkimage.c
View File

@ -39,6 +39,7 @@ struct mkimage_params params = {
.comp = IH_COMP_GZIP,
.dtc = MKIMAGE_DEFAULT_DTC_OPTIONS,
.imagename = "",
.imagename2 = "",
};
/*
@ -150,6 +151,8 @@ main (int argc, char **argv)
int retval = 0;
struct image_type_params *tparams = NULL;
/* Init Freescale PBL Boot image generation/list support */
init_pbl_image_type();
/* Init Kirkwood Boot image generation/list support */
init_kwb_image_type ();
/* Init Freescale imx Boot image generation/list support */
@ -250,6 +253,15 @@ main (int argc, char **argv)
usage ();
params.imagename = *++argv;
goto NXTARG;
case 'R':
if (--argc <= 0)
usage();
/*
* This entry is for the second configuration
* file, if only one is not enough.
*/
params.imagename2 = *++argv;
goto NXTARG;
case 's':
params.skipcpy = 1;
break;
@ -440,6 +452,9 @@ NXTARG: ;
break;
}
}
} else if (params.type == IH_TYPE_PBLIMAGE) {
/* PBL has special Image format, implements its' own */
pbl_load_uboot(ifd, &params);
} else {
copy_file (ifd, params.datafile, 0);
}

3
tools/mkimage.h
View File

@ -69,6 +69,7 @@ struct mkimage_params {
unsigned int addr;
unsigned int ep;
char *imagename;
char *imagename2;
char *datafile;
char *imagefile;
char *cmdname;
@ -147,6 +148,8 @@ void mkimage_register (struct image_type_params *tparams);
*
* Supported image types init functions
*/
void pbl_load_uboot(int fd, struct mkimage_params *mparams);
void init_pbl_image_type(void);
void init_ais_image_type(void);
void init_kwb_image_type (void);
void init_imx_image_type (void);

331
tools/pblimage.c 100644
View File

@ -0,0 +1,331 @@
/*
* Copyright 2012 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#define _GNU_SOURCE
#include "mkimage.h"
#include <image.h>
#include "pblimage.h"
/*
* The PBL can load up to 64 bytes at a time, so we split the U-Boot
* image into 64 byte chunks. PBL needs a command for each piece, of
* the form "81xxxxxx", where "xxxxxx" is the offset. SYS_TEXT_BASE
* is 0xFFF80000 for PBL boot, and PBL only cares about low 24-bit,
* so it starts from 0x81F80000.
*/
static uint32_t next_pbl_cmd = 0x81F80000;
/*
* need to store all bytes in memory for calculating crc32, then write the
* bytes to image file for PBL boot.
*/
static unsigned char mem_buf[600000];
static unsigned char *pmem_buf = mem_buf;
static int pbl_size;
static char *fname = "Unknown";
static int lineno = -1;
static struct pbl_header pblimage_header;
static union
{
char c[4];
unsigned char l;
} endian_test = { {'l', '?', '?', 'b'} };
#define ENDIANNESS ((char)endian_test.l)
static void generate_pbl_cmd(void)
{
uint32_t val = next_pbl_cmd;
next_pbl_cmd += 0x40;
int i;
for (i = 3; i >= 0; i--) {
*pmem_buf++ = (val >> (i * 8)) & 0xff;
pbl_size++;
}
}
static void pbl_fget(size_t size, FILE *stream)
{
unsigned char c;
int c_temp;
while (size && (c_temp = fgetc(stream)) != EOF) {
c = (unsigned char)c_temp;
*pmem_buf++ = c;
pbl_size++;
size--;
}
}
/* load split u-boot with PBI command 81xxxxxx. */
static void load_uboot(FILE *fp_uboot)
{
while (next_pbl_cmd < 0x82000000) {
generate_pbl_cmd();
pbl_fget(64, fp_uboot);
}
}
static void check_get_hexval(char *token)
{
uint32_t hexval;
int i;
if (!sscanf(token, "%x", &hexval)) {
printf("Error:%s[%d] - Invalid hex data(%s)\n", fname,
lineno, token);
exit(EXIT_FAILURE);
}
for (i = 3; i >= 0; i--) {
*pmem_buf++ = (hexval >> (i * 8)) & 0xff;
pbl_size++;
}
}
static void pbl_parser(char *name)
{
FILE *fd = NULL;
char *line = NULL;
char *token, *saveptr1, *saveptr2;
size_t len = 0;
fname = name;
fd = fopen(name, "r");
if (fd == NULL) {
printf("Error:%s - Can't open\n", fname);
exit(EXIT_FAILURE);
}
while ((getline(&line, &len, fd)) > 0) {
lineno++;
token = strtok_r(line, "\r\n", &saveptr1);
/* drop all lines with zero tokens (= empty lines) */
if (token == NULL)
continue;
for (line = token;; line = NULL) {
token = strtok_r(line, " \t", &saveptr2);
if (token == NULL)
break;
/* Drop all text starting with '#' as comments */
if (token[0] == '#')
break;
check_get_hexval(token);
}
}
if (line)
free(line);
fclose(fd);
}
static uint32_t crc_table[256];
static void make_crc_table(void)
{
uint32_t mask;
int i, j;
uint32_t poly; /* polynomial exclusive-or pattern */
/*
* the polynomial used by PBL is 1 + x1 + x2 + x4 + x5 + x7 + x8 + x10
* + x11 + x12 + x16 + x22 + x23 + x26 + x32.
*/
poly = 0x04c11db7;
for (i = 0; i < 256; i++) {
mask = i << 24;
for (j = 0; j < 8; j++) {
if (mask & 0x80000000)
mask = (mask << 1) ^ poly;
else
mask <<= 1;
}
crc_table[i] = mask;
}
}
unsigned long pbl_crc32(unsigned long crc, const char *buf, uint32_t len)
{
uint32_t crc32_val = 0xffffffff;
uint32_t xor = 0x0;
int i;
make_crc_table();
for (i = 0; i < len; i++)
crc32_val = (crc32_val << 8) ^
crc_table[(crc32_val >> 24) ^ (*buf++ & 0xff)];
crc32_val = crc32_val ^ xor;
if (crc32_val < 0) {
crc32_val += 0xffffffff;
crc32_val += 1;
}
return crc32_val;
}
static uint32_t reverse_byte(uint32_t val)
{
uint32_t temp;
unsigned char *p1;
int j;
temp = val;
p1 = (unsigned char *)&temp;
for (j = 3; j >= 0; j--)
*p1++ = (val >> (j * 8)) & 0xff;
return temp;
}
/* write end command and crc command to memory. */
static void add_end_cmd(void)
{
uint32_t pbl_end_cmd[4] = {0x09138000, 0x00000000,
0x091380c0, 0x00000000};
uint32_t crc32_pbl;
int i;
unsigned char *p = (unsigned char *)&pbl_end_cmd;
if (ENDIANNESS == 'l') {
for (i = 0; i < 4; i++)
pbl_end_cmd[i] = reverse_byte(pbl_end_cmd[i]);
}
for (i = 0; i < 16; i++) {
*pmem_buf++ = *p++;
pbl_size++;
}
/* Add PBI CRC command. */
*pmem_buf++ = 0x08;
*pmem_buf++ = 0x13;
*pmem_buf++ = 0x80;
*pmem_buf++ = 0x40;
pbl_size += 4;
/* calculated CRC32 and write it to memory. */
crc32_pbl = pbl_crc32(0, (const char *)mem_buf, pbl_size);
*pmem_buf++ = (crc32_pbl >> 24) & 0xff;
*pmem_buf++ = (crc32_pbl >> 16) & 0xff;
*pmem_buf++ = (crc32_pbl >> 8) & 0xff;
*pmem_buf++ = (crc32_pbl) & 0xff;
pbl_size += 4;
if ((pbl_size % 16) != 0) {
for (i = 0; i < 8; i++) {
*pmem_buf++ = 0x0;
pbl_size++;
}
}
if ((pbl_size % 16 != 0)) {
printf("Error: Bad size of image file\n");
exit(EXIT_FAILURE);
}
}
void pbl_load_uboot(int ifd, struct mkimage_params *params)
{
FILE *fp_uboot;
int size;
/* parse the rcw.cfg file. */
pbl_parser(params->imagename);
/* parse the pbi.cfg file. */
pbl_parser(params->imagename2);
fp_uboot = fopen(params->datafile, "r");
if (fp_uboot == NULL) {
printf("Error: %s open failed\n", params->datafile);
exit(EXIT_FAILURE);
}
load_uboot(fp_uboot);
add_end_cmd();
fclose(fp_uboot);
lseek(ifd, 0, SEEK_SET);
size = pbl_size;
if (write(ifd, (const void *)&mem_buf, size) != size) {
fprintf(stderr, "Write error on %s: %s\n",
params->imagefile, strerror(errno));
exit(EXIT_FAILURE);
}
}
static int pblimage_check_image_types(uint8_t type)
{
if (type == IH_TYPE_PBLIMAGE)
return EXIT_SUCCESS;
else
return EXIT_FAILURE;
}
static int pblimage_verify_header(unsigned char *ptr, int image_size,
struct mkimage_params *params)
{
struct pbl_header *pbl_hdr = (struct pbl_header *) ptr;
/* Only a few checks can be done: search for magic numbers */
if (ENDIANNESS == 'l') {
if (pbl_hdr->preamble != reverse_byte(RCW_PREAMBLE))
return -FDT_ERR_BADSTRUCTURE;
if (pbl_hdr->rcwheader != reverse_byte(RCW_HEADER))
return -FDT_ERR_BADSTRUCTURE;
} else {
if (pbl_hdr->preamble != RCW_PREAMBLE)
return -FDT_ERR_BADSTRUCTURE;
if (pbl_hdr->rcwheader != RCW_HEADER)
return -FDT_ERR_BADSTRUCTURE;
}
return 0;
}
static void pblimage_print_header(const void *ptr)
{
printf("Image Type: Freescale PBL Boot Image\n");
}
static void pblimage_set_header(void *ptr, struct stat *sbuf, int ifd,
struct mkimage_params *params)
{
/*nothing need to do, pbl_load_uboot takes care of whole file. */
}
/* pblimage parameters */
static struct image_type_params pblimage_params = {
.name = "Freescale PBL Boot Image support",
.header_size = sizeof(struct pbl_header),
.hdr = (void *)&pblimage_header,
.check_image_type = pblimage_check_image_types,
.verify_header = pblimage_verify_header,
.print_header = pblimage_print_header,
.set_header = pblimage_set_header,
};
void init_pbl_image_type(void)
{
pbl_size = 0;
mkimage_register(&pblimage_params);
}

26
board/freescale/p3060qds/p3060qds.h → tools/pblimage.h
View File

@ -1,5 +1,8 @@
/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2012 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@ -8,7 +11,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@ -17,14 +20,17 @@
* MA 02111-1307 USA
*/
#ifndef __P3060QDS_H__
#define __P3060QDS_H__
#ifndef PBLIMAGE_H
#define PBLIMAGE_H
#include <asm/fsl_ddr_sdram.h>
#include <asm/u-boot.h>
#define RCW_BYTES 64
#define RCW_PREAMBLE 0xaa55aa55
#define RCW_HEADER 0x010e0100
void fdt_fixup_board_enet(void *blob);
void pci_of_setup(void *blob, bd_t *bd);
extern fixed_ddr_parm_t fixed_ddr_parm_0[];
struct pbl_header {
uint32_t preamble;
uint32_t rcwheader;
uint8_t rcw_data[RCW_BYTES];
};
#endif
#endif /* PBLIMAGE_H */