diff --git a/drivers/mmc/mv_sdhci.c b/drivers/mmc/mv_sdhci.c
index 75fa014931..82c695f906 100644
--- a/drivers/mmc/mv_sdhci.c
+++ b/drivers/mmc/mv_sdhci.c
@@ -1,6 +1,41 @@
+/*
+ * Marvell SD Host Controller Interface
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
 #include <common.h>
 #include <malloc.h>
 #include <sdhci.h>
+#include <linux/mbus.h>
+
+#define SDHCI_WINDOW_CTRL(win)		(0x4080 + ((win) << 4))
+#define SDHCI_WINDOW_BASE(win)		(0x4084 + ((win) << 4))
+
+static void sdhci_mvebu_mbus_config(void __iomem *base)
+{
+	const struct mbus_dram_target_info *dram;
+	int i;
+
+	dram = mvebu_mbus_dram_info();
+
+	for (i = 0; i < 4; i++) {
+		writel(0, base + SDHCI_WINDOW_CTRL(i));
+		writel(0, base + SDHCI_WINDOW_BASE(i));
+	}
+
+	for (i = 0; i < dram->num_cs; i++) {
+		const struct mbus_dram_window *cs = dram->cs + i;
+
+		/* Write size, attributes and target id to control register */
+		writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
+		       (dram->mbus_dram_target_id << 4) | 1,
+		       base + SDHCI_WINDOW_CTRL(i));
+
+		/* Write base address to base register */
+		writel(cs->base, base + SDHCI_WINDOW_BASE(i));
+	}
+}
 
 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
 static struct sdhci_ops mv_ops;
@@ -47,6 +82,12 @@ int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks)
 	mv_ops.write_b = mv_sdhci_writeb;
 	host->ops = &mv_ops;
 #endif
+
+	if (CONFIG_IS_ENABLED(ARCH_MVEBU)) {
+		/* Configure SDHCI MBUS mbus bridge windows */
+		sdhci_mvebu_mbus_config((void __iomem *)regbase);
+	}
+
 	if (quirks & SDHCI_QUIRK_REG32_RW)
 		host->version = sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
 	else