wandboard: Add support for Carrier Board MicroSD card
Allow use of the carrier board MicroSD card available in the Wandboard; this allow for loading alternative system from the other card for testing or upgrade proposes. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
This commit is contained in:
parent
08f32f7d25
commit
5ed15738d9
|
@ -76,6 +76,7 @@ enum {
|
||||||
MX6_PAD_GPIO_17__GPIO_7_12 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0),
|
MX6_PAD_GPIO_17__GPIO_7_12 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0),
|
||||||
MX6_PAD_GPIO_18__GPIO_7_13 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0),
|
MX6_PAD_GPIO_18__GPIO_7_13 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0),
|
||||||
MX6_PAD_GPIO_19__GPIO_4_5 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0),
|
MX6_PAD_GPIO_19__GPIO_4_5 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0),
|
||||||
|
MX6_PAD_GPIO_2__GPIO_1_2 = IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0),
|
||||||
MX6_PAD_GPIO_5__GPIO_1_5 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0),
|
MX6_PAD_GPIO_5__GPIO_1_5 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0),
|
||||||
MX6_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0),
|
MX6_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0),
|
||||||
MX6_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0),
|
MX6_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0),
|
||||||
|
@ -108,8 +109,14 @@ enum {
|
||||||
MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0),
|
MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0),
|
||||||
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0),
|
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0),
|
||||||
MX6_PAD_RGMII_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0),
|
MX6_PAD_RGMII_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0),
|
||||||
|
MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0928, 1, 0),
|
||||||
|
MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x06C8, 0x02E0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
|
||||||
MX6_PAD_SD1_CMD__GPIO_1_18 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0),
|
MX6_PAD_SD1_CMD__GPIO_1_18 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0),
|
||||||
MX6_PAD_SD1_DAT3__GPIO_1_21 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0),
|
MX6_PAD_SD1_DAT3__GPIO_1_21 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0),
|
||||||
|
MX6_PAD_SD1_DAT0__USDHC1_DAT0 = IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0),
|
||||||
|
MX6_PAD_SD1_DAT1__USDHC1_DAT1 = IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0),
|
||||||
|
MX6_PAD_SD1_DAT2__USDHC1_DAT2 = IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0),
|
||||||
|
MX6_PAD_SD1_DAT3__USDHC1_DAT3 = IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0),
|
||||||
MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, 0),
|
MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, 0),
|
||||||
MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
|
MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
|
||||||
MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0),
|
MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0),
|
||||||
|
|
|
@ -38,6 +38,7 @@ DECLARE_GLOBAL_DATA_PTR;
|
||||||
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||||
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
|
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
|
||||||
|
|
||||||
|
#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2)
|
||||||
#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9)
|
#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9)
|
||||||
#define ETH_PHY_RESET IMX_GPIO_NR(3, 29)
|
#define ETH_PHY_RESET IMX_GPIO_NR(3, 29)
|
||||||
|
|
||||||
|
@ -53,6 +54,17 @@ static iomux_v3_cfg_t const uart1_pads[] = {
|
||||||
MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||||
};
|
};
|
||||||
|
|
||||||
|
iomux_v3_cfg_t const usdhc1_pads[] = {
|
||||||
|
MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||||
|
MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||||
|
MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||||
|
MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||||
|
MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||||
|
MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||||
|
/* Carrier MicroSD Card Detect */
|
||||||
|
MX6_PAD_GPIO_2__GPIO_1_2 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||||
|
};
|
||||||
|
|
||||||
static iomux_v3_cfg_t const usdhc3_pads[] = {
|
static iomux_v3_cfg_t const usdhc3_pads[] = {
|
||||||
MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||||
MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||||
|
@ -99,8 +111,9 @@ static void setup_iomux_enet(void)
|
||||||
gpio_set_value(ETH_PHY_RESET, 1);
|
gpio_set_value(ETH_PHY_RESET, 1);
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct fsl_esdhc_cfg usdhc_cfg[1] = {
|
static struct fsl_esdhc_cfg usdhc_cfg[2] = {
|
||||||
{USDHC3_BASE_ADDR},
|
{USDHC3_BASE_ADDR},
|
||||||
|
{USDHC1_BASE_ADDR},
|
||||||
};
|
};
|
||||||
|
|
||||||
int board_mmc_getcd(struct mmc *mmc)
|
int board_mmc_getcd(struct mmc *mmc)
|
||||||
|
@ -109,6 +122,9 @@ int board_mmc_getcd(struct mmc *mmc)
|
||||||
int ret = 0;
|
int ret = 0;
|
||||||
|
|
||||||
switch (cfg->esdhc_base) {
|
switch (cfg->esdhc_base) {
|
||||||
|
case USDHC1_BASE_ADDR:
|
||||||
|
ret = !gpio_get_value(USDHC1_CD_GPIO);
|
||||||
|
break;
|
||||||
case USDHC3_BASE_ADDR:
|
case USDHC3_BASE_ADDR:
|
||||||
ret = !gpio_get_value(USDHC3_CD_GPIO);
|
ret = !gpio_get_value(USDHC3_CD_GPIO);
|
||||||
break;
|
break;
|
||||||
|
@ -119,13 +135,42 @@ int board_mmc_getcd(struct mmc *mmc)
|
||||||
|
|
||||||
int board_mmc_init(bd_t *bis)
|
int board_mmc_init(bd_t *bis)
|
||||||
{
|
{
|
||||||
imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
|
s32 status = 0;
|
||||||
|
u32 index = 0;
|
||||||
|
|
||||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
/*
|
||||||
usdhc_cfg[0].max_bus_width = 4;
|
* Following map is done:
|
||||||
gpio_direction_input(USDHC3_CD_GPIO);
|
* (U-boot device node) (Physical Port)
|
||||||
|
* mmc0 SOM MicroSD
|
||||||
|
* mmc1 Carrier board MicroSD
|
||||||
|
*/
|
||||||
|
for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
|
||||||
|
switch (index) {
|
||||||
|
case 0:
|
||||||
|
imx_iomux_v3_setup_multiple_pads(
|
||||||
|
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
|
||||||
|
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
||||||
|
usdhc_cfg[0].max_bus_width = 4;
|
||||||
|
gpio_direction_input(USDHC3_CD_GPIO);
|
||||||
|
break;
|
||||||
|
case 1:
|
||||||
|
imx_iomux_v3_setup_multiple_pads(
|
||||||
|
usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
|
||||||
|
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||||
|
usdhc_cfg[1].max_bus_width = 4;
|
||||||
|
gpio_direction_input(USDHC1_CD_GPIO);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
printf("Warning: you configured more USDHC controllers"
|
||||||
|
"(%d) then supported by the board (%d)\n",
|
||||||
|
index + 1, CONFIG_SYS_FSL_USDHC_NUM);
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
|
status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
|
||||||
|
}
|
||||||
|
|
||||||
|
return status;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int mx6_rgmii_rework(struct phy_device *phydev)
|
static int mx6_rgmii_rework(struct phy_device *phydev)
|
||||||
|
|
|
@ -59,6 +59,7 @@
|
||||||
/* MMC Configuration */
|
/* MMC Configuration */
|
||||||
#define CONFIG_FSL_ESDHC
|
#define CONFIG_FSL_ESDHC
|
||||||
#define CONFIG_FSL_USDHC
|
#define CONFIG_FSL_USDHC
|
||||||
|
#define CONFIG_SYS_FSL_USDHC_NUM 2
|
||||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||||
|
|
||||||
#define CONFIG_MMC
|
#define CONFIG_MMC
|
||||||
|
|
Loading…
Reference in a new issue