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board: ti: am57xx: Update EMIF SDRAM 1 and 3 Timings 

Update EMIF data based on recommendations from the now standard TI
EMIF tool version 1.1.1 based on 256MBx16 DDR3L Kingston D2516EC4BXGGB
data sheet

Update T_RRD from 5 to 6 based on AM57xx TRM -
Minimum number of DDR cycles from activate to ativate for a different
bank, minus 1.

Update T_CKESR from 4 to 3 based on AM57xx TRM - Minimum number of DDR
clocks cycles for which SDRAM must remain in self refresh, minus 1.

Signed-off-by: Schuyler Patton <spatton@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
utp
Schuyler Patton 2016-04-08 16:53:44 -05:00 committed by Tom Rini
parent 7e52e11f35
commit 5f405e7fa0
1 changed files with 2 additions and 2 deletions
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4
board/ti/am57xx/board.c
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@ -131,9 +131,9 @@ static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xcccf36ab,
.sdram_tim1 = 0xcccf36b3,
.sdram_tim2 = 0x308f7fda,
.sdram_tim3 = 0x409f88a8,
.sdram_tim3 = 0x407f88a8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190b,
.temp_alert_config = 0x00000000,