arm: mvebu: Add basic support for Armada 375 eval board db-88f6720
This patch adds basic support for the Marvell A375 eval board. Tested are the following interfaces: - I2C - SPI - SPI NOR - Ethernet (mvpp2), port 0 & 1 Currently the A375 SerDes and DDR3 init code is not intergrated. So the SPL U-Boot is not fully functional. Right now, this A375 mainline U-Boot can only be used by chainloading it via the original Marvell U-Boot. This can be done via this command: => tftpboot 00800000 a375/u-boot-dtb.bin;go 00800000 Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>utp
Stefan Roese
parent
09e89ab4af
commit
606576d54b
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@ -115,7 +115,7 @@ config KIRKWOOD
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select CPU_ARM926EJS
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config ARCH_MVEBU
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bool "Marvell MVEBU family (Armada XP/38x)"
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bool "Marvell MVEBU family (Armada XP/375/38x)"
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select CPU_V7
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select SUPPORT_SPL
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select OF_CONTROL
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@ -49,6 +49,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
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tegra210-p2571.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += \
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armada-375-db.dtb \
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armada-388-clearfog.dtb \
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armada-388-gp.dtb \
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armada-xp-gp.dtb \
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@ -0,0 +1,216 @@
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/*
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* Device Tree file for Marvell Armada 375 evaluation board
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* (DB-88F6720)
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*
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* Copyright (C) 2014 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "armada-375.dtsi"
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/ {
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model = "Marvell Armada 375 Development Board";
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compatible = "marvell,a375-db", "marvell,armada375";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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aliases {
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/* So that mvebu u-boot can update the MAC addresses */
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ethernet0 = ð0;
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ethernet1 = ð1;
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spi0 = &spi0;
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x40000000>; /* 1 GB */
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};
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
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MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000
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MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>;
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internal-regs {
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spi@10600 {
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pinctrl-0 = <&spi0_pins>;
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pinctrl-names = "default";
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/*
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* SPI conflicts with NAND, so we disable it
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* here, and select NAND as the enabled device
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* by default.
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*/
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status = "okay";
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u-boot,dm-pre-reloc;
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spi-flash@0 {
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u-boot,dm-pre-reloc;
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "n25q128a13", "jedec,spi-nor";
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reg = <0>; /* Chip select 0 */
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spi-max-frequency = <108000000>;
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};
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};
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i2c@11000 {
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status = "okay";
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clock-frequency = <100000>;
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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};
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i2c@11100 {
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status = "okay";
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clock-frequency = <100000>;
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pinctrl-0 = <&i2c1_pins>;
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pinctrl-names = "default";
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};
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serial@12000 {
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u-boot,dm-pre-reloc;
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status = "okay";
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};
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pinctrl {
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sdio_st_pins: sdio-st-pins {
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marvell,pins = "mpp44", "mpp45";
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marvell,function = "gpio";
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};
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};
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sata@a0000 {
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status = "okay";
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nr-ports = <2>;
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};
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nand: nand@d0000 {
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pinctrl-0 = <&nand_pins>;
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pinctrl-names = "default";
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status = "okay";
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num-cs = <1>;
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marvell,nand-keep-config;
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marvell,nand-enable-arbiter;
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nand-on-flash-bbt;
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nand-ecc-strength = <4>;
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nand-ecc-step-size = <512>;
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partition@0 {
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label = "U-Boot";
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reg = <0 0x800000>;
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};
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partition@800000 {
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label = "Linux";
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reg = <0x800000 0x800000>;
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};
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partition@1000000 {
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label = "Filesystem";
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reg = <0x1000000 0x3f000000>;
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};
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};
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usb@54000 {
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status = "okay";
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};
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usb3@58000 {
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status = "okay";
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};
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mvsdio@d4000 {
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pinctrl-0 = <&sdio_pins &sdio_st_pins>;
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pinctrl-names = "default";
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status = "okay";
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cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
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wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
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};
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mdio {
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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phy3: ethernet-phy@3 {
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reg = <3>;
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};
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};
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ethernet@f0000 {
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status = "okay";
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eth0@c4000 {
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status = "okay";
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phy = <&phy0>;
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phy-mode = "rgmii-id";
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};
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eth1@c5000 {
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status = "okay";
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phy = <&phy3>;
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phy-mode = "gmii";
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};
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};
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};
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pcie-controller {
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status = "okay";
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/*
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* The two PCIe units are accessible through
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* standard PCIe slots on the board.
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*/
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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pcie@2,0 {
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/* Port 1, Lane 0 */
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status = "okay";
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};
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};
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};
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};
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@ -0,0 +1,658 @@
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/*
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* Device Tree Include file for Marvell Armada 375 family SoC
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*
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* Copyright (C) 2014 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/phy/phy.h>
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#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
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/ {
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model = "Marvell Armada 375 family SoC";
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compatible = "marvell,armada375";
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aliases {
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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gpio2 = &gpio2;
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serial0 = &uart0;
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serial1 = &uart1;
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};
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clocks {
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/* 2 GHz fixed main PLL */
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mainpll: mainpll {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <1000000000>;
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};
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/* 25 MHz reference crystal */
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refclk: oscillator {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "marvell,armada-375-smp";
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <1>;
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};
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};
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts-extended = <&mpic 3>;
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};
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soc {
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compatible = "marvell,armada375-mbus", "simple-bus";
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u-boot,dm-pre-reloc;
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#address-cells = <2>;
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#size-cells = <1>;
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controller = <&mbusc>;
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interrupt-parent = <&gic>;
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pcie-mem-aperture = <0xe0000000 0x8000000>;
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pcie-io-aperture = <0xe8000000 0x100000>;
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bootrom {
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compatible = "marvell,bootrom";
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reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
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};
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devbus-bootcs {
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compatible = "marvell,mvebu-devbus";
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reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
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ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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devbus-cs0 {
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compatible = "marvell,mvebu-devbus";
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reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
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ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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devbus-cs1 {
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compatible = "marvell,mvebu-devbus";
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reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
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ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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devbus-cs2 {
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compatible = "marvell,mvebu-devbus";
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reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
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ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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devbus-cs3 {
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compatible = "marvell,mvebu-devbus";
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reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
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ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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internal-regs {
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compatible = "simple-bus";
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u-boot,dm-pre-reloc;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
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L2: cache-controller@8000 {
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compatible = "arm,pl310-cache";
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reg = <0x8000 0x1000>;
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cache-unified;
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cache-level = <2>;
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arm,double-linefill-incr = <1>;
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arm,double-linefill-wrap = <0>;
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arm,double-linefill = <1>;
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prefetch-data = <1>;
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};
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scu@c000 {
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compatible = "arm,cortex-a9-scu";
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reg = <0xc000 0x58>;
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};
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timer@c600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0xc600 0x20>;
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interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
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clocks = <&coreclk 2>;
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};
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gic: interrupt-controller@d000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#size-cells = <0>;
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interrupt-controller;
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reg = <0xd000 0x1000>,
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<0xc100 0x100>;
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "marvell,orion-mdio";
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reg = <0xc0054 0x4>;
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clocks = <&gateclk 19>;
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};
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/* Network controller */
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ethernet@f0000 {
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compatible = "marvell,armada-375-pp2";
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reg = <0xf0000 0xa000>, /* Packet Processor regs */
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<0xc0000 0x3060>, /* LMS regs */
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<0xc4000 0x100>, /* eth0 regs */
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<0xc5000 0x100>; /* eth1 regs */
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clocks = <&gateclk 3>, <&gateclk 19>;
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clock-names = "pp_clk", "gop_clk";
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status = "disabled";
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eth0: eth0@c4000 {
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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port-id = <0>;
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status = "disabled";
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};
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eth1: eth1@c5000 {
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interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
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port-id = <1>;
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status = "disabled";
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};
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};
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rtc@10300 {
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compatible = "marvell,orion-rtc";
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reg = <0x10300 0x20>;
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interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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};
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|
||||
spi0: spi@10600 {
|
||||
compatible = "marvell,armada-375-spi",
|
||||
"marvell,orion-spi";
|
||||
reg = <0x10600 0x50>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@10680 {
|
||||
compatible = "marvell,armada-375-spi",
|
||||
"marvell,orion-spi";
|
||||
reg = <0x10680 0x50>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@11000 {
|
||||
compatible = "marvell,mv64xxx-i2c";
|
||||
reg = <0x11000 0x20>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
timeout-ms = <1000>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@11100 {
|
||||
compatible = "marvell,mv64xxx-i2c";
|
||||
reg = <0x11100 0x20>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
timeout-ms = <1000>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: serial@12000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x12000 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@12100 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x12100 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pinctrl {
|
||||
compatible = "marvell,mv88f6720-pinctrl";
|
||||
reg = <0x18000 0x24>;
|
||||
|
||||
i2c0_pins: i2c0-pins {
|
||||
marvell,pins = "mpp14", "mpp15";
|
||||
marvell,function = "i2c0";
|
||||
};
|
||||
|
||||
i2c1_pins: i2c1-pins {
|
||||
marvell,pins = "mpp61", "mpp62";
|
||||
marvell,function = "i2c1";
|
||||
};
|
||||
|
||||
nand_pins: nand-pins {
|
||||
marvell,pins = "mpp0", "mpp1", "mpp2",
|
||||
"mpp3", "mpp4", "mpp5",
|
||||
"mpp6", "mpp7", "mpp8",
|
||||
"mpp9", "mpp10", "mpp11",
|
||||
"mpp12", "mpp13";
|
||||
marvell,function = "nand";
|
||||
};
|
||||
|
||||
sdio_pins: sdio-pins {
|
||||
marvell,pins = "mpp24", "mpp25", "mpp26",
|
||||
"mpp27", "mpp28", "mpp29";
|
||||
marvell,function = "sd";
|
||||
};
|
||||
|
||||
spi0_pins: spi0-pins {
|
||||
marvell,pins = "mpp0", "mpp1", "mpp4",
|
||||
"mpp5", "mpp8", "mpp9";
|
||||
marvell,function = "spi0";
|
||||
};
|
||||
};
|
||||
|
||||
gpio0: gpio@18100 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18100 0x40>;
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpio1: gpio@18140 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18140 0x40>;
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpio2: gpio@18180 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18180 0x40>;
|
||||
ngpios = <3>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
system-controller@18200 {
|
||||
compatible = "marvell,armada-375-system-controller";
|
||||
reg = <0x18200 0x100>;
|
||||
};
|
||||
|
||||
gateclk: clock-gating-control@18220 {
|
||||
compatible = "marvell,armada-375-gating-clock";
|
||||
reg = <0x18220 0x4>;
|
||||
clocks = <&coreclk 0>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
usbcluster: usb-cluster@18400 {
|
||||
compatible = "marvell,armada-375-usb-cluster";
|
||||
reg = <0x18400 0x4>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
mbusc: mbus-controller@20000 {
|
||||
compatible = "marvell,mbus-controller";
|
||||
reg = <0x20000 0x100>, <0x20180 0x20>;
|
||||
};
|
||||
|
||||
mpic: interrupt-controller@20a00 {
|
||||
compatible = "marvell,mpic";
|
||||
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-controller;
|
||||
msi-controller;
|
||||
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
timer@20300 {
|
||||
compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
|
||||
reg = <0x20300 0x30>, <0x21040 0x30>;
|
||||
interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&mpic 5>,
|
||||
<&mpic 6>;
|
||||
clocks = <&coreclk 0>, <&refclk>;
|
||||
clock-names = "nbclk", "fixed";
|
||||
};
|
||||
|
||||
watchdog@20300 {
|
||||
compatible = "marvell,armada-375-wdt";
|
||||
reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
|
||||
clocks = <&coreclk 0>, <&refclk>;
|
||||
clock-names = "nbclk", "fixed";
|
||||
};
|
||||
|
||||
cpurst@20800 {
|
||||
compatible = "marvell,armada-370-cpu-reset";
|
||||
reg = <0x20800 0x10>;
|
||||
};
|
||||
|
||||
coherency-fabric@21010 {
|
||||
compatible = "marvell,armada-375-coherency-fabric";
|
||||
reg = <0x21010 0x1c>;
|
||||
};
|
||||
|
||||
usb@50000 {
|
||||
compatible = "marvell,orion-ehci";
|
||||
reg = <0x50000 0x500>;
|
||||
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 18>;
|
||||
phys = <&usbcluster PHY_TYPE_USB2>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@54000 {
|
||||
compatible = "marvell,orion-ehci";
|
||||
reg = <0x54000 0x500>;
|
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 26>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb3@58000 {
|
||||
compatible = "marvell,armada-375-xhci";
|
||||
reg = <0x58000 0x20000>,<0x5b880 0x80>;
|
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 16>;
|
||||
phys = <&usbcluster PHY_TYPE_USB3>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
xor@60800 {
|
||||
compatible = "marvell,orion-xor";
|
||||
reg = <0x60800 0x100
|
||||
0x60A00 0x100>;
|
||||
clocks = <&gateclk 22>;
|
||||
status = "okay";
|
||||
|
||||
xor00 {
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
};
|
||||
xor01 {
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
dmacap,memset;
|
||||
};
|
||||
};
|
||||
|
||||
xor@60900 {
|
||||
compatible = "marvell,orion-xor";
|
||||
reg = <0x60900 0x100
|
||||
0x60b00 0x100>;
|
||||
clocks = <&gateclk 23>;
|
||||
status = "okay";
|
||||
|
||||
xor10 {
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
};
|
||||
xor11 {
|
||||
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
dmacap,memset;
|
||||
};
|
||||
};
|
||||
|
||||
crypto@90000 {
|
||||
compatible = "marvell,armada-375-crypto";
|
||||
reg = <0x90000 0x10000>;
|
||||
reg-names = "regs";
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 30>, <&gateclk 31>,
|
||||
<&gateclk 28>, <&gateclk 29>;
|
||||
clock-names = "cesa0", "cesa1",
|
||||
"cesaz0", "cesaz1";
|
||||
marvell,crypto-srams = <&crypto_sram0>,
|
||||
<&crypto_sram1>;
|
||||
marvell,crypto-sram-size = <0x800>;
|
||||
};
|
||||
|
||||
sata@a0000 {
|
||||
compatible = "marvell,orion-sata";
|
||||
reg = <0xa0000 0x5000>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 14>, <&gateclk 20>;
|
||||
clock-names = "0", "1";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nand@d0000 {
|
||||
compatible = "marvell,armada370-nand";
|
||||
reg = <0xd0000 0x54>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 11>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mvsdio@d4000 {
|
||||
compatible = "marvell,orion-sdio";
|
||||
reg = <0xd4000 0x200>;
|
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 17>;
|
||||
bus-width = <4>;
|
||||
cap-sdio-irq;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
thermal@e8078 {
|
||||
compatible = "marvell,armada375-thermal";
|
||||
reg = <0xe8078 0x4>, <0xe807c 0x8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
coreclk: mvebu-sar@e8204 {
|
||||
compatible = "marvell,armada-375-core-clock";
|
||||
reg = <0xe8204 0x04>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
coredivclk: corediv-clock@e8250 {
|
||||
compatible = "marvell,armada-375-corediv-clock";
|
||||
reg = <0xe8250 0xc>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&mainpll>;
|
||||
clock-output-names = "nand";
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
compatible = "marvell,armada-370-pcie";
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
msi-parent = <&mpic>;
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
ranges =
|
||||
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
|
||||
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
|
||||
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
|
||||
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */
|
||||
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
|
||||
0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>;
|
||||
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x2 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <1>;
|
||||
clocks = <&gateclk 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
crypto_sram0: sa-sram0 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
|
||||
clocks = <&gateclk 30>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
|
||||
};
|
||||
|
||||
crypto_sram1: sa-sram1 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
|
||||
clocks = <&gateclk 31>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1,5 +1,8 @@
|
|||
if ARCH_MVEBU
|
||||
|
||||
config ARMADA_375
|
||||
bool
|
||||
|
||||
config ARMADA_38X
|
||||
bool
|
||||
|
||||
|
|
@ -23,13 +26,17 @@ config DB_88F6820_GP
|
|||
select ARMADA_38X
|
||||
|
||||
choice
|
||||
prompt "Marvell MVEBU (Armada XP/38x) board select"
|
||||
prompt "Marvell MVEBU (Armada XP/375/38x) board select"
|
||||
optional
|
||||
|
||||
config TARGET_CLEARFOG
|
||||
bool "Support ClearFog"
|
||||
select DB_88F6820_GP
|
||||
|
||||
config TARGET_DB_88F6720
|
||||
bool "Support DB-88F6720 Armada 375"
|
||||
select ARMADA_375
|
||||
|
||||
config TARGET_DB_88F6820_GP
|
||||
bool "Support DB-88F6820-GP"
|
||||
select DB_88F6820_GP
|
||||
|
|
@ -54,6 +61,7 @@ endchoice
|
|||
|
||||
config SYS_BOARD
|
||||
default "clearfog" if TARGET_CLEARFOG
|
||||
default "db-88f6720" if TARGET_DB_88F6720
|
||||
default "db-88f6820-gp" if TARGET_DB_88F6820_GP
|
||||
default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
|
||||
default "ds414" if TARGET_DS414
|
||||
|
|
@ -62,6 +70,7 @@ config SYS_BOARD
|
|||
|
||||
config SYS_CONFIG_NAME
|
||||
default "clearfog" if TARGET_CLEARFOG
|
||||
default "db-88f6720" if TARGET_DB_88F6720
|
||||
default "db-88f6820-gp" if TARGET_DB_88F6820_GP
|
||||
default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
|
||||
default "ds414" if TARGET_DS414
|
||||
|
|
@ -70,6 +79,7 @@ config SYS_CONFIG_NAME
|
|||
|
||||
config SYS_VENDOR
|
||||
default "Marvell" if TARGET_DB_MV784MP_GP
|
||||
default "Marvell" if TARGET_DB_88F6720
|
||||
default "Marvell" if TARGET_DB_88F6820_GP
|
||||
default "solidrun" if TARGET_CLEARFOG
|
||||
default "Synology" if TARGET_DS414
|
||||
|
|
|
|||
|
|
@ -0,0 +1,6 @@
|
|||
DB_88F6720 BOARD
|
||||
M: Stefan Roese <sr@denx.de>
|
||||
S: Maintained
|
||||
F: board/Marvell/db-88f6720/
|
||||
F: include/configs/db-88f6720.h
|
||||
F: configs/db-88f6720_defconfig
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
#
|
||||
# Copyright (C) 2016 Stefan Roese <sr@denx.de>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y := db-88f6720.o
|
||||
|
|
@ -0,0 +1,91 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Stefan Roese <sr@denx.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <miiphy.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/soc.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/*
|
||||
* Those values and defines are taken from the Marvell U-Boot version
|
||||
* "u-boot-2013.01-2014_T2.0" for the board Armada 375 DB-88F6720
|
||||
*/
|
||||
#define DB_88F6720_MPP0_7 0x00020020 /* SPI */
|
||||
#define DB_88F6720_MPP8_15 0x22000022 /* SPI , I2C */
|
||||
#define DB_88F6720_MPP16_23 0x22222222 /* UART, TDM*/
|
||||
#define DB_88F6720_MPP24_31 0x33333333 /* SDIO, SPI1*/
|
||||
#define DB_88F6720_MPP32_39 0x04403330 /* SPI1, External SMI */
|
||||
#define DB_88F6720_MPP40_47 0x22002044 /* UART1, GE0, SATA0 LED */
|
||||
#define DB_88F6720_MPP48_55 0x22222222 /* GE0 */
|
||||
#define DB_88F6720_MPP56_63 0x04444422 /* GE0 , LED_MATRIX, GPIO */
|
||||
#define DB_88F6720_MPP64_67 0x014 /* LED_MATRIX, SATA1 LED*/
|
||||
|
||||
#define DB_88F6720_GPP_OUT_ENA_LOW 0xFFFFFFFF
|
||||
#define DB_88F6720_GPP_OUT_ENA_MID 0x7FFFFFFF
|
||||
#define DB_88F6720_GPP_OUT_ENA_HIGH 0xFFFFFFFF
|
||||
#define DB_88F6720_GPP_OUT_VAL_LOW 0x0
|
||||
#define DB_88F6720_GPP_OUT_VAL_MID BIT(31) /* SATA Power output enable */
|
||||
#define DB_88F6720_GPP_OUT_VAL_HIGH 0x0
|
||||
#define DB_88F6720_GPP_POL_LOW 0x0
|
||||
#define DB_88F6720_GPP_POL_MID 0x0
|
||||
#define DB_88F6720_GPP_POL_HIGH 0x0
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/* Configure MPP */
|
||||
writel(DB_88F6720_MPP0_7, MVEBU_MPP_BASE + 0x00);
|
||||
writel(DB_88F6720_MPP8_15, MVEBU_MPP_BASE + 0x04);
|
||||
writel(DB_88F6720_MPP16_23, MVEBU_MPP_BASE + 0x08);
|
||||
writel(DB_88F6720_MPP24_31, MVEBU_MPP_BASE + 0x0c);
|
||||
writel(DB_88F6720_MPP32_39, MVEBU_MPP_BASE + 0x10);
|
||||
writel(DB_88F6720_MPP40_47, MVEBU_MPP_BASE + 0x14);
|
||||
writel(DB_88F6720_MPP48_55, MVEBU_MPP_BASE + 0x18);
|
||||
writel(DB_88F6720_MPP56_63, MVEBU_MPP_BASE + 0x1c);
|
||||
writel(DB_88F6720_MPP64_67, MVEBU_MPP_BASE + 0x20);
|
||||
|
||||
/* Configure GPIO */
|
||||
/* Set GPP Out value */
|
||||
writel(DB_88F6720_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
|
||||
writel(DB_88F6720_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
|
||||
writel(DB_88F6720_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
|
||||
|
||||
/* Set GPP Polarity */
|
||||
writel(DB_88F6720_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
|
||||
writel(DB_88F6720_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
|
||||
writel(DB_88F6720_GPP_POL_HIGH, MVEBU_GPIO2_BASE + 0x0c);
|
||||
|
||||
/* Set GPP Out Enable */
|
||||
writel(DB_88F6720_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
|
||||
writel(DB_88F6720_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
|
||||
writel(DB_88F6720_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: Marvell DB-88F6720\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
cpu_eth_init(bis); /* Built in controller(s) come first */
|
||||
return pci_eth_init(bis);
|
||||
}
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
#
|
||||
# Copyright (C) 2014 Stefan Roese <sr@denx.de>
|
||||
#
|
||||
|
||||
# Armada XP uses version 1 image format
|
||||
VERSION 1
|
||||
|
||||
# Boot Media configurations
|
||||
BOOT_FROM spi
|
||||
|
||||
# Binary Header (bin_hdr) with DDR3 training code
|
||||
BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MVEBU=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_TARGET_DB_88F6720=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="armada-375-db"
|
||||
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
|
||||
CONFIG_SPL=y
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_OF_TRANSLATE=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_NAND_PXA3XX=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_MVPP2=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_DEBUG_UART_BASE=0xf1012000
|
||||
CONFIG_DEBUG_UART_CLOCK=250000000
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
|
|
@ -0,0 +1,120 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Stefan Roese <sr@denx.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _CONFIG_DB_88F6720_H
|
||||
#define _CONFIG_DB_88F6720_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options (easy to change)
|
||||
*/
|
||||
#define CONFIG_DISPLAY_BOARDINFO_LATE
|
||||
|
||||
/*
|
||||
* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
|
||||
* for DDR ECC byte filling in the SPL before loading the main
|
||||
* U-Boot into it.
|
||||
*/
|
||||
#define CONFIG_SYS_TEXT_BASE 0x00800000
|
||||
#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
|
||||
|
||||
/*
|
||||
* Commands configuration
|
||||
*/
|
||||
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
|
||||
#define CONFIG_CMD_CACHE
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_ENV
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_EXT4
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_FS_GENERIC
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_CMD_SPI
|
||||
#define CONFIG_CMD_TFTPPUT
|
||||
#define CONFIG_CMD_TIME
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_MVTWSI
|
||||
#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x0
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
|
||||
/* USB/EHCI configuration */
|
||||
#define CONFIG_EHCI_IS_TDI
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
|
||||
|
||||
/* SPI NOR flash default params, used by sf commands */
|
||||
#define CONFIG_SF_DEFAULT_SPEED 1000000
|
||||
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
|
||||
|
||||
/* Environment in SPI NOR flash */
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
|
||||
#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
|
||||
#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
|
||||
|
||||
#define CONFIG_PHY_MARVELL /* there is a marvell phy */
|
||||
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
|
||||
|
||||
#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
|
||||
#define CONFIG_SYS_ALT_MEMTEST
|
||||
|
||||
/* Additional FS support/configuration */
|
||||
#define CONFIG_SUPPORT_VFAT
|
||||
|
||||
/*
|
||||
* mv-common.h should be defined after CMD configs since it used them
|
||||
* to enable certain macros
|
||||
*/
|
||||
#include "mv-common.h"
|
||||
|
||||
/*
|
||||
* Memory layout while starting into the bin_hdr via the
|
||||
* BootROM:
|
||||
*
|
||||
* 0x4000.4000 - 0x4003.4000 headers space (192KiB)
|
||||
* 0x4000.4030 bin_hdr start address
|
||||
* 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
|
||||
* 0x4007.fffc BootROM stack top
|
||||
*
|
||||
* The address space between 0x4007.fffc and 0x400f.fff is not locked in
|
||||
* L2 cache thus cannot be used.
|
||||
*/
|
||||
|
||||
/* SPL */
|
||||
/* Defines for SPL */
|
||||
#define CONFIG_SPL_FRAMEWORK
|
||||
#define CONFIG_SPL_TEXT_BASE 0x40004030
|
||||
#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
|
||||
|
||||
#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SYS_MALLOC_SIMPLE
|
||||
#endif
|
||||
|
||||
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
|
||||
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
|
||||
|
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT
|
||||
#define CONFIG_SPL_LIBGENERIC_SUPPORT
|
||||
#define CONFIG_SPL_SERIAL_SUPPORT
|
||||
#define CONFIG_SPL_I2C_SUPPORT
|
||||
|
||||
/* SPL related SPI defines */
|
||||
#define CONFIG_SPL_SPI_SUPPORT
|
||||
#define CONFIG_SPL_SPI_FLASH_SUPPORT
|
||||
#define CONFIG_SPL_SPI_LOAD
|
||||
#define CONFIG_SPL_SPI_BUS 0
|
||||
#define CONFIG_SPL_SPI_CS 0
|
||||
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
|
||||
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
|
||||
|
||||
#endif /* _CONFIG_DB_88F6720_H */
|
||||
Loading…
Reference in New Issue