Matthias Fuchs
Tom Rini
parent
2b8a04e551
commit
61b57c4ab9
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@ -110,9 +110,6 @@ config TARGET_CATCENTER
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config TARGET_PPCHAMELEONEVB
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bool "Support PPChameleonEVB"
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config TARGET_AR405
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bool "Support AR405"
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config TARGET_ASH405
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bool "Support ASH405"
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@ -254,7 +251,6 @@ source "board/avnet/v5fx30teval/Kconfig"
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source "board/csb272/Kconfig"
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source "board/csb472/Kconfig"
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source "board/dave/PPChameleonEVB/Kconfig"
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source "board/esd/ar405/Kconfig"
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source "board/esd/ash405/Kconfig"
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source "board/esd/cms700/Kconfig"
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source "board/esd/cpci2dp/Kconfig"
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@ -1,12 +0,0 @@
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if TARGET_AR405
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config SYS_BOARD
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default "ar405"
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config SYS_VENDOR
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default "esd"
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config SYS_CONFIG_NAME
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default "AR405"
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endif
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@ -1,6 +0,0 @@
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AR405 BOARD
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M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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S: Maintained
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F: board/esd/ar405/
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F: include/configs/AR405.h
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F: configs/AR405_defconfig
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@ -1,8 +0,0 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = ar405.o flash.o ../common/misc.o
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@ -1,394 +0,0 @@
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/*
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* (C) Copyright 2001-2004
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include "ar405.h"
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <command.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern void lxt971_no_sleep(void);
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/* ------------------------------------------------------------------------- */
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#if 0
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#define FPGA_DEBUG
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#endif
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/* fpga configuration data - generated by bin2cc */
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const unsigned char fpgadata[] = {
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#include "fpgadata.c"
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};
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const unsigned char fpgadata_xl30[] = {
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#include "fpgadata_xl30.c"
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};
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/*
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* include common fpga code (for esd boards)
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*/
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#include "../common/fpga.c"
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int board_early_init_f (void)
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{
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int index, len, i;
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int status;
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#ifdef FPGA_DEBUG
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/* set up serial port with default baudrate */
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(void) get_clocks ();
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gd->baudrate = CONFIG_BAUDRATE;
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serial_init ();
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console_init_f ();
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#endif
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/*
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* Boot onboard FPGA
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*/
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/* first try 40er image */
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gd->board_type = 40;
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status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
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if (status != 0) {
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/* try xl30er image */
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gd->board_type = 30;
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status = fpga_boot ((unsigned char *) fpgadata_xl30, sizeof (fpgadata_xl30));
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if (status != 0) {
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/* booting FPGA failed */
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#ifndef FPGA_DEBUG
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/* set up serial port with default baudrate */
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(void) get_clocks ();
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gd->baudrate = CONFIG_BAUDRATE;
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serial_init ();
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console_init_f ();
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#endif
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printf ("\nFPGA: Booting failed ");
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switch (status) {
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case ERROR_FPGA_PRG_INIT_LOW:
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printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
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break;
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case ERROR_FPGA_PRG_INIT_HIGH:
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printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
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break;
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case ERROR_FPGA_PRG_DONE:
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printf ("(Timeout: DONE not high after programming FPGA)\n ");
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break;
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}
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/* display infos on fpgaimage */
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index = 15;
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for (i = 0; i < 4; i++) {
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len = fpgadata[index];
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printf ("FPGA: %s\n", &(fpgadata[index + 1]));
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index += len + 3;
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}
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putc ('\n');
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/* delayed reboot */
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for (i = 20; i > 0; i--) {
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printf ("Rebooting in %2d seconds \r", i);
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for (index = 0; index < 1000; index++)
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udelay (1000);
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}
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putc ('\n');
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do_reset (NULL, 0, 0, NULL);
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}
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}
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/*
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* IRQ 0-15 405GP internally generated; active high; level sensitive
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* IRQ 16 405GP internally generated; active low; level sensitive
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* IRQ 17-24 RESERVED
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* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
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* IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
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* IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
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* IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
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* IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
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* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
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* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
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*/
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mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
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mtdcr (UIC0ER, 0x00000000); /* disable all ints */
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mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
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mtdcr (UIC0PR, 0xFFFFFF81); /* set int polarities */
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mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
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mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
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mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
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out_be16((void *)0xf03000ec, 0x0fff); /* enable interrupts in fpga */
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return 0;
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}
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/*
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* Check Board Identity:
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*/
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int checkboard (void)
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{
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int index;
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int len;
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char str[64];
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int i = getenv_f("serial#", str, sizeof (str));
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const unsigned char *fpga;
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puts ("Board: ");
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if (i == -1) {
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puts ("### No HW ID - assuming AR405");
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} else {
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puts(str);
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}
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puts ("\nFPGA: ");
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/* display infos on fpgaimage */
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if (gd->board_type == 30) {
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fpga = fpgadata_xl30;
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} else {
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fpga = fpgadata;
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}
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index = 15;
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for (i = 0; i < 4; i++) {
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len = fpga[index];
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printf ("%s ", &(fpga[index + 1]));
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index += len + 3;
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}
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putc ('\n');
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/*
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* Disable sleep mode in LXT971
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*/
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lxt971_no_sleep();
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return 0;
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}
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#if 1 /* test-only: some internal test routines... */
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#define DIGEN ((void *)0xf03000b4) /* u8 */
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#define DIGOUT ((void *)0xf03000b0) /* u16 */
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#define DIGIN ((void *)0xf03000a0) /* u16 */
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/*
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* Some test routines
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*/
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int do_digtest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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int i;
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int k;
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int start;
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int end;
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if (argc != 3) {
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puts("Usage: digtest n_start n_end (digtest 0 7)\n");
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return 0;
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}
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start = simple_strtol (argv[1], NULL, 10);
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end = simple_strtol (argv[2], NULL, 10);
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/*
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* Enable digital outputs
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*/
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out_8(DIGEN, 0x08);
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printf("\nStarting digital In-/Out Test from I/O %d to %d (Cntrl-C to abort)...\n",
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start, end);
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/*
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* Set outputs one by one
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*/
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for (;;) {
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for (i=start; i<=end; i++) {
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out_be16(DIGOUT, 0x0001 << i);
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for (k=0; k<200; k++)
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udelay(1000);
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if (in_be16(DIGIN) != (0x0001 << i)) {
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printf("ERROR: OUT=0x%04X, IN=0x%04X\n",
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0x0001 << i, in_be16(DIGIN));
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return 0;
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}
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/* Abort if ctrl-c was pressed */
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if (ctrlc()) {
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puts("\nAbort\n");
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return 0;
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}
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}
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}
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return 0;
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}
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U_BOOT_CMD(
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digtest, 3, 1, do_digtest,
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"Test digital in-/output",
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""
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);
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#define ERROR_DELTA 256
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struct io {
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short val;
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short dummy;
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};
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int do_anatest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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short val;
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int i;
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int volt;
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struct io *out;
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struct io *in;
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out = (struct io *)0xf0300090;
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in = (struct io *)0xf0300000;
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i = simple_strtol (argv[1], NULL, 10);
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volt = 0;
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printf("Setting Channel %d to %dV...\n", i, volt);
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out_be16((void *)&(out[i].val), (volt * 0x7fff) / 10);
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udelay(10000);
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val = in_be16((void *)&(in[i*2].val));
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printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff);
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if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
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(val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
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printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
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((volt * 0x7fff) / 40) + ERROR_DELTA);
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return -1;
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}
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val = in_be16((void *)&(in[i*2+1].val));
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printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff);
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if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
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(val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
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printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
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((volt * 0x7fff) / 40) + ERROR_DELTA);
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return -1;
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}
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volt = 5;
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printf("Setting Channel %d to %dV...\n", i, volt);
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out_be16((void *)&(out[i].val), (volt * 0x7fff) / 10);
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udelay(10000);
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val = in_be16((void *)&(in[i*2].val));
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printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff);
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if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
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(val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
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printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
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((volt * 0x7fff) / 40) + ERROR_DELTA);
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return -1;
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}
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val = in_be16((void *)&(in[i*2+1].val));
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printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff);
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if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
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(val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
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printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
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((volt * 0x7fff) / 40) + ERROR_DELTA);
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return -1;
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}
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volt = 10;
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printf("Setting Channel %d to %dV...\n", i, volt);
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out_be16((void *)&(out[i].val), (volt * 0x7fff) / 10);
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udelay(10000);
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val = in_be16((void *)&(in[i*2].val));
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printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff);
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if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
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(val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
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printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
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((volt * 0x7fff) / 40) + ERROR_DELTA);
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return -1;
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}
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val = in_be16((void *)&(in[i*2+1].val));
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printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff);
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if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
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(val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
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printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
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((volt * 0x7fff) / 40) + ERROR_DELTA);
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return -1;
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}
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printf("Channel %d OK!\n", i);
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return 0;
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}
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U_BOOT_CMD(
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anatest, 2, 1, do_anatest,
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"Test analog in-/output",
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""
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);
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int counter = 0;
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void cyclicInt(void *ptr)
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{
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out_be16((void *)0xf03000e8, 0x0800); /* ack int */
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counter++;
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}
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int do_inctest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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ulong *incin;
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int i;
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incin = (ulong *)0xf0300040;
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/*
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* Clear inc counter
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*/
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out_be32((void *)&incin[0], 0);
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out_be32((void *)&incin[1], 0);
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out_be32((void *)&incin[2], 0);
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out_be32((void *)&incin[3], 0);
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incin = (ulong *)0xf0300050;
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/*
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* Inc a little
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*/
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for (i=0; i<10000; i++) {
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switch (i & 0x03) {
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case 0:
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out_8(DIGEN, 0x02);
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break;
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case 1:
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out_8(DIGEN, 0x03);
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break;
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case 2:
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out_8(DIGEN, 0x01);
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break;
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case 3:
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out_8(DIGEN, 0x00);
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break;
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}
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udelay(10);
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}
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printf("Inc 0 = %d\n", in_be32((void *)&incin[0]));
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printf("Inc 1 = %d\n", in_be32((void *)&incin[1]));
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printf("Inc 2 = %d\n", in_be32((void *)&incin[2]));
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printf("Inc 3 = %d\n", in_be32((void *)&incin[3]));
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out_be16((void *)0xf03000e0, 0x0c80-1); /* set counter */
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out_be16((void *)0xf03000ec,
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in_be16((void *)0xf03000ec) | 0x0800); /* enable int */
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irq_install_handler (30, (interrupt_handler_t *) cyclicInt, NULL);
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printf("counter=%d\n", counter);
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return 0;
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}
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U_BOOT_CMD(
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inctest, 3, 1, do_inctest,
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"Test incremental encoder inputs",
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""
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);
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#endif
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@ -1,28 +0,0 @@
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/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/****************************************************************************
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* FLASH Memory Map as used by TQ Monitor:
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*
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* Start Address Length
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* +-----------------------+ 0x4000_0000 Start of Flash -----------------
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* | MON8xx code | 0x4000_0100 Reset Vector
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* +-----------------------+ 0x400?_????
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* | (unused) |
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* +-----------------------+ 0x4001_FF00
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* | Ethernet Addresses | 0x78
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* +-----------------------+ 0x4001_FF78
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* | (Reserved for MON8xx) | 0x44
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* +-----------------------+ 0x4001_FFBC
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* | Lock Address | 0x04
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* +-----------------------+ 0x4001_FFC0 ^
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* | Hardware Information | 0x40 | MON8xx
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* +=======================+ 0x4002_0000 (sector border) -----------------
|
||||
* | Autostart Header | | Applications
|
||||
* | ... | v
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
|
@ -1,85 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/ppc4xx.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
/*
|
||||
* include common flash code (for esd boards)
|
||||
*/
|
||||
#include "../common/flash.c"
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions
|
||||
*/
|
||||
static ulong flash_get_size (vu_long * addr, flash_info_t * info);
|
||||
static void flash_get_offsets (ulong base, flash_info_t * info);
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
unsigned long size_b0;
|
||||
int i;
|
||||
uint pbcr;
|
||||
unsigned long base_b0;
|
||||
int size_val = 0;
|
||||
|
||||
/* Init: no FLASHes known */
|
||||
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
|
||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
||||
}
|
||||
|
||||
/* Static FLASH Bank configuration here - FIXME XXX */
|
||||
|
||||
size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
|
||||
|
||||
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
|
||||
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
|
||||
size_b0, size_b0<<20);
|
||||
}
|
||||
|
||||
/* Setup offsets */
|
||||
flash_get_offsets (-size_b0, &flash_info[0]);
|
||||
|
||||
/* Re-do sizing to get full correct info */
|
||||
mtdcr(EBC0_CFGADDR, PB0CR);
|
||||
pbcr = mfdcr(EBC0_CFGDATA);
|
||||
mtdcr(EBC0_CFGADDR, PB0CR);
|
||||
base_b0 = -size_b0;
|
||||
switch (size_b0) {
|
||||
case 1 << 20:
|
||||
size_val = 0;
|
||||
break;
|
||||
case 2 << 20:
|
||||
size_val = 1;
|
||||
break;
|
||||
case 4 << 20:
|
||||
size_val = 2;
|
||||
break;
|
||||
case 8 << 20:
|
||||
size_val = 3;
|
||||
break;
|
||||
case 16 << 20:
|
||||
size_val = 4;
|
||||
break;
|
||||
}
|
||||
pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
|
||||
mtdcr(EBC0_CFGDATA, pbcr);
|
||||
|
||||
/* Monitor protection ON by default */
|
||||
(void)flash_protect(FLAG_PROTECT_SET,
|
||||
-CONFIG_SYS_MONITOR_LEN,
|
||||
0xffffffff,
|
||||
&flash_info[0]);
|
||||
|
||||
flash_info[0].size = size_b0;
|
||||
|
||||
return (size_b0);
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,3 +0,0 @@
|
|||
CONFIG_PPC=y
|
||||
CONFIG_4xx=y
|
||||
CONFIG_TARGET_AR405=y
|
||||
|
|
@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
|
|||
|
||||
Board Arch CPU Commit Removed Last known maintainer/contact
|
||||
=================================================================================================
|
||||
AR405 ppc4xx 405gpr - - Matthias Fuchs <matthias.fuchs@esd.eu>
|
||||
APC405 ppc4xx 405gpr - - Matthias Fuchs <matthias.fuchs@esd.eu>
|
||||
TASREG m68k mcf52x2 - - Matthias Fuchs <matthias.fuchs@esd.eu>
|
||||
A3000 powerpc mpc824x - -
|
||||
|
|
|
|||
|
|
@ -1,253 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2001-2004
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
|
||||
#define CONFIG_AR405 1 /* ...on a AR405 board */
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
|
||||
|
||||
#define CONFIG_BOARD_TYPES 1 /* support board types */
|
||||
|
||||
#define CONFIG_BAUDRATE 9600
|
||||
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
|
||||
|
||||
#if 1
|
||||
#define CONFIG_BOOTCOMMAND "bootm fff00000" /* autoboot command */
|
||||
#else
|
||||
#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
#define CONFIG_BOOTARGS "root=/dev/nfs " \
|
||||
"ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 " \
|
||||
"nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4"
|
||||
#else
|
||||
#define CONFIG_BOOTARGS "root=/dev/hda1 " \
|
||||
"ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0"
|
||||
|
||||
#endif
|
||||
|
||||
#define CONFIG_PREBOOT /* enable preboot variable */
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
#define CONFIG_PPC4xx_EMAC
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_PHY_ADDR 0 /* PHY address */
|
||||
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
|
||||
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_IRQ
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_MII
|
||||
#undef CONFIG_CMD_NFS
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_BSP
|
||||
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
|
||||
|
||||
#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
|
||||
|
||||
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
|
||||
#define CONFIG_LOOPW 1 /* enable loopw command */
|
||||
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
|
||||
|
||||
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
|
||||
|
||||
#define CONFIG_SYS_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */
|
||||
|
||||
/* The following table includes the supported baudrates */
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
|
||||
57600, 115200, 230400, 460800, 921600 }
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
|
||||
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
|
||||
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
|
||||
#define PCI_HOST_FORCE 1 /* configure as pci host */
|
||||
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
|
||||
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
|
||||
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
/* resource configuration */
|
||||
|
||||
#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
|
||||
|
||||
#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
|
||||
|
||||
#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
|
||||
|
||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
|
||||
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0403 /* PCI Device ID: ARISTO405 */
|
||||
#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
|
||||
#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
|
||||
#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
|
||||
#define CONFIG_SYS_PCI_PTM2LA 0xfff00000 /* point to flash */
|
||||
#define CONFIG_SYS_PCI_PTM2MS 0xfff00001 /* 1MB, enable */
|
||||
#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
|
||||
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
|
||||
#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
|
||||
#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
|
||||
/*
|
||||
* The following defines are added for buggy IOP480 byte interface.
|
||||
* All other boards should use the standard values (CPCI405 etc.)
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
|
||||
#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
|
||||
#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
|
||||
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
|
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
|
||||
#define CONFIG_ENV_SIZE 0x04000 /* Size of Environment */
|
||||
|
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
|
||||
|
||||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* BR0/1 and OR0/1 (FLASH)
|
||||
*/
|
||||
|
||||
#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* External Bus Controller (EBC) Setup
|
||||
*/
|
||||
|
||||
/* Memory Bank 0 (Flash Bank 0) initialization */
|
||||
#define CONFIG_SYS_EBC_PB0AP 0x92015480
|
||||
#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
|
||||
|
||||
/* Memory Bank 1 (CAN0, 1, 2, 3) initialization */
|
||||
#define CONFIG_SYS_EBC_PB1AP 0x01000380 /* enable Ready, BEM=0 */
|
||||
#define CONFIG_SYS_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
|
||||
|
||||
/* Memory Bank 2 (Expension Bus) initialization */
|
||||
#define CONFIG_SYS_EBC_PB2AP 0x01000280 /* disable Ready, BEM=0 */
|
||||
#define CONFIG_SYS_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
|
||||
|
||||
/* Memory Bank 3 (16552) initialization */
|
||||
#define CONFIG_SYS_EBC_PB3AP 0x01000380 /* enable Ready, BEM=0 */
|
||||
#define CONFIG_SYS_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
|
||||
|
||||
/* Memory Bank 4 (FPGA regs) initialization */
|
||||
#define CONFIG_SYS_EBC_PB4AP 0x01005380 /* enable Ready, BEM=0 */
|
||||
#define CONFIG_SYS_EBC_PB4CR 0xF031C000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=32bit */
|
||||
|
||||
/* Memory Bank 5 (Flash Bank 1/DUMMY) initialization */
|
||||
#define CONFIG_SYS_EBC_PB5AP 0x92015480
|
||||
#define CONFIG_SYS_EBC_PB5CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in data cache)
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue