MLK-18460-2 mx7d_12x12_arm2: Add LPDDR3 and DDR3 ARM2 support
Porting the iMX7D 12x12 LPDDR3 and DDR3 ARM2 board codes from v2017.03. Signed-off-by: Ye Li <ye.li@nxp.com>zero-sugar
Ye Li
parent
31c500c421
commit
63a40240b4
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@ -34,6 +34,20 @@ config TARGET_MX7DSABRESD
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select DM
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select DM_THERMAL
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config TARGET_MX7D_12X12_LPDDR3_ARM2
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bool "Support mx7d_12x12_lpddr3_arm2"
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select BOARD_LATE_INIT
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select MX7D
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select DM
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select DM_THERMAL
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config TARGET_MX7D_12X12_DDR3_ARM2
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bool "Support mx7d_12x12_ddr3_arm2"
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select BOARD_LATE_INIT
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select MX7D
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select DM
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select DM_THERMAL
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config TARGET_PICO_IMX7D
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bool "pico-imx7d"
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select BOARD_LATE_INIT
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@ -62,6 +76,8 @@ config SYS_SOC
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source "board/compulab/cl-som-imx7/Kconfig"
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source "board/freescale/mx7dsabresd/Kconfig"
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source "board/freescale/mx7d_12x12_lpddr3_arm2/Kconfig"
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source "board/freescale/mx7d_12x12_ddr3_arm2/Kconfig"
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source "board/technexion/pico-imx7d/Kconfig"
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source "board/toradex/colibri_imx7/Kconfig"
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source "board/warp7/Kconfig"
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@ -0,0 +1,14 @@
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if TARGET_MX7D_12X12_DDR3_ARM2
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config SYS_BOARD
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default "mx7d_12x12_ddr3_arm2"
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config SYS_VENDOR
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default "freescale"
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config SYS_CONFIG_NAME
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default "mx7d_12x12_ddr3_arm2"
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config SYS_TEXT_BASE
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default 0x87800000
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endif
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@ -0,0 +1,6 @@
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# (C) Copyright 2015 Freescale Semiconductor, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := mx7d_12x12_ddr3_arm2.o
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@ -0,0 +1,111 @@
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/*
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* Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Refer doc/README.imxmage for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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#define __ASSEMBLY__
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#include <config.h>
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/* image version */
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IMAGE_VERSION 2
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/*
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* Boot Device : one of
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* sd/onenand, nor
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*/
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BOOT_FROM sd
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#ifdef CONFIG_USE_IMXIMG_PLUGIN
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/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
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PLUGIN board/freescale/mx7d_12x12_ddr3_arm2/plugin.bin 0x00910000
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#else
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#ifdef CONFIG_SECURE_BOOT
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CSF CONFIG_CSF_SIZE
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#endif
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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DATA 4 0x30340004 0x4F400005
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/* Clear then set bit30 to ensure exit from DDR retention */
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DATA 4 0x30360388 0x40000000
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DATA 4 0x30360384 0x40000000
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DATA 4 0x30391000 0x00000002
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DATA 4 0x307a0000 0x01040001
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DATA 4 0x307a01a0 0x80400003
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DATA 4 0x307a01a4 0x00100020
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DATA 4 0x307a01a8 0x80100004
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DATA 4 0x307a0064 0x00400046
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DATA 4 0x307a0490 0x00000001
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DATA 4 0x307a00d0 0x00020083
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DATA 4 0x307a00d4 0x00690000
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DATA 4 0x307a00dc 0x09300004
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DATA 4 0x307a00e0 0x04080000
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DATA 4 0x307a00e4 0x00100004
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DATA 4 0x307a00f4 0x0000033f
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DATA 4 0x307a0100 0x09081109
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DATA 4 0x307a0104 0x0007020d
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DATA 4 0x307a0108 0x03040407
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DATA 4 0x307a010c 0x00002006
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DATA 4 0x307a0110 0x04020205
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DATA 4 0x307a0114 0x03030202
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DATA 4 0x307a0120 0x00000803
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DATA 4 0x307a0180 0x00800020
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DATA 4 0x307a0184 0x02000100
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DATA 4 0x307a0190 0x02098204
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DATA 4 0x307a0194 0x00030303
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DATA 4 0x307a0200 0x00000016
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DATA 4 0x307a0204 0x00080808
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DATA 4 0x307a0210 0x00000f0f
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DATA 4 0x307a0214 0x07070707
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DATA 4 0x307a0218 0x0f070707
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DATA 4 0x307a0240 0x06000604
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DATA 4 0x307a0244 0x00000001
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DATA 4 0x30391000 0x00000000
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DATA 4 0x30790000 0x17420f40
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DATA 4 0x30790004 0x10210100
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DATA 4 0x30790010 0x00060807
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DATA 4 0x307900b0 0x1010007e
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DATA 4 0x3079009c 0x00000b24
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DATA 4 0x30790020 0x08080808
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DATA 4 0x30790030 0x08080808
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DATA 4 0x30790050 0x01000010
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DATA 4 0x30790050 0x00000010
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DATA 4 0x307900c0 0x0e407304
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DATA 4 0x307900c0 0x0e447304
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DATA 4 0x307900c0 0x0e447306
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CHECK_BITS_SET 4 0x307900c4 0x1
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DATA 4 0x307900c0 0x0e407304
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DATA 4 0x30384130 0x00000000
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DATA 4 0x30340020 0x00000178
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DATA 4 0x30384130 0x00000002
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DATA 4 0x30790018 0x0000000f
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CHECK_BITS_SET 4 0x307a0004 0x1
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#endif
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@ -0,0 +1,122 @@
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/*
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* Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Refer docs/README.imxmage for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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#define __ASSEMBLY__
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#include <config.h>
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/* image version */
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IMAGE_VERSION 2
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/*
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* Boot Device : one of
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* sd/onenand, nor
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*/
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BOOT_FROM sd
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#ifdef CONFIG_USE_IMXIMG_PLUGIN
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/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
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PLUGIN board/freescale/mx7d_12x12_ddr3_arm2/plugin.bin 0x00910000
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#else
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#ifdef CONFIG_SECURE_BOOT
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CSF CONFIG_CSF_SIZE
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#endif
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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DATA 4 0x30360070 0x00703021
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DATA 4 0x30360090 0x0
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DATA 4 0x30360070 0x00603021
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CHECK_BITS_SET 4 0x30360070 0x80000000
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DATA 4 0x30389880 0x1
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DATA 4 0x30340004 0x4F400005
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/* Clear then set bit30 to ensure exit from DDR retention */
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DATA 4 0x30360388 0x40000000
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DATA 4 0x30360384 0x40000000
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DATA 4 0x30391000 0x00000002
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DATA 4 0x307a0000 0x01040001
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DATA 4 0x307a01a0 0x80400003
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DATA 4 0x307a01a4 0x00100020
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DATA 4 0x307a01a8 0x80100004
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DATA 4 0x307a0064 0x00400046
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DATA 4 0x307a0490 0x00000001
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DATA 4 0x307a00d0 0x00020083
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DATA 4 0x307a00d4 0x00690000
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DATA 4 0x307a00dc 0x09300004
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DATA 4 0x307a00e0 0x04080000
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DATA 4 0x307a00e4 0x00100004
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DATA 4 0x307a00f4 0x0000033f
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DATA 4 0x307a0100 0x09081109
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DATA 4 0x307a0104 0x0007020d
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DATA 4 0x307a0108 0x03040407
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DATA 4 0x307a010c 0x00002006
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DATA 4 0x307a0110 0x04020205
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DATA 4 0x307a0114 0x03030202
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DATA 4 0x307a0120 0x00000803
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DATA 4 0x307a0180 0x00800020
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DATA 4 0x307a0184 0x02000100
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DATA 4 0x307a0190 0x02098204
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DATA 4 0x307a0194 0x00030303
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DATA 4 0x307a0200 0x00000016
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DATA 4 0x307a0204 0x00080808
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DATA 4 0x307a0210 0x00000f0f
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DATA 4 0x307a0214 0x07070707
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DATA 4 0x307a0218 0x0f070707
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DATA 4 0x307a0240 0x06000604
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DATA 4 0x307a0244 0x00000001
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DATA 4 0x30391000 0x00000000
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DATA 4 0x30790000 0x17420f40
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DATA 4 0x30790004 0x10210100
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DATA 4 0x30790010 0x00060807
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DATA 4 0x307900b0 0x1010007e
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DATA 4 0x3079009c 0x00000dee
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DATA 4 0x3079007c 0x18181818
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DATA 4 0x30790080 0x18181818
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DATA 4 0x30790084 0x40401818
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DATA 4 0x30790088 0x00000040
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DATA 4 0x3079006c 0x40404040
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DATA 4 0x30790020 0x08080808
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DATA 4 0x30790030 0x08080808
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DATA 4 0x30790050 0x01000010
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DATA 4 0x30790050 0x00000010
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DATA 4 0x307900c0 0x0e407304
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DATA 4 0x307900c0 0x0e447304
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DATA 4 0x307900c0 0x0e447306
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CHECK_BITS_SET 4 0x307900c4 0x1
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DATA 4 0x307900c0 0x0e407304
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DATA 4 0x30384130 0x00000000
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DATA 4 0x30340020 0x00000178
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DATA 4 0x30384130 0x00000002
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DATA 4 0x30790018 0x0000000f
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CHECK_BITS_SET 4 0x307a0004 0x1
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#endif
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@ -0,0 +1,190 @@
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/*
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* Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx7-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/io.h>
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#include <linux/sizes.h>
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#include <common.h>
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#include <fsl_esdhc.h>
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#include <mmc.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <power/pmic.h>
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#include <power/pfuze3000_pmic.h>
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#include "../common/pfuze.h"
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#include <asm/arch/crm_regs.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
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PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
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#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
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PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
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#define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
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int dram_init(void)
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{
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gd->ram_size = PHYS_SDRAM_SIZE;
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return 0;
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}
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static iomux_v3_cfg_t const uart1_pads[] = {
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MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const wdog_pads[] = {
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MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static void setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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}
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#ifdef CONFIG_FSL_ESDHC
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int board_mmc_get_env_dev(int devno)
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{
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return devno - 1;
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}
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int mmc_map_to_kernel_blk(int dev_no)
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{
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return dev_no + 1;
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}
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#endif
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#ifdef CONFIG_MXC_SPI
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iomux_v3_cfg_t const ecspi1_pads[] = {
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MX7D_PAD_SD1_RESET_B__ECSPI4_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
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MX7D_PAD_SD1_WP__ECSPI4_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
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MX7D_PAD_SD1_CD_B__ECSPI4_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
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/* Chip selects CS0:CS3 */
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MX7D_PAD_SD1_CLK__GPIO5_IO3 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX7D_PAD_SD1_CMD__GPIO5_IO4 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX7D_PAD_SD1_DATA0__GPIO5_IO5 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX7D_PAD_SD1_DATA1__GPIO5_IO6 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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void setup_spinor(void)
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{
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imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
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ARRAY_SIZE(ecspi1_pads));
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gpio_request(IMX_GPIO_NR(5, 3), "ecspi1_cs");
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gpio_direction_output(IMX_GPIO_NR(5, 3), 0);
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}
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int board_spi_cs_gpio(unsigned bus, unsigned cs)
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{
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return (bus == 3 && cs == 0) ? (IMX_GPIO_NR(5, 3)) : -1;
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}
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#endif
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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#ifdef CONFIG_MXC_SPI
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setup_spinor();
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#endif
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return 0;
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}
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#ifdef CONFIG_CMD_BMODE
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static const struct boot_mode board_boot_modes[] = {
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/* 4 bit bus width */
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{"emmc", MAKE_CFGVAL(0x10, 0x22, 0x00, 0x00)},
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{"sd3", MAKE_CFGVAL(0x10, 0x1a, 0x00, 0x00)},
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{NULL, 0},
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};
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#endif
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#ifdef CONFIG_DM_PMIC
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int power_init_board(void)
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{
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struct udevice *dev;
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int ret, dev_id, rev_id, reg;
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ret = pmic_get("pfuze3000", &dev);
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if (ret == -ENODEV)
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return 0;
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if (ret != 0)
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return ret;
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dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
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rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
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printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
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/* disable Low Power Mode during standby mode */
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reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
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reg |= 0x1;
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pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);
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/* SW1A/1B mode set to APS/APS */
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reg = 0x8;
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pmic_reg_write(dev, PFUZE3000_SW1AMODE, reg);
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pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg);
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/* SW1A/1B standby voltage set to 0.975V */
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reg = 0xb;
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pmic_reg_write(dev, PFUZE3000_SW1ASTBY, reg);
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pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg);
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/* set SW1B normal voltage to 0.975V */
|
||||
reg = pmic_reg_read(dev, PFUZE3000_SW1BVOLT);
|
||||
reg &= ~0x1f;
|
||||
reg |= PFUZE3000_SW1AB_SETP(9750);
|
||||
pmic_reg_write(dev, PFUZE3000_SW1BVOLT, reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
add_board_boot_modes(board_boot_modes);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_MMC
|
||||
board_late_mmc_env_init();
|
||||
#endif
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
|
||||
|
||||
set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
u32 get_board_rev(void)
|
||||
{
|
||||
return get_cpu_rev();
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: MX7D 12x12 DDR3 ARM2\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,227 @@
|
|||
/*
|
||||
* Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
|
||||
/* DDR script */
|
||||
.macro imx7d_ddrphy_latency_setting
|
||||
ldr r2, =ANATOP_BASE_ADDR
|
||||
ldr r3, [r2, #0x800]
|
||||
and r3, r3, #0xFF
|
||||
cmp r3, #0x11
|
||||
bne NO_DELAY
|
||||
|
||||
/*TO 1.1*/
|
||||
ldr r1, =0x00000dee
|
||||
str r1, [r0, #0x9c]
|
||||
ldr r1, =0x18181818
|
||||
str r1, [r0, #0x7c]
|
||||
ldr r1, =0x18181818
|
||||
str r1, [r0, #0x80]
|
||||
ldr r1, =0x40401818
|
||||
str r1, [r0, #0x84]
|
||||
ldr r1, =0x00000040
|
||||
str r1, [r0, #0x88]
|
||||
ldr r1, =0x40404040
|
||||
str r1, [r0, #0x6c]
|
||||
b TUNE_END
|
||||
|
||||
NO_DELAY:
|
||||
/*TO 1.0*/
|
||||
ldr r1, =0x00000b24
|
||||
str r1, [r0, #0x9c]
|
||||
|
||||
TUNE_END:
|
||||
.endm
|
||||
|
||||
.macro imx7d_ddr_freq_setting
|
||||
ldr r2, =ANATOP_BASE_ADDR
|
||||
ldr r3, [r2, #0x800]
|
||||
and r3, r3, #0xFF
|
||||
cmp r3, #0x11
|
||||
bne FREQ_DEFAULT_533
|
||||
|
||||
/* Change to 400Mhz for TO1.1 */
|
||||
ldr r0, =ANATOP_BASE_ADDR
|
||||
ldr r1, =0x70
|
||||
ldr r2, =0x00703021
|
||||
str r2, [r0, r1]
|
||||
ldr r1, =0x90
|
||||
ldr r2, =0x0
|
||||
str r2, [r0, r1]
|
||||
ldr r1, =0x70
|
||||
ldr r2, =0x00603021
|
||||
str r2, [r0, r1]
|
||||
|
||||
ldr r3, =0x80000000
|
||||
wait_lock:
|
||||
ldr r2, [r0, r1]
|
||||
and r2, r3
|
||||
cmp r2, r3
|
||||
bne wait_lock
|
||||
|
||||
ldr r0, =CCM_BASE_ADDR
|
||||
ldr r1, =0x9880
|
||||
ldr r2, =0x1
|
||||
str r2, [r0, r1]
|
||||
|
||||
FREQ_DEFAULT_533:
|
||||
.endm
|
||||
|
||||
.macro imx7d_12x12_ddr3_arm2_ddr_setting
|
||||
imx7d_ddr_freq_setting
|
||||
|
||||
/* Configure ocram_epdc */
|
||||
ldr r0, =IOMUXC_GPR_BASE_ADDR
|
||||
ldr r1, =0x4f400005
|
||||
str r1, [r0, #0x4]
|
||||
|
||||
/* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */
|
||||
ldr r0, =ANATOP_BASE_ADDR
|
||||
ldr r1, =(0x1 << 30)
|
||||
str r1, [r0, #0x388]
|
||||
str r1, [r0, #0x384]
|
||||
|
||||
ldr r0, =SRC_BASE_ADDR
|
||||
ldr r1, =0x2
|
||||
ldr r2, =0x1000
|
||||
str r1, [r0, r2]
|
||||
|
||||
ldr r0, =DDRC_IPS_BASE_ADDR
|
||||
ldr r1, =0x01040001
|
||||
str r1, [r0]
|
||||
ldr r1, =0x80400003
|
||||
str r1, [r0, #0x1a0]
|
||||
ldr r1, =0x00100020
|
||||
str r1, [r0, #0x1a4]
|
||||
ldr r1, =0x80100004
|
||||
str r1, [r0, #0x1a8]
|
||||
ldr r1, =0x00400046
|
||||
str r1, [r0, #0x64]
|
||||
ldr r1, =0x1
|
||||
str r1, [r0, #0x490]
|
||||
ldr r1, =0x00020001
|
||||
str r1, [r0, #0xd0]
|
||||
ldr r1, =0x00690000
|
||||
str r1, [r0, #0xd4]
|
||||
ldr r1, =0x09300004
|
||||
str r1, [r0, #0xdc]
|
||||
ldr r1, =0x04080000
|
||||
str r1, [r0, #0xe0]
|
||||
ldr r1, =0x00100004
|
||||
str r1, [r0, #0xe4]
|
||||
ldr r1, =0x33f
|
||||
str r1, [r0, #0xf4]
|
||||
ldr r1, =0x09081109
|
||||
str r1, [r0, #0x100]
|
||||
ldr r1, =0x0007020d
|
||||
str r1, [r0, #0x104]
|
||||
ldr r1, =0x03040407
|
||||
str r1, [r0, #0x108]
|
||||
ldr r1, =0x00002006
|
||||
str r1, [r0, #0x10c]
|
||||
ldr r1, =0x04020205
|
||||
str r1, [r0, #0x110]
|
||||
ldr r1, =0x03030202
|
||||
str r1, [r0, #0x114]
|
||||
ldr r1, =0x00000803
|
||||
str r1, [r0, #0x120]
|
||||
ldr r1, =0x00800020
|
||||
str r1, [r0, #0x180]
|
||||
ldr r1, =0x02000100
|
||||
str r1, [r0, #0x184]
|
||||
ldr r1, =0x02098204
|
||||
str r1, [r0, #0x190]
|
||||
ldr r1, =0x00030303
|
||||
str r1, [r0, #0x194]
|
||||
|
||||
ldr r1, =0x00000016
|
||||
str r1, [r0, #0x200]
|
||||
ldr r1, =0x00080808
|
||||
str r1, [r0, #0x204]
|
||||
ldr r1, =0x00000f0f
|
||||
str r1, [r0, #0x210]
|
||||
ldr r1, =0x07070707
|
||||
str r1, [r0, #0x214]
|
||||
ldr r1, =0x0f070707
|
||||
str r1, [r0, #0x218]
|
||||
|
||||
ldr r1, =0x06000604
|
||||
str r1, [r0, #0x240]
|
||||
ldr r1, =0x00000001
|
||||
str r1, [r0, #0x244]
|
||||
|
||||
ldr r0, =SRC_BASE_ADDR
|
||||
mov r1, #0x0
|
||||
ldr r2, =0x1000
|
||||
str r1, [r0, r2]
|
||||
|
||||
ldr r0, =DDRPHY_IPS_BASE_ADDR
|
||||
ldr r1, =0x17420f40
|
||||
str r1, [r0]
|
||||
ldr r1, =0x10210100
|
||||
str r1, [r0, #0x4]
|
||||
ldr r1, =0x00060807
|
||||
str r1, [r0, #0x10]
|
||||
ldr r1, =0x1010007e
|
||||
str r1, [r0, #0xb0]
|
||||
imx7d_ddrphy_latency_setting
|
||||
ldr r1, =0x08080808
|
||||
str r1, [r0, #0x20]
|
||||
ldr r1, =0x08080808
|
||||
str r1, [r0, #0x30]
|
||||
ldr r1, =0x01000010
|
||||
str r1, [r0, #0x50]
|
||||
|
||||
ldr r1, =0x0e407304
|
||||
str r1, [r0, #0xc0]
|
||||
ldr r1, =0x0e447304
|
||||
str r1, [r0, #0xc0]
|
||||
ldr r1, =0x0e447306
|
||||
str r1, [r0, #0xc0]
|
||||
|
||||
wait_zq:
|
||||
ldr r1, [r0, #0xc4]
|
||||
tst r1, #0x1
|
||||
beq wait_zq
|
||||
|
||||
ldr r1, =0x0e407304
|
||||
str r1, [r0, #0xc0]
|
||||
|
||||
ldr r0, =CCM_BASE_ADDR
|
||||
mov r1, #0x0
|
||||
ldr r2, =0x4130
|
||||
str r1, [r0, r2]
|
||||
ldr r0, =IOMUXC_GPR_BASE_ADDR
|
||||
mov r1, #0x178
|
||||
str r1, [r0, #0x20]
|
||||
ldr r0, =CCM_BASE_ADDR
|
||||
mov r1, #0x2
|
||||
ldr r2, =0x4130
|
||||
str r1, [r0, r2]
|
||||
ldr r0, =DDRPHY_IPS_BASE_ADDR
|
||||
ldr r1, =0x0000000f
|
||||
str r1, [r0, #0x18]
|
||||
|
||||
ldr r0, =DDRC_IPS_BASE_ADDR
|
||||
wait_stat:
|
||||
ldr r1, [r0, #0x4]
|
||||
tst r1, #0x1
|
||||
beq wait_stat
|
||||
.endm
|
||||
|
||||
.macro imx7_clock_gating
|
||||
.endm
|
||||
|
||||
.macro imx7_qos_setting
|
||||
.endm
|
||||
|
||||
.macro imx7_ddr_setting
|
||||
imx7d_12x12_ddr3_arm2_ddr_setting
|
||||
.endm
|
||||
|
||||
/* include the common plugin code here */
|
||||
#include <asm/arch/mx7_plugin.S>
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
if TARGET_MX7D_12X12_LPDDR3_ARM2
|
||||
|
||||
config SYS_BOARD
|
||||
default "mx7d_12x12_lpddr3_arm2"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "freescale"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "mx7d_12x12_lpddr3_arm2"
|
||||
|
||||
config SYS_TEXT_BASE
|
||||
default 0x87800000
|
||||
endif
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
# (C) Copyright 2015 Freescale Semiconductor, Inc.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y := mx7d_12x12_lpddr3_arm2.o
|
||||
|
|
@ -0,0 +1,110 @@
|
|||
/*
|
||||
* Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* Refer doc/README.imxmage for more details about how-to configure
|
||||
* and create imximage boot image
|
||||
*
|
||||
* The syntax is taken as close as possible with the kwbimage
|
||||
*/
|
||||
|
||||
#define __ASSEMBLY__
|
||||
#include <config.h>
|
||||
|
||||
/* image version */
|
||||
|
||||
IMAGE_VERSION 2
|
||||
|
||||
BOOT_FROM sd
|
||||
|
||||
#ifdef CONFIG_USE_IMXIMG_PLUGIN
|
||||
/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
|
||||
PLUGIN board/freescale/mx7d_12x12_lpddr3_arm2/plugin.bin 0x00910000
|
||||
#else
|
||||
|
||||
#ifdef CONFIG_SECURE_BOOT
|
||||
CSF CONFIG_CSF_SIZE
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Device Configuration Data (DCD)
|
||||
*
|
||||
* Each entry must have the format:
|
||||
* Addr-type Address Value
|
||||
*
|
||||
* where:
|
||||
* Addr-type register length (1,2 or 4 bytes)
|
||||
* Address absolute address of the register
|
||||
* value value to be stored in the register
|
||||
*/
|
||||
|
||||
DATA 4 0x30340004 0x4F400005
|
||||
/* Clear then set bit30 to ensure exit from DDR retention */
|
||||
DATA 4 0x30360388 0x40000000
|
||||
DATA 4 0x30360384 0x40000000
|
||||
|
||||
DATA 4 0x30391000 0x00000002
|
||||
DATA 4 0x307a0000 0x03040008
|
||||
DATA 4 0x307a0064 0x00200038
|
||||
DATA 4 0x307a0490 0x00000001
|
||||
DATA 4 0x307a00d0 0x00350001
|
||||
DATA 4 0x307a00dc 0x00c3000a
|
||||
DATA 4 0x307a00e0 0x00010000
|
||||
DATA 4 0x307a00e4 0x00110006
|
||||
DATA 4 0x307a00f4 0x0000033f
|
||||
DATA 4 0x307a0100 0x0a0e110b
|
||||
DATA 4 0x307a0104 0x00020211
|
||||
DATA 4 0x307a0108 0x03060708
|
||||
DATA 4 0x307a010c 0x00a0500c
|
||||
DATA 4 0x307a0110 0x05020307
|
||||
DATA 4 0x307a0114 0x02020404
|
||||
DATA 4 0x307a0118 0x02020003
|
||||
DATA 4 0x307a011c 0x00000202
|
||||
DATA 4 0x307a0120 0x00000202
|
||||
|
||||
DATA 4 0x307a0180 0x00600018
|
||||
DATA 4 0x307a0184 0x00e00100
|
||||
DATA 4 0x307a0190 0x02098205
|
||||
DATA 4 0x307a0194 0x00060303
|
||||
DATA 4 0x307a01a0 0x80400003
|
||||
DATA 4 0x307a01a4 0x00100020
|
||||
DATA 4 0x307a01a8 0x80100004
|
||||
|
||||
DATA 4 0x307a0200 0x00000016
|
||||
DATA 4 0x307a0204 0x00090909
|
||||
DATA 4 0x307a0210 0x00000f00
|
||||
DATA 4 0x307a0214 0x08080808
|
||||
DATA 4 0x307a0218 0x0f0f0808
|
||||
|
||||
DATA 4 0x307a0240 0x06000600
|
||||
DATA 4 0x307a0244 0x00000000
|
||||
DATA 4 0x30391000 0x00000000
|
||||
DATA 4 0x30790000 0x17421e40
|
||||
DATA 4 0x30790004 0x10210100
|
||||
DATA 4 0x30790008 0x00010000
|
||||
DATA 4 0x30790010 0x0007080c
|
||||
DATA 4 0x307900b0 0x1010007e
|
||||
|
||||
DATA 4 0x3079001C 0x01010000
|
||||
DATA 4 0x3079009c 0x00000b24
|
||||
|
||||
DATA 4 0x30790030 0x06060606
|
||||
DATA 4 0x30790020 0x0a0a0a0a
|
||||
DATA 4 0x30790050 0x01000008
|
||||
DATA 4 0x30790050 0x00000008
|
||||
DATA 4 0x30790018 0x0000000f
|
||||
DATA 4 0x307900c0 0x0e487304
|
||||
DATA 4 0x307900c0 0x0e4c7304
|
||||
DATA 4 0x307900c0 0x0e4c7306
|
||||
CHECK_BITS_SET 4 0x307900c4 0x1
|
||||
|
||||
DATA 4 0x307900c0 0x0e487304
|
||||
|
||||
DATA 4 0x30384130 0x00000000
|
||||
DATA 4 0x30340020 0x00000178
|
||||
DATA 4 0x30384130 0x00000002
|
||||
|
||||
CHECK_BITS_SET 4 0x307a0004 0x1
|
||||
#endif
|
||||
|
|
@ -0,0 +1,121 @@
|
|||
/*
|
||||
* Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* Refer docs/README.imxmage for more details about how-to configure
|
||||
* and create imximage boot image
|
||||
*
|
||||
* The syntax is taken as close as possible with the kwbimage
|
||||
*/
|
||||
|
||||
#define __ASSEMBLY__
|
||||
#include <config.h>
|
||||
|
||||
/* image version */
|
||||
|
||||
IMAGE_VERSION 2
|
||||
|
||||
/*
|
||||
* Boot Device : one of
|
||||
* spi/sd/nand/onenand, qspi/nor
|
||||
*/
|
||||
|
||||
BOOT_FROM sd
|
||||
|
||||
#ifdef CONFIG_USE_IMXIMG_PLUGIN
|
||||
/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
|
||||
PLUGIN board/freescale/mx7d_12x12_lpddr3_arm2/plugin.bin 0x00910000
|
||||
#else
|
||||
|
||||
#ifdef CONFIG_SECURE_BOOT
|
||||
CSF CONFIG_CSF_SIZE
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Device Configuration Data (DCD)
|
||||
*
|
||||
* Each entry must have the format:
|
||||
* Addr-type Address Value
|
||||
*
|
||||
* where:
|
||||
* Addr-type register length (1,2 or 4 bytes)
|
||||
* Address absolute address of the register
|
||||
* value value to be stored in the register
|
||||
*/
|
||||
|
||||
DATA 4 0x30340004 0x4F400005
|
||||
/* Clear then set bit30 to ensure exit from DDR retention */
|
||||
DATA 4 0x30360388 0x40000000
|
||||
DATA 4 0x30360384 0x40000000
|
||||
|
||||
DATA 4 0x30391000 0x00000002
|
||||
DATA 4 0x307a0000 0x03040008
|
||||
DATA 4 0x307a0064 0x00200038
|
||||
DATA 4 0x307a0490 0x00000001
|
||||
DATA 4 0x307a00d0 0x00350001
|
||||
DATA 4 0x307a00dc 0x00c3000a
|
||||
DATA 4 0x307a00e0 0x00010000
|
||||
DATA 4 0x307a00e4 0x00110006
|
||||
DATA 4 0x307a00f4 0x0000033f
|
||||
DATA 4 0x307a0100 0x0a0e110b
|
||||
DATA 4 0x307a0104 0x00020211
|
||||
DATA 4 0x307a0108 0x03060708
|
||||
DATA 4 0x307a010c 0x00a0500c
|
||||
DATA 4 0x307a0110 0x05020307
|
||||
DATA 4 0x307a0114 0x02020404
|
||||
DATA 4 0x307a0118 0x02020003
|
||||
DATA 4 0x307a011c 0x00000202
|
||||
DATA 4 0x307a0120 0x00000202
|
||||
|
||||
DATA 4 0x307a0180 0x00600018
|
||||
DATA 4 0x307a0184 0x00e00100
|
||||
DATA 4 0x307a0190 0x02098205
|
||||
DATA 4 0x307a0194 0x00060303
|
||||
DATA 4 0x307a01a0 0x80400003
|
||||
DATA 4 0x307a01a4 0x00100020
|
||||
DATA 4 0x307a01a8 0x80100004
|
||||
|
||||
DATA 4 0x307a0200 0x00000016
|
||||
DATA 4 0x307a0204 0x00090909
|
||||
DATA 4 0x307a0210 0x00000f00
|
||||
DATA 4 0x307a0214 0x08080808
|
||||
DATA 4 0x307a0218 0x0f0f0808
|
||||
|
||||
DATA 4 0x307a0240 0x06000601
|
||||
DATA 4 0x307a0244 0x00000000
|
||||
DATA 4 0x30391000 0x00000000
|
||||
DATA 4 0x30790000 0x17421e40
|
||||
DATA 4 0x30790004 0x10210100
|
||||
DATA 4 0x30790008 0x00010000
|
||||
DATA 4 0x30790010 0x0007080c
|
||||
DATA 4 0x3079007c 0x1c1c1c1c
|
||||
DATA 4 0x30790080 0x1c1c1c1c
|
||||
DATA 4 0x30790084 0x30301c1c
|
||||
DATA 4 0x30790088 0x00000030
|
||||
DATA 4 0x3079006c 0x30303030
|
||||
DATA 4 0x307900b0 0x1010007e
|
||||
|
||||
DATA 4 0x3079001C 0x01010000
|
||||
DATA 4 0x3079009c 0x0db60d6e
|
||||
|
||||
DATA 4 0x30790030 0x06060606
|
||||
DATA 4 0x30790020 0x0a0a0a0a
|
||||
DATA 4 0x30790050 0x01000008
|
||||
DATA 4 0x30790050 0x00000008
|
||||
DATA 4 0x30790018 0x0000000f
|
||||
DATA 4 0x307900c0 0x1e487304
|
||||
DATA 4 0x307900c0 0x1e487304
|
||||
DATA 4 0x307900c0 0x1e487306
|
||||
DATA 4 0x307900c0 0x1e4c7304
|
||||
CHECK_BITS_SET 4 0x307900c4 0x1
|
||||
|
||||
DATA 4 0x307900c0 0x1e487304
|
||||
|
||||
DATA 4 0x30384130 0x00000000
|
||||
DATA 4 0x30340020 0x00000178
|
||||
DATA 4 0x30384130 0x00000002
|
||||
|
||||
CHECK_BITS_SET 4 0x307a0004 0x1
|
||||
#endif
|
||||
|
|
@ -0,0 +1,659 @@
|
|||
/*
|
||||
* Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/mx7-pins.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/mach-imx/iomux-v3.h>
|
||||
#include <asm/mach-imx/boot_mode.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <common.h>
|
||||
#include <fsl_esdhc.h>
|
||||
#include <mmc.h>
|
||||
#include <miiphy.h>
|
||||
#include <netdev.h>
|
||||
#include <power/pmic.h>
|
||||
#include <power/pfuze3000_pmic.h>
|
||||
#include "../common/pfuze.h"
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/mach-imx/video.h>
|
||||
|
||||
#ifdef CONFIG_VIDEO_MXS
|
||||
#include <linux/fb.h>
|
||||
#endif
|
||||
#if defined(CONFIG_MXC_EPDC)
|
||||
#include <lcd.h>
|
||||
#include <mxc_epdc_fb.h>
|
||||
#endif
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
|
||||
PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
|
||||
|
||||
#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM)
|
||||
#define ENET_PAD_CTRL_MII (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM)
|
||||
|
||||
#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM)
|
||||
|
||||
#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
|
||||
PAD_CTL_DSE_3P3V_49OHM)
|
||||
|
||||
#define QSPI_PAD_CTRL \
|
||||
(PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
|
||||
|
||||
#define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
|
||||
|
||||
#define EPDC_PAD_CTRL 0x0
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->ram_size = PHYS_SDRAM_SIZE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static iomux_v3_cfg_t const uart1_pads[] = {
|
||||
MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
#ifdef CONFIG_VIDEO_MXS
|
||||
static iomux_v3_cfg_t const lcd_pads[] = {
|
||||
MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
|
||||
MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const pwm_pads[] = {
|
||||
/* Use GPIO for Brightness adjustment, duty cycle = period */
|
||||
MX7D_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
void do_enable_parallel_lcd(struct display_info_t const *dev)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads));
|
||||
|
||||
/* Power up the LCD */
|
||||
gpio_request(IMX_GPIO_NR(3, 4), "lcd_pwr");
|
||||
gpio_direction_output(IMX_GPIO_NR(3, 4) , 1);
|
||||
|
||||
/* Set Brightness to high */
|
||||
gpio_request(IMX_GPIO_NR(1, 1), "lcd_backlight");
|
||||
gpio_direction_output(IMX_GPIO_NR(1, 1) , 1);
|
||||
}
|
||||
|
||||
struct display_info_t const displays[] = {{
|
||||
.bus = ELCDIF1_IPS_BASE_ADDR,
|
||||
.addr = 0,
|
||||
.pixfmt = 24,
|
||||
.detect = NULL,
|
||||
.enable = do_enable_parallel_lcd,
|
||||
.mode = {
|
||||
.name = "MCIMX28LCD",
|
||||
.xres = 800,
|
||||
.yres = 480,
|
||||
.pixclock = 29850,
|
||||
.left_margin = 89,
|
||||
.right_margin = 164,
|
||||
.upper_margin = 23,
|
||||
.lower_margin = 10,
|
||||
.hsync_len = 10,
|
||||
.vsync_len = 10,
|
||||
.sync = 0,
|
||||
.vmode = FB_VMODE_NONINTERLACED
|
||||
} } };
|
||||
size_t display_count = ARRAY_SIZE(displays);
|
||||
#endif
|
||||
|
||||
|
||||
static iomux_v3_cfg_t const per_rst_pads[] = {
|
||||
MX7D_PAD_GPIO1_IO03__GPIO1_IO3 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const wdog_pads[] = {
|
||||
MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
static iomux_v3_cfg_t const fec1_pads[] = {
|
||||
MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
|
||||
MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
|
||||
MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX7D_PAD_ENET1_TX_CLK__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void setup_iomux_fec1(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
|
||||
}
|
||||
#endif
|
||||
|
||||
static void setup_iomux_uart(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FSL_QSPI
|
||||
#ifndef CONFIG_DM_SPI
|
||||
static iomux_v3_cfg_t const quadspi_pads[] = {
|
||||
MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA04__QSPI_A_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
|
||||
MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA12__QSPI_B_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
|
||||
};
|
||||
#endif
|
||||
|
||||
int board_qspi_init(void)
|
||||
{
|
||||
#ifndef CONFIG_DM_SPI
|
||||
/* Set the iomux */
|
||||
imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads));
|
||||
#endif
|
||||
|
||||
/* Set the clock */
|
||||
set_clk_qspi();
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
int mmc_map_to_kernel_blk(int dev_no)
|
||||
{
|
||||
return dev_no;
|
||||
}
|
||||
|
||||
int board_mmc_get_env_dev(int devno)
|
||||
{
|
||||
return devno;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int ret;
|
||||
|
||||
setup_iomux_fec1();
|
||||
|
||||
ret = fecmxc_initialize_multi(bis, 0,
|
||||
CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
|
||||
if (ret)
|
||||
printf("FEC1 MXC: %s:failed\n", __func__);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int setup_fec(void)
|
||||
{
|
||||
struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
|
||||
= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
|
||||
int ret;
|
||||
|
||||
/* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
|
||||
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
|
||||
(IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
|
||||
IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
|
||||
|
||||
ret = set_clk_enet(ENET_125MHZ);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
/* Enable 1.8V(SEL_1P5_1P8_POS_REG) on
|
||||
Phy control debug reg 0 */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
|
||||
|
||||
/* rgmii tx clock delay enable */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
|
||||
|
||||
if (phydev->drv->config)
|
||||
phydev->drv->config(phydev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MXC_SPI
|
||||
iomux_v3_cfg_t const ecspi1_pads[] = {
|
||||
MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
|
||||
/* CS0 */
|
||||
MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
void setup_spinor(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
|
||||
ARRAY_SIZE(ecspi1_pads));
|
||||
gpio_request(IMX_GPIO_NR(4, 19), "ecspi1_cs");
|
||||
gpio_direction_output(IMX_GPIO_NR(4, 19), 0);
|
||||
}
|
||||
|
||||
int board_spi_cs_gpio(unsigned bus, unsigned cs)
|
||||
{
|
||||
return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 19)) : -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
setup_iomux_uart();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MXC_EPDC
|
||||
static iomux_v3_cfg_t const epdc_enable_pads[] = {
|
||||
MX7D_PAD_EPDC_DATA00__EPDC_DATA0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA01__EPDC_DATA1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA02__EPDC_DATA2 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA03__EPDC_DATA3 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA04__EPDC_DATA4 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA05__EPDC_DATA5 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA06__EPDC_DATA6 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA07__EPDC_DATA7 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_SDLE__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_SDOE__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_SDCE2__EPDC_SDCE2 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_SDCE3__EPDC_SDCE3 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_GDOE__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_GDRL__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_GDSP__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_BDR0__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_BDR1__EPDC_BDR1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const epdc_disable_pads[] = {
|
||||
MX7D_PAD_EPDC_DATA00__GPIO2_IO0,
|
||||
MX7D_PAD_EPDC_DATA01__GPIO2_IO1,
|
||||
MX7D_PAD_EPDC_DATA02__GPIO2_IO2,
|
||||
MX7D_PAD_EPDC_DATA03__GPIO2_IO3,
|
||||
MX7D_PAD_EPDC_DATA04__GPIO2_IO4,
|
||||
MX7D_PAD_EPDC_DATA05__GPIO2_IO5,
|
||||
MX7D_PAD_EPDC_DATA06__GPIO2_IO6,
|
||||
MX7D_PAD_EPDC_DATA07__GPIO2_IO7,
|
||||
MX7D_PAD_EPDC_SDCLK__GPIO2_IO16,
|
||||
MX7D_PAD_EPDC_SDLE__GPIO2_IO17,
|
||||
MX7D_PAD_EPDC_SDOE__GPIO2_IO18,
|
||||
MX7D_PAD_EPDC_SDSHR__GPIO2_IO19,
|
||||
MX7D_PAD_EPDC_SDCE0__GPIO2_IO20,
|
||||
MX7D_PAD_EPDC_SDCE1__GPIO2_IO21,
|
||||
MX7D_PAD_EPDC_SDCE2__GPIO2_IO22,
|
||||
MX7D_PAD_EPDC_SDCE3__GPIO2_IO23,
|
||||
MX7D_PAD_EPDC_GDCLK__GPIO2_IO24,
|
||||
MX7D_PAD_EPDC_GDOE__GPIO2_IO25,
|
||||
MX7D_PAD_EPDC_GDRL__GPIO2_IO26,
|
||||
MX7D_PAD_EPDC_GDSP__GPIO2_IO27,
|
||||
MX7D_PAD_EPDC_BDR0__GPIO2_IO28,
|
||||
MX7D_PAD_EPDC_BDR1__GPIO2_IO29,
|
||||
};
|
||||
|
||||
vidinfo_t panel_info = {
|
||||
.vl_refresh = 85,
|
||||
.vl_col = 1024,
|
||||
.vl_row = 758,
|
||||
.vl_pixclock = 40000000,
|
||||
.vl_left_margin = 12,
|
||||
.vl_right_margin = 76,
|
||||
.vl_upper_margin = 4,
|
||||
.vl_lower_margin = 5,
|
||||
.vl_hsync = 12,
|
||||
.vl_vsync = 2,
|
||||
.vl_sync = 0,
|
||||
.vl_mode = 0,
|
||||
.vl_flag = 0,
|
||||
.vl_bpix = 3,
|
||||
.cmap = 0,
|
||||
};
|
||||
|
||||
struct epdc_timing_params panel_timings = {
|
||||
.vscan_holdoff = 4,
|
||||
.sdoed_width = 10,
|
||||
.sdoed_delay = 20,
|
||||
.sdoez_width = 10,
|
||||
.sdoez_delay = 20,
|
||||
.gdclk_hp_offs = 524,
|
||||
.gdsp_offs = 327,
|
||||
.gdoe_offs = 0,
|
||||
.gdclk_offs = 19,
|
||||
.num_ce = 1,
|
||||
};
|
||||
|
||||
static void setup_epdc_power(void)
|
||||
{
|
||||
/* IOMUX_GPR1: bit30: Disable On-chip RAM EPDC Function */
|
||||
struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
|
||||
= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
|
||||
|
||||
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
|
||||
IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK, 0);
|
||||
|
||||
/* Setup epdc voltage */
|
||||
|
||||
/* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */
|
||||
imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 |
|
||||
MUX_PAD_CTRL(EPDC_PAD_CTRL));
|
||||
gpio_request(IMX_GPIO_NR(2, 31), "epdc_pwrstat");
|
||||
gpio_direction_input(IMX_GPIO_NR(2, 31));
|
||||
|
||||
/* EPDC_VCOM0 - GPIO4[14] for VCOM control */
|
||||
imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 |
|
||||
MUX_PAD_CTRL(EPDC_PAD_CTRL));
|
||||
|
||||
/* Set as output */
|
||||
gpio_request(IMX_GPIO_NR(4, 14), "epdc_vcom0");
|
||||
gpio_direction_output(IMX_GPIO_NR(4, 14), 1);
|
||||
|
||||
/* EPDC_PWRWAKEUP - GPIO4[23] for EPD PMIC WAKEUP */
|
||||
imx_iomux_v3_setup_pad(MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 |
|
||||
MUX_PAD_CTRL(EPDC_PAD_CTRL));
|
||||
/* Set as output */
|
||||
gpio_request(IMX_GPIO_NR(4, 23), "epdc_pwrwakeup");
|
||||
gpio_direction_output(IMX_GPIO_NR(4, 23), 1);
|
||||
|
||||
/* EPDC_PWRCTRL0 - GPIO4[20] for EPD PWR CTL0 */
|
||||
imx_iomux_v3_setup_pad(MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 |
|
||||
MUX_PAD_CTRL(EPDC_PAD_CTRL));
|
||||
/* Set as output */
|
||||
gpio_request(IMX_GPIO_NR(4, 20), "epdc_pwrctrl0");
|
||||
gpio_direction_output(IMX_GPIO_NR(4, 20), 1);
|
||||
}
|
||||
|
||||
static void epdc_enable_pins(void)
|
||||
{
|
||||
/* epdc iomux settings */
|
||||
imx_iomux_v3_setup_multiple_pads(epdc_enable_pads,
|
||||
ARRAY_SIZE(epdc_enable_pads));
|
||||
}
|
||||
|
||||
static void epdc_disable_pins(void)
|
||||
{
|
||||
/* Configure MUX settings for EPDC pins to GPIO and drive to 0 */
|
||||
imx_iomux_v3_setup_multiple_pads(epdc_disable_pads,
|
||||
ARRAY_SIZE(epdc_disable_pads));
|
||||
}
|
||||
|
||||
static void setup_epdc(void)
|
||||
{
|
||||
/*** epdc Maxim PMIC settings ***/
|
||||
|
||||
/* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */
|
||||
imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 |
|
||||
MUX_PAD_CTRL(EPDC_PAD_CTRL));
|
||||
|
||||
/* EPDC_VCOM0 - GPIO4[14] for VCOM control */
|
||||
imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 |
|
||||
MUX_PAD_CTRL(EPDC_PAD_CTRL));
|
||||
|
||||
/* EPDC_PWRWAKEUP - GPIO4[23] for EPD PMIC WAKEUP */
|
||||
imx_iomux_v3_setup_pad(MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 |
|
||||
MUX_PAD_CTRL(EPDC_PAD_CTRL));
|
||||
|
||||
/* EPDC_PWRCTRL0 - GPIO4[20] for EPD PWR CTL0 */
|
||||
imx_iomux_v3_setup_pad(MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 |
|
||||
MUX_PAD_CTRL(EPDC_PAD_CTRL));
|
||||
|
||||
/* Set pixel clock rates for EPDC in clock.c */
|
||||
|
||||
panel_info.epdc_data.wv_modes.mode_init = 0;
|
||||
panel_info.epdc_data.wv_modes.mode_du = 1;
|
||||
panel_info.epdc_data.wv_modes.mode_gc4 = 3;
|
||||
panel_info.epdc_data.wv_modes.mode_gc8 = 2;
|
||||
panel_info.epdc_data.wv_modes.mode_gc16 = 2;
|
||||
panel_info.epdc_data.wv_modes.mode_gc32 = 2;
|
||||
|
||||
panel_info.epdc_data.epdc_timings = panel_timings;
|
||||
|
||||
setup_epdc_power();
|
||||
}
|
||||
|
||||
void epdc_power_on(void)
|
||||
{
|
||||
unsigned int reg;
|
||||
struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR;
|
||||
|
||||
/* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
|
||||
gpio_set_value(IMX_GPIO_NR(4, 20), 1);
|
||||
udelay(1000);
|
||||
|
||||
/* Enable epdc signal pin */
|
||||
epdc_enable_pins();
|
||||
|
||||
/* Set PMIC Wakeup to high - enable Display power */
|
||||
gpio_set_value(IMX_GPIO_NR(4, 23), 1);
|
||||
|
||||
/* Wait for PWRGOOD == 1 */
|
||||
while (1) {
|
||||
reg = readl(&gpio_regs->gpio_psr);
|
||||
if (!(reg & (1 << 31)))
|
||||
break;
|
||||
|
||||
udelay(100);
|
||||
}
|
||||
|
||||
/* Enable VCOM */
|
||||
gpio_set_value(IMX_GPIO_NR(4, 14), 1);
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
|
||||
void epdc_power_off(void)
|
||||
{
|
||||
/* Set PMIC Wakeup to low - disable Display power */
|
||||
gpio_set_value(IMX_GPIO_NR(4, 23), 0);
|
||||
|
||||
/* Disable VCOM */
|
||||
gpio_set_value(IMX_GPIO_NR(4, 14), 0);
|
||||
|
||||
epdc_disable_pins();
|
||||
|
||||
/* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
|
||||
gpio_set_value(IMX_GPIO_NR(4, 20), 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
||||
|
||||
/* Reset peripherals */
|
||||
imx_iomux_v3_setup_multiple_pads(per_rst_pads, ARRAY_SIZE(per_rst_pads));
|
||||
|
||||
gpio_request(IMX_GPIO_NR(1, 3), "per_rst");
|
||||
gpio_direction_output(IMX_GPIO_NR(1, 3) , 0);
|
||||
udelay(500);
|
||||
gpio_set_value(IMX_GPIO_NR(1, 3), 1);
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
setup_fec();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MXC_SPI
|
||||
setup_spinor();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_QSPI
|
||||
board_qspi_init();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MXC_EPDC
|
||||
setup_epdc();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
static const struct boot_mode board_boot_modes[] = {
|
||||
/* 4 bit bus width */
|
||||
{"sd1", MAKE_CFGVAL(0x10, 0x12, 0x00, 0x00)},
|
||||
{"sd2", MAKE_CFGVAL(0x10, 0x16, 0x00, 0x00)},
|
||||
{"emmc", MAKE_CFGVAL(0x10, 0x2a, 0x00, 0x00)},
|
||||
{"qspi", MAKE_CFGVAL(0x00, 0x40, 0x00, 0x00)},
|
||||
{NULL, 0},
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DM_PMIC
|
||||
int power_init_board(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret, dev_id, rev_id, reg;
|
||||
|
||||
ret = pmic_get("pfuze3000", &dev);
|
||||
if (ret == -ENODEV)
|
||||
return 0;
|
||||
if (ret != 0)
|
||||
return ret;
|
||||
|
||||
dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
|
||||
rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
|
||||
printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
|
||||
|
||||
/* disable Low Power Mode during standby mode */
|
||||
reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
|
||||
reg |= 0x1;
|
||||
pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);
|
||||
|
||||
/* SW1A/1B mode set to APS/APS */
|
||||
reg = 0x8;
|
||||
pmic_reg_write(dev, PFUZE3000_SW1AMODE, reg);
|
||||
pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg);
|
||||
|
||||
/* SW1A/1B standby voltage set to 0.975V */
|
||||
reg = 0xb;
|
||||
pmic_reg_write(dev, PFUZE3000_SW1ASTBY, reg);
|
||||
pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg);
|
||||
|
||||
/* below are for LPSR mode support */
|
||||
reg = pmic_reg_read(dev, PFUZE3000_SW3MODE);
|
||||
reg |= 0x20;
|
||||
pmic_reg_write(dev, PFUZE3000_SW3MODE, reg);
|
||||
|
||||
reg = pmic_reg_read(dev, PFUZE3000_VLDO1CTL);
|
||||
reg |= 0x80;
|
||||
pmic_reg_write(dev, PFUZE3000_VLDO1CTL, reg);
|
||||
|
||||
reg = pmic_reg_read(dev, PFUZE3000_VLDO3CTL);
|
||||
reg |= 0x80;
|
||||
pmic_reg_write(dev, PFUZE3000_VLDO3CTL, reg);
|
||||
|
||||
reg = pmic_reg_read(dev, PFUZE3000_SW2MODE);
|
||||
reg |= 0x20;
|
||||
pmic_reg_write(dev, PFUZE3000_SW2MODE, reg);
|
||||
|
||||
/* set SW1B normal voltage to 0.975V */
|
||||
reg = pmic_reg_read(dev, PFUZE3000_SW1BVOLT);
|
||||
reg &= ~0x1f;
|
||||
reg |= PFUZE3000_SW1AB_SETP(9750);
|
||||
pmic_reg_write(dev, PFUZE3000_SW1BVOLT, reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
add_board_boot_modes(board_boot_modes);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_MMC
|
||||
board_late_mmc_env_init();
|
||||
#endif
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
|
||||
|
||||
set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
u32 get_board_rev(void)
|
||||
{
|
||||
return get_cpu_rev();
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: MX7D 12x12 LPDDR3 ARM2\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,657 @@
|
|||
/*
|
||||
* Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
|
||||
/* DDR script */
|
||||
.macro imx7d_ddrphy_latency_setting
|
||||
ldr r2, =ANATOP_BASE_ADDR
|
||||
ldr r3, [r2, #0x800]
|
||||
and r3, r3, #0xFF
|
||||
cmp r3, #0x11
|
||||
bne TUNE_END
|
||||
|
||||
/*TO 1.1*/
|
||||
ldr r1, =0x1c1c1c1c
|
||||
str r1, [r0, #0x7c]
|
||||
ldr r1, =0x1c1c1c1c
|
||||
str r1, [r0, #0x80]
|
||||
ldr r1, =0x30301c1c
|
||||
str r1, [r0, #0x84]
|
||||
ldr r1, =0x00000030
|
||||
str r1, [r0, #0x88]
|
||||
ldr r1, =0x30303030
|
||||
str r1, [r0, #0x6c]
|
||||
|
||||
TUNE_END:
|
||||
.endm
|
||||
|
||||
.macro imx7d_12x12_lpddr3_arm2_setting
|
||||
|
||||
/* check whether it is a LPSR resume */
|
||||
ldr r1, =0x30270000
|
||||
ldr r7, [r1]
|
||||
cmp r7, #0
|
||||
beq 16f
|
||||
|
||||
/* disable wdog powerdown counter */
|
||||
ldr r0, =0x30280000
|
||||
ldrh r1, =0x0
|
||||
strh r1, [r0, #0x8]
|
||||
|
||||
/* initialize AIPs 1-3 port */
|
||||
ldr r0, =0x301f0000
|
||||
ldr r1, =0x77777777
|
||||
str r1, [r0]
|
||||
str r1, [r0, #0x4]
|
||||
ldr r1, =0x0
|
||||
str r1, [r0, #0x40]
|
||||
str r1, [r0, #0x44]
|
||||
str r1, [r0, #0x48]
|
||||
str r1, [r0, #0x4c]
|
||||
str r1, [r0, #0x50]
|
||||
|
||||
ldr r0, =0x305f0000
|
||||
ldr r1, =0x77777777
|
||||
str r1, [r0]
|
||||
str r1, [r0, #0x4]
|
||||
ldr r1, =0x0
|
||||
str r1, [r0, #0x40]
|
||||
str r1, [r0, #0x44]
|
||||
str r1, [r0, #0x48]
|
||||
str r1, [r0, #0x4c]
|
||||
str r1, [r0, #0x50]
|
||||
|
||||
ldr r0, =0x309f0000
|
||||
ldr r1, =0x77777777
|
||||
str r1, [r0]
|
||||
str r1, [r0, #0x4]
|
||||
ldr r1, =0x0
|
||||
str r1, [r0, #0x40]
|
||||
str r1, [r0, #0x44]
|
||||
str r1, [r0, #0x48]
|
||||
str r1, [r0, #0x4c]
|
||||
str r1, [r0, #0x50]
|
||||
|
||||
ldr r1, =0x30360000
|
||||
ldr r2, =0x30390000
|
||||
ldr r3, =0x307a0000
|
||||
ldr r4, =0x30790000
|
||||
ldr r10, =0x30380000
|
||||
ldr r11, =0x30340000
|
||||
|
||||
/* turn on ddr power */
|
||||
ldr r7, =(0x1 << 29)
|
||||
str r7, [r1, #0x388]
|
||||
|
||||
ldr r6, =50
|
||||
1:
|
||||
subs r6, r6, #0x1
|
||||
bne 1b
|
||||
|
||||
/* clear ddr_phy reset */
|
||||
ldr r6, =0x1000
|
||||
ldr r7, [r2, r6]
|
||||
orr r7, r7, #0x3
|
||||
str r7, [r2, r6]
|
||||
ldr r7, [r2, r6]
|
||||
bic r7, r7, #0x1
|
||||
str r7, [r2, r6]
|
||||
|
||||
/* restore DDRC */
|
||||
ldr r6, =0x0
|
||||
ldr r7, =0x03040008
|
||||
str r7, [r3, r6]
|
||||
|
||||
ldr r6, =0x1a0
|
||||
ldr r7, =0x80400003
|
||||
str r7, [r3, r6]
|
||||
|
||||
ldr r6, =0x1a4
|
||||
ldr r7, =0x00100020
|
||||
str r7, [r3, r6]
|
||||
|
||||
ldr r6, =0x1a8
|
||||
ldr r7, =0x80100004
|
||||
str r7, [r3, r6]
|
||||
|
||||
ldr r6, =0x64
|
||||
ldr r7, =0x00200038
|
||||
str r7, [r3, r6]
|
||||
|
||||
ldr r6, =0xd0
|
||||
ldr r7, =0xc0350001
|
||||
str r7, [r3, r6]
|
||||
|
||||
ldr r6, =0xdc
|
||||
ldr r7, =0x00C3000A
|
||||
str r7, [r3, r6]
|
||||
|
||||
ldr r6, =0xe0
|
||||
ldr r7, =0x00010000
|
||||
str r7, [r3, r6]
|
||||
|
||||
ldr r6, =0xe4
|
||||
ldr r7, =0x00110006
|
||||
str r7, [r3, r6]
|
||||
|
||||
ldr r6, =0xf4
|
||||
ldr r7, =0x0000033F
|
||||
str r7, [r3, r6]
|
||||
|
||||
ldr r6, =0x100
|
||||
ldr r7, =0x0A0E110B
|
||||
str r7, [r3, r6]
|
||||
|
||||
ldr r6, =0x104
|
||||
ldr r7, =0x00020211
|
||||
str r7, [r3, r6]
|
||||
|
||||
ldr r6, =0x108
|
||||
ldr r7, =0x03060708
|
||||
str r7, [r3, r6]
|
||||
|
||||
ldr r6, =0x10c
|
||||
ldr r7, =0x00A0500C
|
||||
str r7, [r3, r6]
|
||||
|
||||
ldr r6, =0x110
|
||||
ldr r7, =0x05020307
|
||||
str r7, [r3, r6]
|
||||
|
||||
ldr r6, =0x114
|
||||
ldr r7, =0x02020404
|
||||
str r7, [r3, r6]
|
||||
|
||||
ldr r6, =0x118
|
||||
ldr r7, =0x02020003
|
||||
str r7, [r3, r6]
|
||||
|
||||
ldr r6, =0x11c
|
||||
ldr r7, =0x00000202
|
||||
str r7, [r3, r6]
|
||||
|
||||
ldr r6, =0x120
|
||||
ldr r7, =0x00000202
|
||||
str r7, [r3, r6]
|
||||
|
||||
ldr r6, =0x180
|
||||
ldr r7, =0x00600018
|
||||
str r7, [r3, r6]
|
||||
|
||||
ldr r6, =0x184
|
||||
ldr r7, =0x00e00100
|
||||
str r7, [r3, r6]
|
||||
|
||||
ldr r6, =0x190
|
||||
ldr r7, =0x02098205
|
||||
str r7, [r3, r6]
|
||||
|
||||
ldr r6, =0x194
|
||||
ldr r7, =0x00060303
|
||||
str r7, [r3, r6]
|
||||
|
||||
ldr r6, =0x200
|
||||
ldr r7, =0x00000016
|
||||
str r7, [r3, r6]
|
||||
|
||||
ldr r6, =0x204
|
||||
ldr r7, =0x00090909
|
||||
str r7, [r3, r6]
|
||||
|
||||
ldr r6, =0x210
|
||||
ldr r7, =0xF00
|
||||
str r7, [r3, r6]
|
||||
|
||||
ldr r6, =0x214
|
||||
ldr r7, =0x08080808
|
||||
str r7, [r3, r6]
|
||||
|
||||
ldr r6, =0x218
|
||||
ldr r7, =0x0f0f0808
|
||||
str r7, [r3, r6]
|
||||
|
||||
ldr r6, =0x240
|
||||
ldr r7, =0x06000600
|
||||
str r7, [r3, r6]
|
||||
|
||||
ldr r6, =0x244
|
||||
ldr r7, =0x00000000
|
||||
str r7, [r3, r6]
|
||||
|
||||
ldr r7, =0x20
|
||||
str r7, [r3, #0x30]
|
||||
ldr r7, =0x0
|
||||
str r7, [r3, #0x1b0]
|
||||
|
||||
/* do PHY, clear ddr_phy reset */
|
||||
ldr r6, =0x1000
|
||||
ldr r7, [r2, r6]
|
||||
bic r7, r7, #0x2
|
||||
str r7, [r2, r6]
|
||||
|
||||
ldr r7, [r1, #0x800]
|
||||
and r7, r7, #0xFF
|
||||
cmp r7, #0x11
|
||||
bne 2f
|
||||
|
||||
/* for TO1.1 */
|
||||
ldr r7, [r11]
|
||||
bic r7, r7, #(1 << 27)
|
||||
str r7, [r11]
|
||||
ldr r7, [r11]
|
||||
bic r7, r7, #(1 << 29)
|
||||
str r7, [r11]
|
||||
2:
|
||||
/* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */
|
||||
ldr r7, =(0x1 << 30)
|
||||
str r7, [r1, #0x388]
|
||||
ldr r7, =(0x1 << 30)
|
||||
str r7, [r1, #0x384]
|
||||
|
||||
/* need to delay ~5mS */
|
||||
ldr r6, =0x100000
|
||||
3:
|
||||
subs r6, r6, #0x1
|
||||
bne 3b
|
||||
|
||||
/* restore DDR PHY */
|
||||
ldr r6, =0x0
|
||||
ldr r7, =0x17421E40
|
||||
str r7, [r4, r6]
|
||||
|
||||
ldr r6, =0x4
|
||||
ldr r7, =0x10210100
|
||||
str r7, [r4, r6]
|
||||
|
||||
ldr r6, =0x8
|
||||
ldr r7, =0x00010000
|
||||
str r7, [r4, r6]
|
||||
|
||||
ldr r6, =0x10
|
||||
ldr r7, =0x0007080C
|
||||
str r7, [r4, r6]
|
||||
|
||||
ldr r6, =0xb0
|
||||
ldr r7, =0x1010007e
|
||||
str r7, [r4, r6]
|
||||
|
||||
ldr r7, [r1, #0x800]
|
||||
and r7, r7, #0xFF
|
||||
cmp r7, #0x11
|
||||
bne 4f
|
||||
|
||||
ldr r6, =0x7c
|
||||
ldr r7, =0x1c1c1c1c
|
||||
str r7, [r4, r6]
|
||||
|
||||
ldr r6, =0x80
|
||||
ldr r7, =0x1c1c1c1c
|
||||
str r7, [r4, r6]
|
||||
|
||||
ldr r6, =0x84
|
||||
ldr r7, =0x30301c1c
|
||||
str r7, [r4, r6]
|
||||
|
||||
ldr r6, =0x88
|
||||
ldr r7, =0x00000030
|
||||
str r7, [r4, r6]
|
||||
|
||||
ldr r6, =0x6c
|
||||
ldr r7, =0x30303030
|
||||
str r7, [r4, r6]
|
||||
|
||||
ldr r6, =0x1c
|
||||
ldr r7, =0x01010000
|
||||
str r7, [r4, r6]
|
||||
|
||||
ldr r6, =0x9c
|
||||
ldr r7, =0x0DB60D6E
|
||||
str r7, [r4, r6]
|
||||
|
||||
b 5f
|
||||
|
||||
4:
|
||||
ldr r6, =0x1c
|
||||
ldr r7, =0x01010000
|
||||
str r7, [r4, r6]
|
||||
|
||||
ldr r6, =0x9c
|
||||
ldr r7, =0x00000b24
|
||||
str r7, [r4, r6]
|
||||
|
||||
5:
|
||||
ldr r6, =0x20
|
||||
ldr r7, =0x0a0a0a0a
|
||||
str r7, [r4, r6]
|
||||
|
||||
ldr r6, =0x30
|
||||
ldr r7, =0x06060606
|
||||
str r7, [r4, r6]
|
||||
|
||||
ldr r6, =0x50
|
||||
ldr r7, =0x01000008
|
||||
str r7, [r4, r6]
|
||||
|
||||
ldr r6, =0x50
|
||||
ldr r7, =0x00000008
|
||||
str r7, [r4, r6]
|
||||
|
||||
ldr r6, =0xc0
|
||||
ldr r7, =0x0e487304
|
||||
str r7, [r4, r6]
|
||||
|
||||
ldr r6, =0xc0
|
||||
ldr r7, =0x0e4c7304
|
||||
str r7, [r4, r6]
|
||||
|
||||
ldr r6, =0xc0
|
||||
ldr r7, =0x0e4c7306
|
||||
str r7, [r4, r6]
|
||||
|
||||
6:
|
||||
ldr r7, [r4, #0xc4]
|
||||
tst r7, #0x1
|
||||
beq 6b
|
||||
|
||||
ldr r6, =0xc0
|
||||
ldr r7, =0x0e487304
|
||||
str r7, [r4, r6]
|
||||
|
||||
ldr r7, =0x0
|
||||
add r9, r10, #0x4000
|
||||
str r7, [r9, #0x130]
|
||||
|
||||
ldr r7, =0x170
|
||||
orr r7, r7, #0x8
|
||||
str r7, [r11, #0x20]
|
||||
|
||||
ldr r7, =0x2
|
||||
add r9, r10, #0x4000
|
||||
str r7, [r9, #0x130]
|
||||
|
||||
ldr r7, =0xf
|
||||
str r7, [r4, #0x18]
|
||||
|
||||
/* wait until self-refresh mode entered */
|
||||
11:
|
||||
ldr r7, [r3, #0x4]
|
||||
and r7, r7, #0x3
|
||||
cmp r7, #0x3
|
||||
bne 11b
|
||||
ldr r7, =0x0
|
||||
str r7, [r3, #0x320]
|
||||
ldr r7, =0x1
|
||||
str r7, [r3, #0x1b0]
|
||||
ldr r7, =0x1
|
||||
str r7, [r3, #0x320]
|
||||
12:
|
||||
ldr r7, [r3, #0x324]
|
||||
and r7, r7, #0x1
|
||||
cmp r7, #0x1
|
||||
bne 12b
|
||||
13:
|
||||
ldr r7, [r3, #0x4]
|
||||
and r7, r7, #0x20
|
||||
cmp r7, #0x20
|
||||
bne 13b
|
||||
|
||||
/* let DDR out of self-refresh */
|
||||
ldr r7, =0x0
|
||||
str r7, [r3, #0x30]
|
||||
14:
|
||||
ldr r7, [r3, #0x4]
|
||||
and r7, r7, #0x30
|
||||
cmp r7, #0x0
|
||||
bne 14b
|
||||
|
||||
15:
|
||||
ldr r7, [r3, #0x4]
|
||||
and r7, r7, #0x3
|
||||
cmp r7, #0x1
|
||||
bne 15b
|
||||
|
||||
imx7_qos_setting
|
||||
|
||||
/* enable port */
|
||||
ldr r7, =0x1
|
||||
str r7, [r3, #0x490]
|
||||
|
||||
/* jump to kernel resume */
|
||||
ldr r1, =0x30270000
|
||||
ldr r7, [r1]
|
||||
|
||||
mov pc, r7
|
||||
16:
|
||||
/* Configure ocram_epdc */
|
||||
ldr r0, =IOMUXC_GPR_BASE_ADDR
|
||||
ldr r1, =0x4f400005
|
||||
str r1, [r0, #0x4]
|
||||
|
||||
/* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */
|
||||
ldr r0, =ANATOP_BASE_ADDR
|
||||
ldr r1, =(0x1 << 30)
|
||||
str r1, [r0, #0x388]
|
||||
str r1, [r0, #0x384]
|
||||
|
||||
ldr r0, =SRC_BASE_ADDR
|
||||
ldr r1, =0x2
|
||||
ldr r2, =0x1000
|
||||
str r1, [r0, r2]
|
||||
|
||||
ldr r0, =DDRC_IPS_BASE_ADDR
|
||||
ldr r1, =0x03040008
|
||||
str r1, [r0]
|
||||
ldr r1, =0x00200038
|
||||
str r1, [r0, #0x64]
|
||||
ldr r1, =0x1
|
||||
str r1, [r0, #0x490]
|
||||
ldr r1, =0x00350001
|
||||
str r1, [r0, #0xd0]
|
||||
ldr r1, =0x00c3000a
|
||||
str r1, [r0, #0xdc]
|
||||
ldr r1, =0x00010000
|
||||
str r1, [r0, #0xe0]
|
||||
ldr r1, =0x00110006
|
||||
str r1, [r0, #0xe4]
|
||||
ldr r1, =0x33f
|
||||
str r1, [r0, #0xf4]
|
||||
ldr r1, =0x0a0e110b
|
||||
str r1, [r0, #0x100]
|
||||
ldr r1, =0x00020211
|
||||
str r1, [r0, #0x104]
|
||||
ldr r1, =0x03060708
|
||||
str r1, [r0, #0x108]
|
||||
ldr r1, =0x00a0500c
|
||||
str r1, [r0, #0x10c]
|
||||
ldr r1, =0x05020307
|
||||
str r1, [r0, #0x110]
|
||||
ldr r1, =0x02020404
|
||||
str r1, [r0, #0x114]
|
||||
ldr r1, =0x02020003
|
||||
str r1, [r0, #0x118]
|
||||
ldr r1, =0x00000202
|
||||
str r1, [r0, #0x11c]
|
||||
ldr r1, =0x00000202
|
||||
str r1, [r0, #0x120]
|
||||
ldr r1, =0x00600018
|
||||
str r1, [r0, #0x180]
|
||||
ldr r1, =0x00e00100
|
||||
str r1, [r0, #0x184]
|
||||
ldr r1, =0x02098205
|
||||
str r1, [r0, #0x190]
|
||||
ldr r1, =0x00060303
|
||||
str r1, [r0, #0x194]
|
||||
ldr r1, =0x80400003
|
||||
str r1, [r0, #0x1a0]
|
||||
ldr r1, =0x00100020
|
||||
str r1, [r0, #0x1a4]
|
||||
ldr r1, =0x80100004
|
||||
str r1, [r0, #0x1a8]
|
||||
|
||||
ldr r1, =0x00000016
|
||||
str r1, [r0, #0x200]
|
||||
ldr r1, =0x00090909
|
||||
str r1, [r0, #0x204]
|
||||
ldr r1, =0x00000f00
|
||||
str r1, [r0, #0x210]
|
||||
ldr r1, =0x08080808
|
||||
str r1, [r0, #0x214]
|
||||
ldr r1, =0x0f0f0808
|
||||
str r1, [r0, #0x218]
|
||||
|
||||
ldr r1, =0x06000600
|
||||
str r1, [r0, #0x240]
|
||||
mov r1, #0x0
|
||||
str r1, [r0, #0x244]
|
||||
|
||||
ldr r0, =SRC_BASE_ADDR
|
||||
mov r1, #0x0
|
||||
ldr r2, =0x1000
|
||||
str r1, [r0, r2]
|
||||
|
||||
ldr r0, =DDRPHY_IPS_BASE_ADDR
|
||||
ldr r1, =0x17421e40
|
||||
str r1, [r0]
|
||||
ldr r1, =0x10210100
|
||||
str r1, [r0, #0x4]
|
||||
ldr r1, =0x00010000
|
||||
str r1, [r0, #0x8]
|
||||
ldr r1, =0x0007080c
|
||||
str r1, [r0, #0x10]
|
||||
imx7d_ddrphy_latency_setting
|
||||
ldr r1, =0x1010007e
|
||||
str r1, [r0, #0xb0]
|
||||
ldr r1, =0x01010000
|
||||
str r1, [r0, #0x1c]
|
||||
|
||||
ldr r2, =ANATOP_BASE_ADDR
|
||||
ldr r3, [r2, #0x800]
|
||||
and r3, r3, #0xFF
|
||||
cmp r3, #0x11
|
||||
bne 17f
|
||||
|
||||
ldr r1, =0x0db60d6e
|
||||
str r1, [r0, #0x9c]
|
||||
b 18f
|
||||
17:
|
||||
ldr r1, =0x00000b24
|
||||
str r1, [r0, #0x9c]
|
||||
18:
|
||||
ldr r1, =0x06060606
|
||||
str r1, [r0, #0x30]
|
||||
ldr r1, =0x0a0a0a0a
|
||||
str r1, [r0, #0x20]
|
||||
ldr r1, =0x01000008
|
||||
str r1, [r0, #0x50]
|
||||
ldr r1, =0x00000008
|
||||
str r1, [r0, #0x50]
|
||||
|
||||
ldr r1, =0x0000000f
|
||||
str r1, [r0, #0x18]
|
||||
ldr r1, =0x0e487304
|
||||
str r1, [r0, #0xc0]
|
||||
ldr r1, =0x0e4c7304
|
||||
str r1, [r0, #0xc0]
|
||||
ldr r1, =0x0e4c7306
|
||||
str r1, [r0, #0xc0]
|
||||
|
||||
wait_zq:
|
||||
ldr r1, [r0, #0xc4]
|
||||
tst r1, #0x1
|
||||
beq wait_zq
|
||||
|
||||
ldr r1, =0x0e487304
|
||||
str r1, [r0, #0xc0]
|
||||
|
||||
ldr r0, =CCM_BASE_ADDR
|
||||
mov r1, #0x0
|
||||
ldr r2, =0x4130
|
||||
str r1, [r0, r2]
|
||||
ldr r0, =IOMUXC_GPR_BASE_ADDR
|
||||
mov r1, #0x178
|
||||
str r1, [r0, #0x20]
|
||||
ldr r0, =CCM_BASE_ADDR
|
||||
mov r1, #0x2
|
||||
ldr r2, =0x4130
|
||||
str r1, [r0, r2]
|
||||
|
||||
ldr r0, =DDRC_IPS_BASE_ADDR
|
||||
wait_stat:
|
||||
ldr r1, [r0, #0x4]
|
||||
tst r1, #0x1
|
||||
beq wait_stat
|
||||
.endm
|
||||
|
||||
.macro imx7_clock_gating
|
||||
#ifdef CONFIG_IMX_OPTEE
|
||||
ldr r0, =0x30340024
|
||||
ldr r1, =0x1
|
||||
str r1, [r0]
|
||||
#endif
|
||||
.endm
|
||||
|
||||
.macro imx7_qos_setting
|
||||
ldr r0, =REGS_QOS_BASE
|
||||
ldr r1, =0
|
||||
str r1, [r0, #0]
|
||||
|
||||
ldr r1, =0
|
||||
str r1, [r0, #0x60]
|
||||
|
||||
ldr r0, =REGS_QOS_EPDC
|
||||
ldr r1, =0
|
||||
str r1, [r0, #0]
|
||||
|
||||
ldr r0, =REGS_QOS_PXP0
|
||||
ldr r1, =0
|
||||
str r1, [r0, #0]
|
||||
|
||||
ldr r0, =REGS_QOS_PXP1
|
||||
ldr r1, =0
|
||||
str r1, [r0, #0]
|
||||
|
||||
ldr r0, =REGS_QOS_EPDC
|
||||
ldr r1, =0x0f020f22
|
||||
str r1, [r0, #0xd0]
|
||||
str r1, [r0, #0xe0]
|
||||
|
||||
ldr r0, =REGS_QOS_PXP0
|
||||
ldr r1, =0x1
|
||||
str r1, [r0, #0]
|
||||
ldr r0, =REGS_QOS_PXP1
|
||||
str r1, [r0, #0]
|
||||
|
||||
ldr r0, =REGS_QOS_PXP0
|
||||
ldr r1, =0x0f020222
|
||||
str r1, [r0, #0x50]
|
||||
ldr r0, =REGS_QOS_PXP1
|
||||
str r1, [r0, #0x50]
|
||||
|
||||
ldr r0, =REGS_QOS_PXP0
|
||||
ldr r1, =0x0f020222
|
||||
str r1, [r0, #0x60]
|
||||
ldr r0, =REGS_QOS_PXP1
|
||||
str r1, [r0, #0x60]
|
||||
|
||||
ldr r0, =REGS_QOS_PXP0
|
||||
ldr r1, =0x0f020422
|
||||
str r1, [r0, #0x70]
|
||||
ldr r0, =REGS_QOS_PXP1
|
||||
str r1, [r0, #0x70]
|
||||
|
||||
ldr r0, =IOMUXC_GPR_BASE_ADDR
|
||||
ldr r1, =0xe080
|
||||
str r1, [r0, #0x34]
|
||||
.endm
|
||||
|
||||
.macro imx7_ddr_setting
|
||||
imx7d_12x12_lpddr3_arm2_setting
|
||||
.endm
|
||||
|
||||
/* include the common plugin code here */
|
||||
#include <asm/arch/mx7_plugin.S>
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* Configuration settings for the Freescale i.MX7D 12x12 DDR3 ARM2 board.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __MX7D_12X12_DDR3_ARM2_CONFIG_H
|
||||
#define __MX7D_12X12_DDR3_ARM2_CONFIG_H
|
||||
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 2
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC3 */
|
||||
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
|
||||
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC3 */
|
||||
|
||||
#define PHYS_SDRAM_SIZE SZ_1G
|
||||
|
||||
#ifdef CONFIG_SPI_BOOT
|
||||
#define CONFIG_MXC_SPI
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MXC_SPI
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH_ATMEL
|
||||
#define CONFIG_SF_DEFAULT_BUS 3
|
||||
#define CONFIG_SF_DEFAULT_SPEED 20000000
|
||||
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
|
||||
#define CONFIG_SF_DEFAULT_CS 0
|
||||
#endif
|
||||
|
||||
#include "mx7d_arm2.h"
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Configuration settings for the Freescale i.MX7D 12x12 LPDDR3 ARM2 board.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __MX7D_12X12_LPDDR3_ARM2_CONFIG_H
|
||||
#define __MX7D_12X12_LPDDR3_ARM2_CONFIG_H
|
||||
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 3
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
|
||||
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
|
||||
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
|
||||
|
||||
#define PHYS_SDRAM_SIZE SZ_2G
|
||||
|
||||
#define CONFIG_FEC_MXC
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_FEC_XCV_TYPE RGMII
|
||||
#ifdef CONFIG_DM_ETH
|
||||
#define CONFIG_ETHPRIME "eth0"
|
||||
#else
|
||||
#define CONFIG_ETHPRIME "FEC"
|
||||
#endif
|
||||
#define CONFIG_FEC_MXC_PHYADDR 1
|
||||
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_ATHEROS
|
||||
|
||||
/* ENET1 */
|
||||
#define IMX_FEC_BASE ENET_IPS_BASE_ADDR
|
||||
|
||||
#ifdef CONFIG_QSPI_BOOT
|
||||
#define CONFIG_FSL_QSPI
|
||||
#elif defined CONFIG_SPI_BOOT
|
||||
#define CONFIG_MXC_SPI
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MXC_SPI
|
||||
#define CONFIG_SF_DEFAULT_BUS 0
|
||||
#define CONFIG_SF_DEFAULT_SPEED 20000000
|
||||
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
|
||||
#define CONFIG_SF_DEFAULT_CS 0
|
||||
#endif
|
||||
|
||||
/* #define CONFIG_SPLASH_SCREEN*/
|
||||
/* #define CONFIG_MXC_EPDC*/
|
||||
|
||||
#include "mx7d_arm2.h"
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,319 @@
|
|||
/*
|
||||
* Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Configuration settings for the Freescale i.MX7D ARM2 board.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __MX7D_ARM2_CONFIG_H
|
||||
#define __MX7D_ARM2_CONFIG_H
|
||||
|
||||
#include "mx7_common.h"
|
||||
|
||||
#define CONFIG_DBG_MONITOR
|
||||
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_INITRD_TAG
|
||||
#define CONFIG_REVISION_TAG
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
|
||||
|
||||
|
||||
#define CONFIG_MXC_UART
|
||||
#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
|
||||
|
||||
#define CONFIG_IMX_THERMAL
|
||||
|
||||
/* MMC Configs */
|
||||
#define CONFIG_FSL_ESDHC
|
||||
#define CONFIG_FSL_USDHC
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
|
||||
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#undef CONFIG_BOOTM_NETBSD
|
||||
#undef CONFIG_BOOTM_PLAN9
|
||||
#undef CONFIG_BOOTM_RTEMS
|
||||
|
||||
#undef CONFIG_CMD_EXPORTENV
|
||||
#undef CONFIG_CMD_IMPORTENV
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
|
||||
/* I2C configs */
|
||||
#define CONFIG_SYS_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
|
||||
#undef CONFIG_CMD_IMLS
|
||||
|
||||
#define CONFIG_LOADADDR 0x80800000
|
||||
#define CONFIG_SYS_TEXT_BASE 0x87800000
|
||||
|
||||
#ifdef CONFIG_DM_SPI
|
||||
#define CONFIG_SYS_AUXCORE_BOOTDATA 0x68000000 /* Set to QSPI1 B flash at default */
|
||||
#define SF_QSPI1_B_CS_NUM 2
|
||||
#define SF_QSPI1_B_BUS_NUM 1
|
||||
#else
|
||||
#define CONFIG_SYS_AUXCORE_BOOTDATA 0x62000000 /* Set to QSPI1 B flash at default */
|
||||
#define SF_QSPI1_B_CS_NUM 1
|
||||
#define SF_QSPI1_B_BUS_NUM 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IMX_BOOTAUX
|
||||
|
||||
#define UPDATE_M4_ENV \
|
||||
"m4image=m4_qspi.bin\0" \
|
||||
"m4_qspi_cs="__stringify(SF_QSPI1_B_CS_NUM)"\0" \
|
||||
"m4_qspi_bus="__stringify(SF_QSPI1_B_BUS_NUM)"\0" \
|
||||
"loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \
|
||||
"update_m4_from_sd=" \
|
||||
"if sf probe ${m4_qspi_bus}:${m4_qspi_cs}; then " \
|
||||
"if run loadm4image; then " \
|
||||
"setexpr fw_sz ${filesize} + 0xffff; " \
|
||||
"setexpr fw_sz ${fw_sz} / 0x10000; " \
|
||||
"setexpr fw_sz ${fw_sz} * 0x10000; " \
|
||||
"sf erase 0x0 ${fw_sz}; " \
|
||||
"sf write ${loadaddr} 0x0 ${filesize}; " \
|
||||
"fi; " \
|
||||
"fi\0" \
|
||||
"m4boot=sf probe ${m4_qspi_bus}:${m4_qspi_cs}; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0"
|
||||
#else
|
||||
#define UPDATE_M4_ENV ""
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
|
||||
|
||||
#define CONFIG_MFG_ENV_SETTINGS \
|
||||
"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
|
||||
"rdinit=/linuxrc " \
|
||||
"g_mass_storage.stall=0 g_mass_storage.removable=1 " \
|
||||
"g_mass_storage.file=/fat g_mass_storage.ro=1 " \
|
||||
"g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
|
||||
"g_mass_storage.iSerialNumber=\"\" "\
|
||||
"mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs) " \
|
||||
"clk_ignore_unused "\
|
||||
"\0" \
|
||||
"initrd_addr=0x83800000\0" \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
"bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
|
||||
|
||||
#if defined(CONFIG_NAND_BOOT)
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
CONFIG_MFG_ENV_SETTINGS \
|
||||
"panel=MCIMX28LCD\0" \
|
||||
"fdt_addr=0x83000000\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"console=ttymxc0\0" \
|
||||
"bootargs=console=ttymxc0,115200 ubi.mtd=5 " \
|
||||
"root=ubi0:rootfs rootfstype=ubifs " \
|
||||
"mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs)\0"\
|
||||
"bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\
|
||||
"nand read ${fdt_addr} 0x5000000 0x100000;"\
|
||||
"bootz ${loadaddr} - ${fdt_addr}\0"
|
||||
|
||||
#else
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
CONFIG_MFG_ENV_SETTINGS \
|
||||
UPDATE_M4_ENV \
|
||||
"epdc_waveform=epdc_splash.bin\0" \
|
||||
"panel=MCIMX28LCD\0" \
|
||||
"script=boot.scr\0" \
|
||||
"image=zImage\0" \
|
||||
"console=ttymxc0\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
|
||||
"fdt_addr=0x83000000\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"ip_dyn=yes\0" \
|
||||
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
|
||||
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
|
||||
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
|
||||
"mmcautodetect=yes\0" \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=${mmcroot}\0" \
|
||||
"loadbootscript=" \
|
||||
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootz; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootz; " \
|
||||
"fi;\0" \
|
||||
"netargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||
"netboot=echo Booting from net ...; " \
|
||||
"run netargs; " \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"${get_cmd} ${image}; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootz; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootz; " \
|
||||
"fi;\0"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"mmc dev ${mmcdev};" \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loadimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else run netboot; fi"
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x40000000)
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
/* Physical Memory Map */
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
#define CONFIG_ENV_SIZE SZ_8K
|
||||
|
||||
#ifdef CONFIG_FSL_QSPI
|
||||
#define CONFIG_SYS_FSL_QSPI_AHB
|
||||
#define CONFIG_SF_DEFAULT_CS 0
|
||||
#define CONFIG_SF_DEFAULT_SPEED 40000000
|
||||
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
|
||||
#ifdef CONFIG_DM_SPI
|
||||
#define FSL_QSPI_FLASH_NUM 4
|
||||
#define CONFIG_SF_DEFAULT_BUS 1 /* Have set the QSPI to SPI 1 in imx7d.dtsi alias*/
|
||||
#else
|
||||
#define FSL_QSPI_FLASH_NUM 2 /* Non-DM driver only supports 2 flash, one is on A port, another is on B port*/
|
||||
#define CONFIG_SF_DEFAULT_BUS 0
|
||||
#endif
|
||||
#define FSL_QSPI_FLASH_SIZE SZ_64M
|
||||
#define QSPI0_BASE_ADDR QSPI1_IPS_BASE_ADDR
|
||||
#define QSPI0_AMBA_BASE QSPI0_ARB_BASE_ADDR
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MTD_NOR_FLASH
|
||||
#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
|
||||
#define CONFIG_SYS_FLASH_SECT_SIZE (256 * 1024)
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
|
||||
#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
|
||||
#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
#define CONFIG_SYS_FLASH_PROTECTION
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_NAND_MXS
|
||||
#define CONFIG_CMD_NAND
|
||||
#define CONFIG_CMD_NAND_TRIMFFS
|
||||
|
||||
/* NAND stuff */
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BASE 0x40000000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
|
||||
/* DMA stuff, needed for GPMI/MXS NAND support */
|
||||
#define CONFIG_APBH_DMA
|
||||
#define CONFIG_APBH_DMA_BURST
|
||||
#define CONFIG_APBH_DMA_BURST8
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ENV_IS_IN_MMC)
|
||||
#define CONFIG_ENV_OFFSET (14 * SZ_64K)
|
||||
#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
|
||||
#define CONFIG_ENV_OFFSET (896 * 1024)
|
||||
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
|
||||
#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
|
||||
#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
|
||||
#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
|
||||
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
|
||||
#elif defined(CONFIG_ENV_IS_IN_FLASH)
|
||||
#undef CONFIG_ENV_SIZE
|
||||
#define CONFIG_ENV_SIZE CONFIG_SYS_FLASH_SECT_SIZE
|
||||
#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SIZE
|
||||
#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_FLASH_SECT_SIZE)
|
||||
#elif defined(CONFIG_ENV_IS_IN_NAND)
|
||||
#undef CONFIG_ENV_SIZE
|
||||
#define CONFIG_ENV_OFFSET (60 << 20)
|
||||
#define CONFIG_ENV_SECT_SIZE (128 << 10)
|
||||
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_VIDEO
|
||||
#define CONFIG_VIDEO_MXS
|
||||
#define CONFIG_VIDEO_LOGO
|
||||
#define CONFIG_SPLASH_SCREEN
|
||||
#define CONFIG_SPLASH_SCREEN_ALIGN
|
||||
#define CONFIG_CMD_BMP
|
||||
#define CONFIG_BMP_16BPP
|
||||
#define CONFIG_VIDEO_BMP_RLE8
|
||||
#define CONFIG_VIDEO_BMP_LOGO
|
||||
#define CONFIG_IMX_VIDEO_SKIP
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MXC_EPDC)
|
||||
/*
|
||||
* Framebuffer and LCD
|
||||
*/
|
||||
#define CONFIG_CMD_BMP
|
||||
#define CONFIG_SPLASH_SCREEN
|
||||
|
||||
#undef LCD_TEST_PATTERN
|
||||
/* #define CONFIG_SPLASH_IS_IN_MMC 1 */
|
||||
#define LCD_BPP LCD_MONOCHROME
|
||||
/* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */
|
||||
|
||||
#define CONFIG_WAVEFORM_BUF_SIZE 0x400000
|
||||
#endif
|
||||
|
||||
/* USB Configs */
|
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue