Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
commit
6579d15c58
|
@ -1037,6 +1037,14 @@ Pali Rohár <pali.rohar@gmail.com>
|
|||
|
||||
nokia_rx51 ARM ARMV7 (OMAP34xx SoC)
|
||||
|
||||
Eric Nelson <eric.nelson@boundarydevices.com>
|
||||
nitrogen6dl i.MX6DL 1GB
|
||||
nitrogen6dl2g i.MX6DL 2GB
|
||||
nitrogen6q i.MX6Q/6D 1GB
|
||||
nitrogen6q2g i.MX6Q/6D 2GB
|
||||
nitrogen6s i.MX6S 512MB
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||||
nitrogen6s1g i.MX6S 1GB
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||||
|
||||
-------------------------------------------------------------------------
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||||
|
||||
Unknown / orphaned boards:
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||||
|
|
4
Makefile
4
Makefile
|
@ -464,8 +464,8 @@ $(obj)u-boot.img: $(obj)u-boot.bin
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|||
sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \
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||||
-d $< $@
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||||
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||||
$(OBJTREE)/u-boot.imx : $(obj)u-boot.bin $(SUBDIR_TOOLS) depend
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||||
$(MAKE) -C $(SRCTREE)/arch/arm/imx-common $@
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||||
$(obj)u-boot.imx: $(obj)u-boot.bin depend
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||||
$(MAKE) -C $(SRCTREE)/arch/arm/imx-common $(OBJTREE)/u-boot.imx
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||||
|
||||
$(obj)u-boot.kwb: $(obj)u-boot.bin
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$(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \
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|
|
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@ -34,6 +34,6 @@ PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
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|||
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ifneq ($(CONFIG_IMX_CONFIG),)
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ALL-y += $(OBJTREE)/u-boot.imx
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ALL-y += $(obj)u-boot.imx
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endif
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|
|
|
@ -289,7 +289,8 @@ static uint32_t mxs_get_sspclk(enum mxs_sspclock ssp)
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void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq)
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{
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struct mxs_ssp_regs *ssp_regs;
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const uint32_t sspclk = mxs_get_sspclk(bus);
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const enum mxs_sspclock clk = mxs_ssp_clock_by_bus(bus);
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const uint32_t sspclk = mxs_get_sspclk(clk);
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uint32_t reg;
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uint32_t divide, rate, tgtclk;
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|
|
|
@ -30,7 +30,7 @@ void early_delay(int delay);
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|||
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void mxs_power_init(void);
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#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT
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#ifdef CONFIG_SPL_MXS_PSWITCH_WAIT
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void mxs_power_wait_pswitch(void);
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||||
#else
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||||
static inline void mxs_power_wait_pswitch(void) { }
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|
|
|
@ -27,6 +27,7 @@
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|||
#include <config.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#include <linux/compiler.h>
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#include "mxs_init.h"
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@ -119,6 +120,10 @@ static void initialize_dram_values(void)
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writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
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#ifdef CONFIG_MX23
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/*
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* Enable tRAS lockout in HW_DRAM_CTL08 ; it must be the last
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||||
* element to be set
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||||
*/
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writel((1 << 24), MXS_DRAM_BASE + (4 * 8));
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#endif
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}
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|
@ -229,7 +234,7 @@ static void mx23_mem_setup_vddmem(void)
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|||
struct mxs_power_regs *power_regs =
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(struct mxs_power_regs *)MXS_POWER_BASE;
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|
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writel((0x12 << POWER_VDDMEMCTRL_TRG_OFFSET) |
|
||||
writel((0x10 << POWER_VDDMEMCTRL_TRG_OFFSET) |
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||||
POWER_VDDMEMCTRL_ENABLE_ILIMIT |
|
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POWER_VDDMEMCTRL_ENABLE_LINREG |
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POWER_VDDMEMCTRL_PULLDOWN_ACTIVE,
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|
@ -237,13 +242,20 @@ static void mx23_mem_setup_vddmem(void)
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|
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early_delay(10000);
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writel((0x12 << POWER_VDDMEMCTRL_TRG_OFFSET) |
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writel((0x10 << POWER_VDDMEMCTRL_TRG_OFFSET) |
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POWER_VDDMEMCTRL_ENABLE_LINREG,
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&power_regs->hw_power_vddmemctrl);
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||||
}
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static void mx23_mem_init(void)
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{
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/*
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* Reset/ungate the EMI block. This is essential, otherwise the system
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||||
* suffers from memory instability. This thing is mx23 specific and is
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||||
* no longer present on mx28.
|
||||
*/
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||||
mxs_reset_block((struct mxs_register_32 *)MXS_EMI_BASE);
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mx23_mem_setup_vddmem();
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/*
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|
|
|
@ -921,7 +921,7 @@ void mxs_power_init(void)
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|||
early_delay(1000);
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||||
}
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||||
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||||
#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT
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||||
#ifdef CONFIG_SPL_MXS_PSWITCH_WAIT
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||||
void mxs_power_wait_pswitch(void)
|
||||
{
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||||
struct mxs_power_regs *power_regs =
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||||
|
|
|
@ -32,7 +32,11 @@
|
|||
#include <asm/arch/sys_proto.h>
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||||
|
||||
/* Maximum fixed count */
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||||
#define TIMER_LOAD_VAL 0xffffffff
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||||
#if defined(CONFIG_MX23)
|
||||
#define TIMER_LOAD_VAL 0xffff
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||||
#elif defined(CONFIG_MX28)
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||||
#define TIMER_LOAD_VAL 0xffffffff
|
||||
#endif
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||||
|
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DECLARE_GLOBAL_DATA_PTR;
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||||
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||||
|
@ -42,22 +46,22 @@ DECLARE_GLOBAL_DATA_PTR;
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|||
/*
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||||
* This driver uses 1kHz clock source.
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*/
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||||
#define MX28_INCREMENTER_HZ 1000
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#define MXS_INCREMENTER_HZ 1000
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||||
static inline unsigned long tick_to_time(unsigned long tick)
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{
|
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return tick / (MX28_INCREMENTER_HZ / CONFIG_SYS_HZ);
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||||
return tick / (MXS_INCREMENTER_HZ / CONFIG_SYS_HZ);
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}
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||||
|
||||
static inline unsigned long time_to_tick(unsigned long time)
|
||||
{
|
||||
return time * (MX28_INCREMENTER_HZ / CONFIG_SYS_HZ);
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||||
return time * (MXS_INCREMENTER_HZ / CONFIG_SYS_HZ);
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}
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||||
|
||||
/* Calculate how many ticks happen in "us" microseconds */
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static inline unsigned long us_to_tick(unsigned long us)
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||||
{
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||||
return (us * MX28_INCREMENTER_HZ) / 1000000;
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||||
return (us * MXS_INCREMENTER_HZ) / 1000000;
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||||
}
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||||
int timer_init(void)
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||||
|
@ -69,7 +73,11 @@ int timer_init(void)
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|||
mxs_reset_block(&timrot_regs->hw_timrot_rotctrl_reg);
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||||
|
||||
/* Set fixed_count to 0 */
|
||||
#if defined(CONFIG_MX23)
|
||||
writel(0, &timrot_regs->hw_timrot_timcount0);
|
||||
#elif defined(CONFIG_MX28)
|
||||
writel(0, &timrot_regs->hw_timrot_fixed_count0);
|
||||
#endif
|
||||
|
||||
/* Set UPDATE bit and 1Khz frequency */
|
||||
writel(TIMROT_TIMCTRLn_UPDATE | TIMROT_TIMCTRLn_RELOAD |
|
||||
|
@ -77,7 +85,11 @@ int timer_init(void)
|
|||
&timrot_regs->hw_timrot_timctrl0);
|
||||
|
||||
/* Set fixed_count to maximal value */
|
||||
#if defined(CONFIG_MX23)
|
||||
writel(TIMER_LOAD_VAL - 1, &timrot_regs->hw_timrot_timcount0);
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||||
#elif defined(CONFIG_MX28)
|
||||
writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0);
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||||
#endif
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||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -86,9 +98,16 @@ unsigned long long get_ticks(void)
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|||
{
|
||||
struct mxs_timrot_regs *timrot_regs =
|
||||
(struct mxs_timrot_regs *)MXS_TIMROT_BASE;
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||||
uint32_t now;
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||||
|
||||
/* Current tick value */
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uint32_t now = readl(&timrot_regs->hw_timrot_running_count0);
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||||
#if defined(CONFIG_MX23)
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||||
/* Upper bits are the valid ones. */
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now = readl(&timrot_regs->hw_timrot_timcount0) >>
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||||
TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET;
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#elif defined(CONFIG_MX28)
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now = readl(&timrot_regs->hw_timrot_running_count0);
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#endif
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if (lastdec >= now) {
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/*
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|
@ -117,17 +136,17 @@ ulong get_timer(ulong base)
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}
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/* We use the HW_DIGCTL_MICROSECONDS register for sub-millisecond timer. */
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#define MX28_HW_DIGCTL_MICROSECONDS 0x8001c0c0
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#define MXS_HW_DIGCTL_MICROSECONDS 0x8001c0c0
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void __udelay(unsigned long usec)
|
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{
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uint32_t old, new, incr;
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uint32_t counter = 0;
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|
||||
old = readl(MX28_HW_DIGCTL_MICROSECONDS);
|
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old = readl(MXS_HW_DIGCTL_MICROSECONDS);
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while (counter < usec) {
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new = readl(MX28_HW_DIGCTL_MICROSECONDS);
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new = readl(MXS_HW_DIGCTL_MICROSECONDS);
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/* Check if the timer wrapped. */
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if (new < old) {
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|
@ -152,5 +171,5 @@ void __udelay(unsigned long usec)
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|
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ulong get_tbclk(void)
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{
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return MX28_INCREMENTER_HZ;
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return MXS_INCREMENTER_HZ;
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}
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||||
|
|
|
@ -32,7 +32,7 @@ COBJS += cache_v7.o
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|||
COBJS += cpu.o
|
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COBJS += syslib.o
|
||||
|
||||
ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA),)
|
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ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6),)
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||||
SOBJS += lowlevel_init.o
|
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endif
|
||||
|
||||
|
|
|
@ -40,5 +40,5 @@ PF_NO_UNALIGNED := $(call cc-option, -mno-unaligned-access,)
|
|||
PLATFORM_NO_UNALIGNED := $(PF_NO_UNALIGNED)
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|
||||
ifneq ($(CONFIG_IMX_CONFIG),)
|
||||
ALL-y += $(OBJTREE)/u-boot.imx
|
||||
ALL-y += $(obj)u-boot.imx
|
||||
endif
|
||||
|
|
|
@ -28,7 +28,6 @@ include $(TOPDIR)/config.mk
|
|||
LIB = $(obj)lib$(SOC).o
|
||||
|
||||
COBJS = soc.o clock.o
|
||||
SOBJS = lowlevel_init.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
||||
|
|
|
@ -1,35 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
.section ".text.init", "x"
|
||||
|
||||
#include <linux/linkage.h>
|
||||
|
||||
.macro init_arm_errata
|
||||
/* ARM erratum ID #743622 */
|
||||
mrc p15, 0, r10, c15, c0, 1 /* read diagnostic register */
|
||||
orr r10, r10, #1 << 6 /* set bit #6 */
|
||||
/* ARM erratum ID #751472 */
|
||||
orr r10, r10, #1 << 11 /* set bit #11 */
|
||||
mcr p15, 0, r10, c15, c0, 1 /* write diagnostic register */
|
||||
.endm
|
||||
|
||||
ENTRY(lowlevel_init)
|
||||
init_arm_errata
|
||||
mov pc, lr
|
||||
ENDPROC(lowlevel_init)
|
|
@ -30,6 +30,7 @@
|
|||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/imx-common/boot_mode.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
struct scu_regs {
|
||||
u32 ctrl;
|
||||
|
@ -121,12 +122,23 @@ void set_vddsoc(u32 mv)
|
|||
writel(reg, &anatop->reg_core);
|
||||
}
|
||||
|
||||
static void imx_set_wdog_powerdown(bool enable)
|
||||
{
|
||||
struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
|
||||
struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
|
||||
|
||||
/* Write to the PDE (Power Down Enable) bit */
|
||||
writew(enable, &wdog1->wmcr);
|
||||
writew(enable, &wdog2->wmcr);
|
||||
}
|
||||
|
||||
int arch_cpu_init(void)
|
||||
{
|
||||
init_aips();
|
||||
|
||||
set_vddsoc(1200); /* Set VDDSOC to 1.2V */
|
||||
|
||||
imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -193,3 +205,7 @@ const struct boot_mode soc_boot_modes[] = {
|
|||
{"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
|
||||
{NULL, 0},
|
||||
};
|
||||
|
||||
void s_init(void)
|
||||
{
|
||||
}
|
||||
|
|
|
@ -20,6 +20,17 @@
|
|||
#ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
|
||||
#define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
|
||||
|
||||
#define CCM_CCGR0 0x020C4068
|
||||
#define CCM_CCGR1 0x020C406c
|
||||
#define CCM_CCGR2 0x020C4070
|
||||
#define CCM_CCGR3 0x020C4074
|
||||
#define CCM_CCGR4 0x020C4078
|
||||
#define CCM_CCGR5 0x020C407c
|
||||
#define CCM_CCGR6 0x020C4080
|
||||
|
||||
#define PMU_MISC2 0x020C8170
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct mxc_ccm_reg {
|
||||
u32 ccr; /* 0x0000 */
|
||||
u32 ccdr;
|
||||
|
@ -105,6 +116,7 @@ struct mxc_ccm_reg {
|
|||
u32 analog_pfd_528_clr;
|
||||
u32 analog_pfd_528_tog;
|
||||
};
|
||||
#endif
|
||||
|
||||
/* Define the bits in register CCR */
|
||||
#define MXC_CCM_CCR_RBC_EN (1 << 27)
|
||||
|
|
|
@ -601,5 +601,13 @@ struct iomuxc_base_regs {
|
|||
u32 daisy[104]; /* 0x7b0..94c */
|
||||
};
|
||||
|
||||
struct wdog_regs {
|
||||
u16 wcr; /* Control */
|
||||
u16 wsr; /* Service */
|
||||
u16 wrsr; /* Reset Status */
|
||||
u16 wicr; /* Interrupt Control */
|
||||
u16 wmcr; /* Miscellaneous Control */
|
||||
};
|
||||
|
||||
#endif /* __ASSEMBLER__*/
|
||||
#endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */
|
||||
|
|
|
@ -16,6 +16,11 @@
|
|||
|
||||
#ifndef __ASM_ARCH_IOMUX_H__
|
||||
#define __ASM_ARCH_IOMUX_H__
|
||||
|
||||
#define MX6_IOMUXC_GPR4 0x020e0010
|
||||
#define MX6_IOMUXC_GPR6 0x020e0018
|
||||
#define MX6_IOMUXC_GPR7 0x020e001c
|
||||
|
||||
/*
|
||||
* IOMUXC_GPR13 bit fields
|
||||
*/
|
||||
|
|
|
@ -0,0 +1,85 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Boundary Devices Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
#ifndef __ASM_ARCH_MX6_DDR_H__
|
||||
#define __ASM_ARCH_MX6_DDR_H__
|
||||
|
||||
#ifdef CONFIG_MX6Q
|
||||
#include "mx6q-ddr.h"
|
||||
#else
|
||||
#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
|
||||
#include "mx6dl-ddr.h"
|
||||
#else
|
||||
#error "Please select cpu"
|
||||
#endif /* CONFIG_MX6DL or CONFIG_MX6S */
|
||||
#endif /* CONFIG_MX6Q */
|
||||
|
||||
#define MX6_MMDC_P0_MDCTL 0x021b0000
|
||||
#define MX6_MMDC_P0_MDPDC 0x021b0004
|
||||
#define MX6_MMDC_P0_MDOTC 0x021b0008
|
||||
#define MX6_MMDC_P0_MDCFG0 0x021b000c
|
||||
#define MX6_MMDC_P0_MDCFG1 0x021b0010
|
||||
#define MX6_MMDC_P0_MDCFG2 0x021b0014
|
||||
#define MX6_MMDC_P0_MDMISC 0x021b0018
|
||||
#define MX6_MMDC_P0_MDSCR 0x021b001c
|
||||
#define MX6_MMDC_P0_MDREF 0x021b0020
|
||||
#define MX6_MMDC_P0_MDRWD 0x021b002c
|
||||
#define MX6_MMDC_P0_MDOR 0x021b0030
|
||||
#define MX6_MMDC_P0_MDASP 0x021b0040
|
||||
#define MX6_MMDC_P0_MAPSR 0x021b0404
|
||||
#define MX6_MMDC_P0_MPZQHWCTRL 0x021b0800
|
||||
#define MX6_MMDC_P0_MPWLDECTRL0 0x021b080c
|
||||
#define MX6_MMDC_P0_MPWLDECTRL1 0x021b0810
|
||||
#define MX6_MMDC_P0_MPODTCTRL 0x021b0818
|
||||
#define MX6_MMDC_P0_MPRDDQBY0DL 0x021b081c
|
||||
#define MX6_MMDC_P0_MPRDDQBY1DL 0x021b0820
|
||||
#define MX6_MMDC_P0_MPRDDQBY2DL 0x021b0824
|
||||
#define MX6_MMDC_P0_MPRDDQBY3DL 0x021b0828
|
||||
#define MX6_MMDC_P0_MPDGCTRL0 0x021b083c
|
||||
#define MX6_MMDC_P0_MPDGCTRL1 0x021b0840
|
||||
#define MX6_MMDC_P0_MPRDDLCTL 0x021b0848
|
||||
#define MX6_MMDC_P0_MPWRDLCTL 0x021b0850
|
||||
#define MX6_MMDC_P0_MPMUR0 0x021b08b8
|
||||
|
||||
#define MX6_MMDC_P1_MDCTL 0x021b4000
|
||||
#define MX6_MMDC_P1_MDPDC 0x021b4004
|
||||
#define MX6_MMDC_P1_MDOTC 0x021b4008
|
||||
#define MX6_MMDC_P1_MDCFG0 0x021b400c
|
||||
#define MX6_MMDC_P1_MDCFG1 0x021b4010
|
||||
#define MX6_MMDC_P1_MDCFG2 0x021b4014
|
||||
#define MX6_MMDC_P1_MDMISC 0x021b4018
|
||||
#define MX6_MMDC_P1_MDSCR 0x021b401c
|
||||
#define MX6_MMDC_P1_MDREF 0x021b4020
|
||||
#define MX6_MMDC_P1_MDRWD 0x021b402c
|
||||
#define MX6_MMDC_P1_MDOR 0x021b4030
|
||||
#define MX6_MMDC_P1_MDASP 0x021b4040
|
||||
#define MX6_MMDC_P1_MAPSR 0x021b4404
|
||||
#define MX6_MMDC_P1_MPZQHWCTRL 0x021b4800
|
||||
#define MX6_MMDC_P1_MPWLDECTRL0 0x021b480c
|
||||
#define MX6_MMDC_P1_MPWLDECTRL1 0x021b4810
|
||||
#define MX6_MMDC_P1_MPODTCTRL 0x021b4818
|
||||
#define MX6_MMDC_P1_MPRDDQBY0DL 0x021b481c
|
||||
#define MX6_MMDC_P1_MPRDDQBY1DL 0x021b4820
|
||||
#define MX6_MMDC_P1_MPRDDQBY2DL 0x021b4824
|
||||
#define MX6_MMDC_P1_MPRDDQBY3DL 0x021b4828
|
||||
#define MX6_MMDC_P1_MPDGCTRL0 0x021b483c
|
||||
#define MX6_MMDC_P1_MPDGCTRL1 0x021b4840
|
||||
#define MX6_MMDC_P1_MPRDDLCTL 0x021b4848
|
||||
#define MX6_MMDC_P1_MPWRDLCTL 0x021b4850
|
||||
#define MX6_MMDC_P1_MPMUR0 0x021b48b8
|
||||
|
||||
#endif /*__ASM_ARCH_MX6_DDR_H__ */
|
|
@ -0,0 +1,31 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Boundary Devices Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
#ifndef __ASM_ARCH_MX6_PINS_H__
|
||||
#define __ASM_ARCH_MX6_PINS_H__
|
||||
|
||||
#ifdef CONFIG_MX6Q
|
||||
#include "mx6q_pins.h"
|
||||
#else
|
||||
#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
|
||||
#include "mx6dl_pins.h"
|
||||
#else
|
||||
#error "Please select cpu"
|
||||
#endif /* CONFIG_MX6DL or CONFIG_MX6S */
|
||||
#endif /* CONFIG_MX6Q */
|
||||
|
||||
#endif /*__ASM_ARCH_MX6_PINS_H__ */
|
|
@ -0,0 +1,71 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Boundary Devices Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
#ifndef __ASM_ARCH_MX6DLS_DDR_H__
|
||||
#define __ASM_ARCH_MX6DLS_DDR_H__
|
||||
|
||||
#ifndef CONFIG_MX6DL
|
||||
#ifndef CONFIG_MX6S
|
||||
#error "wrong CPU"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define MX6_IOM_DRAM_DQM0 0x020e0470
|
||||
#define MX6_IOM_DRAM_DQM1 0x020e0474
|
||||
#define MX6_IOM_DRAM_DQM2 0x020e0478
|
||||
#define MX6_IOM_DRAM_DQM3 0x020e047c
|
||||
#define MX6_IOM_DRAM_DQM4 0x020e0480
|
||||
#define MX6_IOM_DRAM_DQM5 0x020e0484
|
||||
#define MX6_IOM_DRAM_DQM6 0x020e0488
|
||||
#define MX6_IOM_DRAM_DQM7 0x020e048c
|
||||
|
||||
#define MX6_IOM_DRAM_CAS 0x020e0464
|
||||
#define MX6_IOM_DRAM_RAS 0x020e0490
|
||||
#define MX6_IOM_DRAM_RESET 0x020e0494
|
||||
#define MX6_IOM_DRAM_SDCLK_0 0x020e04ac
|
||||
#define MX6_IOM_DRAM_SDCLK_1 0x020e04b0
|
||||
#define MX6_IOM_DRAM_SDBA2 0x020e04a0
|
||||
#define MX6_IOM_DRAM_SDCKE0 0x020e04a4
|
||||
#define MX6_IOM_DRAM_SDCKE1 0x020e04a8
|
||||
#define MX6_IOM_DRAM_SDODT0 0x020e04b4
|
||||
#define MX6_IOM_DRAM_SDODT1 0x020e04b8
|
||||
|
||||
#define MX6_IOM_DRAM_SDQS0 0x020e04bc
|
||||
#define MX6_IOM_DRAM_SDQS1 0x020e04c0
|
||||
#define MX6_IOM_DRAM_SDQS2 0x020e04c4
|
||||
#define MX6_IOM_DRAM_SDQS3 0x020e04c8
|
||||
#define MX6_IOM_DRAM_SDQS4 0x020e04cc
|
||||
#define MX6_IOM_DRAM_SDQS5 0x020e04d0
|
||||
#define MX6_IOM_DRAM_SDQS6 0x020e04d4
|
||||
#define MX6_IOM_DRAM_SDQS7 0x020e04d8
|
||||
|
||||
#define MX6_IOM_GRP_B0DS 0x020e0764
|
||||
#define MX6_IOM_GRP_B1DS 0x020e0770
|
||||
#define MX6_IOM_GRP_B2DS 0x020e0778
|
||||
#define MX6_IOM_GRP_B3DS 0x020e077c
|
||||
#define MX6_IOM_GRP_B4DS 0x020e0780
|
||||
#define MX6_IOM_GRP_B5DS 0x020e0784
|
||||
#define MX6_IOM_GRP_B6DS 0x020e078c
|
||||
#define MX6_IOM_GRP_B7DS 0x020e0748
|
||||
#define MX6_IOM_GRP_ADDDS 0x020e074c
|
||||
#define MX6_IOM_DDRMODE_CTL 0x020e0750
|
||||
#define MX6_IOM_GRP_DDRPKE 0x020e0754
|
||||
#define MX6_IOM_GRP_DDRMODE 0x020e0760
|
||||
#define MX6_IOM_GRP_CTLDS 0x020e076c
|
||||
#define MX6_IOM_GRP_DDR_TYPE 0x020e0774
|
||||
|
||||
#endif /*__ASM_ARCH_MX6S_DDR_H__ */
|
|
@ -50,100 +50,103 @@
|
|||
#define NO_MUX_I 0
|
||||
#define NO_PAD_I 0
|
||||
enum {
|
||||
MX6DL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6DL_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6DL_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6DL_PAD_DI0_PIN3__IPU1_DI0_PIN3 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6DL_PAD_DI0_PIN4__GPIO_4_20 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6DL_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6DL_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6DL_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6DL_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6DL_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6DL_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6DL_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6DL_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6DL_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6DL_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6DL_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6DL_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6DL_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6DL_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6DL_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6DL_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6DL_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6DL_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6DL_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6DL_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6DL_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6DL_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6DL_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6DL_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6DL_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x0514, 0x0144, 1, 0x07D8, 2, 0),
|
||||
MX6DL_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x0518, 0x0148, 1, 0x07DC, 2, 0),
|
||||
MX6DL_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x051C, 0x014C, 1, 0x07E0, 2, 0),
|
||||
MX6DL_PAD_EIM_D19__GPIO_3_19 = IOMUX_PAD(0x0520, 0x0150, 5, 0x0000, 0, 0),
|
||||
MX6DL_PAD_EIM_D21__GPIO_3_21 = IOMUX_PAD(0x0528, 0x0158, 5, 0x0000, 0, 0),
|
||||
MX6DL_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, 0),
|
||||
MX6DL_PAD_EIM_D23__GPIO_3_23 = IOMUX_PAD(0x0530, 0x0160, 5, 0x0000, 0, 0),
|
||||
MX6DL_PAD_EIM_D26__UART2_TXD = IOMUX_PAD(0x053C, 0x016C, 4, 0x0000, 0, 0),
|
||||
MX6DL_PAD_EIM_D27__UART2_RXD = IOMUX_PAD(0x0540, 0x0170, 4, 0x0904, 1, 0),
|
||||
MX6DL_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0),
|
||||
MX6DL_PAD_EIM_D28__GPIO_3_28 = IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, 0),
|
||||
MX6DL_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x05B8, 0x01E8, 1, 0x0000, 0, 0),
|
||||
MX6DL_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x05BC, 0x01EC, 1, 0x0810, 0, 0),
|
||||
MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x05C0, 0x01F0, 1, 0x0000, 0, 0),
|
||||
MX6DL_PAD_ENET_RXD0__GPIO_1_27 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0),
|
||||
MX6DL_PAD_GPIO_16__GPIO_7_11 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0),
|
||||
MX6DL_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x05E4, 0x0214, 6 | IOMUX_CONFIG_SION, 0x087C, 1, 0),
|
||||
MX6DL_PAD_GPIO_17__GPIO_7_12 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0),
|
||||
MX6DL_PAD_GPIO_18__GPIO_7_13 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0),
|
||||
MX6DL_PAD_GPIO_19__GPIO_4_5 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0),
|
||||
MX6DL_PAD_GPIO_5__GPIO_1_5 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0),
|
||||
MX6DL_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0),
|
||||
MX6DL_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0),
|
||||
MX6DL_PAD_KEY_COL3__GPIO_4_12 = IOMUX_PAD(0x0638, 0x0250, 5, 0x0000, 0, 0),
|
||||
MX6DL_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0),
|
||||
MX6DL_PAD_KEY_ROW3__GPIO_4_13 = IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, 0),
|
||||
MX6DL_PAD_NANDF_D1__GPIO_2_1 = IOMUX_PAD(0x0670, 0x0288, 5, 0x0000, 0, 0),
|
||||
MX6DL_PAD_NANDF_D2__GPIO_2_2 = IOMUX_PAD(0x0674, 0x028C, 5, 0x0000, 0, 0),
|
||||
MX6DL_PAD_NANDF_D3__GPIO_2_3 = IOMUX_PAD(0x0678, 0x0290, 5, 0x0000, 0, 0),
|
||||
MX6DL_PAD_NANDF_D4__GPIO_2_4 = IOMUX_PAD(0x067C, 0x0294, 5, 0x0000, 0, 0),
|
||||
MX6DL_PAD_NANDF_D6__GPIO_2_6 = IOMUX_PAD(0x0684, 0x029C, 5, 0x0000, 0, 0),
|
||||
MX6DL_PAD_RGMII_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0818, 1, 0),
|
||||
MX6DL_PAD_RGMII_RD0__GPIO_6_25 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0),
|
||||
MX6DL_PAD_RGMII_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x0698, 0x02B0, 1, 0x081C, 1, 0),
|
||||
MX6DL_PAD_RGMII_RD1__GPIO_6_27 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0),
|
||||
MX6DL_PAD_RGMII_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0820, 1, 0),
|
||||
MX6DL_PAD_RGMII_RD2__GPIO_6_28 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0),
|
||||
MX6DL_PAD_RGMII_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0824, 1, 0),
|
||||
MX6DL_PAD_RGMII_RD3__GPIO_6_29 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0),
|
||||
MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0828, 1, 0),
|
||||
MX6DL_PAD_RGMII_RX_CTL__GPIO_6_24 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0),
|
||||
MX6DL_PAD_RGMII_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0814, 1, 0),
|
||||
MX6DL_PAD_RGMII_RXC__GPIO_6_30 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0),
|
||||
MX6DL_PAD_RGMII_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0),
|
||||
MX6DL_PAD_RGMII_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x06B0, 0x02C8, 1, 0x0000, 0, 0),
|
||||
MX6DL_PAD_RGMII_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, 0),
|
||||
MX6DL_PAD_RGMII_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0),
|
||||
MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0),
|
||||
MX6DL_PAD_RGMII_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0),
|
||||
MX6DL_PAD_SD1_CMD__GPIO_1_18 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0),
|
||||
MX6DL_PAD_SD1_DAT3__GPIO_1_21 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0),
|
||||
MX6DL_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, 0),
|
||||
MX6DL_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
|
||||
MX6DL_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0),
|
||||
MX6DL_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0),
|
||||
MX6DL_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0),
|
||||
MX6DL_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0),
|
||||
MX6DL_PAD_SD3_DAT5__GPIO_7_0 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0),
|
||||
MX6DL_PAD_SD3_DAT6__UART1_RXD = IOMUX_PAD(0x0714, 0x032C, 1, 0x08FC, 2, 0),
|
||||
MX6DL_PAD_SD3_DAT7__UART1_TXD = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0),
|
||||
MX6DL_PAD_SD4_CLK__USDHC4_CLK = IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, 0),
|
||||
MX6DL_PAD_SD4_CMD__USDHC4_CMD = IOMUX_PAD(0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
|
||||
MX6DL_PAD_SD4_DAT0__USDHC4_DAT0 = IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, 0),
|
||||
MX6DL_PAD_SD4_DAT1__USDHC4_DAT1 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0),
|
||||
MX6DL_PAD_SD4_DAT2__USDHC4_DAT2 = IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, 0),
|
||||
MX6DL_PAD_SD4_DAT3__USDHC4_DAT3 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, 0),
|
||||
MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3 = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6_PAD_DI0_PIN4__GPIO_4_20 = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
|
||||
MX6_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x0514, 0x0144, 1, 0x07D8, 2, 0),
|
||||
MX6_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x0518, 0x0148, 1, 0x07DC, 2, 0),
|
||||
MX6_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x051C, 0x014C, 1, 0x07E0, 2, 0),
|
||||
MX6_PAD_EIM_D19__GPIO_3_19 = IOMUX_PAD(0x0520, 0x0150, 5, 0x0000, 0, 0),
|
||||
MX6_PAD_EIM_D21__GPIO_3_21 = IOMUX_PAD(0x0528, 0x0158, 5, 0x0000, 0, 0),
|
||||
MX6_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, 0),
|
||||
MX6_PAD_EIM_D23__GPIO_3_23 = IOMUX_PAD(0x0530, 0x0160, 5, 0x0000, 0, 0),
|
||||
MX6_PAD_EIM_D26__UART2_TXD = IOMUX_PAD(0x053C, 0x016C, 4, 0x0000, 0, 0),
|
||||
MX6_PAD_EIM_D27__UART2_RXD = IOMUX_PAD(0x0540, 0x0170, 4, 0x0904, 1, 0),
|
||||
MX6_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0),
|
||||
MX6_PAD_EIM_D28__GPIO_3_28 = IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, 0),
|
||||
MX6_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x05B8, 0x01E8, 1, 0x0000, 0, 0),
|
||||
MX6_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x05BC, 0x01EC, 1, 0x0810, 0, 0),
|
||||
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x05C0, 0x01F0, 1, 0x0000, 0, 0),
|
||||
MX6_PAD_ENET_RXD0__GPIO_1_27 = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0),
|
||||
MX6_PAD_GPIO_16__GPIO_7_11 = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0),
|
||||
MX6_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x05E4, 0x0214, 6 | IOMUX_CONFIG_SION, 0x087C, 1, 0),
|
||||
MX6_PAD_GPIO_17__GPIO_7_12 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0),
|
||||
MX6_PAD_GPIO_18__GPIO_7_13 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0),
|
||||
MX6_PAD_GPIO_19__GPIO_4_5 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0),
|
||||
MX6_PAD_GPIO_5__GPIO_1_5 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0),
|
||||
MX6_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0),
|
||||
MX6_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0),
|
||||
MX6_PAD_KEY_COL3__GPIO_4_12 = IOMUX_PAD(0x0638, 0x0250, 5, 0x0000, 0, 0),
|
||||
MX6_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0),
|
||||
MX6_PAD_KEY_ROW3__GPIO_4_13 = IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, 0),
|
||||
MX6_PAD_NANDF_CS1__GPIO_6_14 = IOMUX_PAD(0x0660, 0x0278, 5, 0x0000, 0, 0),
|
||||
MX6_PAD_NANDF_CS2__GPIO_6_15 = IOMUX_PAD(0x0664, 0x027C, 5, 0x0000, 0, 0),
|
||||
MX6_PAD_NANDF_CS3__GPIO_6_16 = IOMUX_PAD(0x0668, 0x0280, 5, 0x0000, 0, 0),
|
||||
MX6_PAD_NANDF_D1__GPIO_2_1 = IOMUX_PAD(0x0670, 0x0288, 5, 0x0000, 0, 0),
|
||||
MX6_PAD_NANDF_D2__GPIO_2_2 = IOMUX_PAD(0x0674, 0x028C, 5, 0x0000, 0, 0),
|
||||
MX6_PAD_NANDF_D3__GPIO_2_3 = IOMUX_PAD(0x0678, 0x0290, 5, 0x0000, 0, 0),
|
||||
MX6_PAD_NANDF_D4__GPIO_2_4 = IOMUX_PAD(0x067C, 0x0294, 5, 0x0000, 0, 0),
|
||||
MX6_PAD_NANDF_D6__GPIO_2_6 = IOMUX_PAD(0x0684, 0x029C, 5, 0x0000, 0, 0),
|
||||
MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0818, 1, 0),
|
||||
MX6_PAD_RGMII_RD0__GPIO_6_25 = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0),
|
||||
MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 = IOMUX_PAD(0x0698, 0x02B0, 1, 0x081C, 1, 0),
|
||||
MX6_PAD_RGMII_RD1__GPIO_6_27 = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0),
|
||||
MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0820, 1, 0),
|
||||
MX6_PAD_RGMII_RD2__GPIO_6_28 = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0),
|
||||
MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0824, 1, 0),
|
||||
MX6_PAD_RGMII_RD3__GPIO_6_29 = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0),
|
||||
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0828, 1, 0),
|
||||
MX6_PAD_RGMII_RX_CTL__GPIO_6_24 = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0),
|
||||
MX6_PAD_RGMII_RXC__ENET_RGMII_RXC = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0814, 1, 0),
|
||||
MX6_PAD_RGMII_RXC__GPIO_6_30 = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0),
|
||||
MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0),
|
||||
MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 = IOMUX_PAD(0x06B0, 0x02C8, 1, 0x0000, 0, 0),
|
||||
MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, 0),
|
||||
MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0),
|
||||
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0),
|
||||
MX6_PAD_RGMII_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0),
|
||||
MX6_PAD_SD1_CMD__GPIO_1_18 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0),
|
||||
MX6_PAD_SD1_DAT3__GPIO_1_21 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0),
|
||||
MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, 0),
|
||||
MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
|
||||
MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0),
|
||||
MX6_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0),
|
||||
MX6_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0),
|
||||
MX6_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0),
|
||||
MX6_PAD_SD3_DAT5__GPIO_7_0 = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0),
|
||||
MX6_PAD_SD3_DAT6__UART1_RXD = IOMUX_PAD(0x0714, 0x032C, 1, 0x08FC, 2, 0),
|
||||
MX6_PAD_SD3_DAT7__UART1_TXD = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0),
|
||||
MX6_PAD_SD4_CLK__USDHC4_CLK = IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, 0),
|
||||
MX6_PAD_SD4_CMD__USDHC4_CMD = IOMUX_PAD(0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
|
||||
MX6_PAD_SD4_DAT0__USDHC4_DAT0 = IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, 0),
|
||||
MX6_PAD_SD4_DAT1__USDHC4_DAT1 = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0),
|
||||
MX6_PAD_SD4_DAT2__USDHC4_DAT2 = IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, 0),
|
||||
MX6_PAD_SD4_DAT3__USDHC4_DAT3 = IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, 0),
|
||||
};
|
||||
#endif /* __ASM_ARCH_MX6_MX6DL_PINS_H__ */
|
||||
|
|
|
@ -0,0 +1,69 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Boundary Devices Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
#ifndef __ASM_ARCH_MX6Q_DDR_H__
|
||||
#define __ASM_ARCH_MX6Q_DDR_H__
|
||||
|
||||
#ifndef CONFIG_MX6Q
|
||||
#error "wrong CPU"
|
||||
#endif
|
||||
|
||||
#define MX6_IOM_DRAM_DQM0 0x020e05ac
|
||||
#define MX6_IOM_DRAM_DQM1 0x020e05b4
|
||||
#define MX6_IOM_DRAM_DQM2 0x020e0528
|
||||
#define MX6_IOM_DRAM_DQM3 0x020e0520
|
||||
#define MX6_IOM_DRAM_DQM4 0x020e0514
|
||||
#define MX6_IOM_DRAM_DQM5 0x020e0510
|
||||
#define MX6_IOM_DRAM_DQM6 0x020e05bc
|
||||
#define MX6_IOM_DRAM_DQM7 0x020e05c4
|
||||
|
||||
#define MX6_IOM_DRAM_CAS 0x020e056c
|
||||
#define MX6_IOM_DRAM_RAS 0x020e0578
|
||||
#define MX6_IOM_DRAM_RESET 0x020e057c
|
||||
#define MX6_IOM_DRAM_SDCLK_0 0x020e0588
|
||||
#define MX6_IOM_DRAM_SDCLK_1 0x020e0594
|
||||
#define MX6_IOM_DRAM_SDBA2 0x020e058c
|
||||
#define MX6_IOM_DRAM_SDCKE0 0x020e0590
|
||||
#define MX6_IOM_DRAM_SDCKE1 0x020e0598
|
||||
#define MX6_IOM_DRAM_SDODT0 0x020e059c
|
||||
#define MX6_IOM_DRAM_SDODT1 0x020e05a0
|
||||
|
||||
#define MX6_IOM_DRAM_SDQS0 0x020e05a8
|
||||
#define MX6_IOM_DRAM_SDQS1 0x020e05b0
|
||||
#define MX6_IOM_DRAM_SDQS2 0x020e0524
|
||||
#define MX6_IOM_DRAM_SDQS3 0x020e051c
|
||||
#define MX6_IOM_DRAM_SDQS4 0x020e0518
|
||||
#define MX6_IOM_DRAM_SDQS5 0x020e050c
|
||||
#define MX6_IOM_DRAM_SDQS6 0x020e05b8
|
||||
#define MX6_IOM_DRAM_SDQS7 0x020e05c0
|
||||
|
||||
#define MX6_IOM_GRP_B0DS 0x020e0784
|
||||
#define MX6_IOM_GRP_B1DS 0x020e0788
|
||||
#define MX6_IOM_GRP_B2DS 0x020e0794
|
||||
#define MX6_IOM_GRP_B3DS 0x020e079c
|
||||
#define MX6_IOM_GRP_B4DS 0x020e07a0
|
||||
#define MX6_IOM_GRP_B5DS 0x020e07a4
|
||||
#define MX6_IOM_GRP_B6DS 0x020e07a8
|
||||
#define MX6_IOM_GRP_B7DS 0x020e0748
|
||||
#define MX6_IOM_GRP_ADDDS 0x020e074c
|
||||
#define MX6_IOM_DDRMODE_CTL 0x020e0750
|
||||
#define MX6_IOM_GRP_DDRPKE 0x020e0758
|
||||
#define MX6_IOM_GRP_DDRMODE 0x020e0774
|
||||
#define MX6_IOM_GRP_CTLDS 0x020e078c
|
||||
#define MX6_IOM_GRP_DDR_TYPE 0x020e0798
|
||||
|
||||
#endif /*__ASM_ARCH_MX6Q_DDR_H__ */
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -40,6 +40,19 @@
|
|||
/*
|
||||
* MXS DMA channels
|
||||
*/
|
||||
#if defined(CONFIG_MX23)
|
||||
enum {
|
||||
MXS_DMA_CHANNEL_AHB_APBH_LCDIF = 0,
|
||||
MXS_DMA_CHANNEL_AHB_APBH_SSP0,
|
||||
MXS_DMA_CHANNEL_AHB_APBH_SSP1,
|
||||
MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
|
||||
MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
|
||||
MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
|
||||
MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
|
||||
MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
|
||||
MXS_MAX_DMA_CHANNELS,
|
||||
};
|
||||
#elif defined(CONFIG_MX28)
|
||||
enum {
|
||||
MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0,
|
||||
MXS_DMA_CHANNEL_AHB_APBH_SSP1,
|
||||
|
@ -53,9 +66,13 @@ enum {
|
|||
MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
|
||||
MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
|
||||
MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
|
||||
MXS_DMA_CHANNEL_AHB_APBH_SSP,
|
||||
MXS_DMA_CHANNEL_AHB_APBH_HSADC,
|
||||
MXS_DMA_CHANNEL_AHB_APBH_LCDIF,
|
||||
MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
|
||||
MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
|
||||
MXS_MAX_DMA_CHANNELS,
|
||||
};
|
||||
#endif
|
||||
|
||||
/*
|
||||
* MXS DMA hardware command.
|
||||
|
|
|
@ -36,6 +36,8 @@
|
|||
#include <asm/arch/regs-rtc.h>
|
||||
#include <asm/arch/regs-ssp.h>
|
||||
#include <asm/arch/regs-timrot.h>
|
||||
#include <asm/arch/regs-usb.h>
|
||||
#include <asm/arch/regs-usbphy.h>
|
||||
|
||||
#ifdef CONFIG_MX23
|
||||
#include <asm/arch/regs-clkctrl-mx23.h>
|
||||
|
|
|
@ -21,6 +21,10 @@
|
|||
#ifndef __MACH_MXS_IOMUX_H__
|
||||
#define __MACH_MXS_IOMUX_H__
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <asm/types.h>
|
||||
|
||||
/*
|
||||
* IOMUX/PAD Bit field definitions
|
||||
*
|
||||
|
@ -165,4 +169,5 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad);
|
|||
*/
|
||||
int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count);
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __MACH_MXS_IOMUX_H__*/
|
||||
|
|
|
@ -74,6 +74,32 @@ struct mxs_ssp_regs {
|
|||
};
|
||||
#endif
|
||||
|
||||
static inline int mxs_ssp_bus_id_valid(int bus)
|
||||
{
|
||||
#if defined(CONFIG_MX23)
|
||||
const unsigned int mxs_ssp_chan_count = 2;
|
||||
#elif defined(CONFIG_MX28)
|
||||
const unsigned int mxs_ssp_chan_count = 4;
|
||||
#endif
|
||||
|
||||
if (bus >= mxs_ssp_chan_count)
|
||||
return 0;
|
||||
|
||||
if (bus < 0)
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static inline int mxs_ssp_clock_by_bus(unsigned int clock)
|
||||
{
|
||||
#if defined(CONFIG_MX23)
|
||||
return 0;
|
||||
#elif defined(CONFIG_MX28)
|
||||
return clock;
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port)
|
||||
{
|
||||
switch (port) {
|
||||
|
|
|
@ -31,6 +31,16 @@
|
|||
struct mxs_timrot_regs {
|
||||
mxs_reg_32(hw_timrot_rotctrl)
|
||||
mxs_reg_32(hw_timrot_rotcount)
|
||||
#if defined(CONFIG_MX23)
|
||||
mxs_reg_32(hw_timrot_timctrl0)
|
||||
mxs_reg_32(hw_timrot_timcount0)
|
||||
mxs_reg_32(hw_timrot_timctrl1)
|
||||
mxs_reg_32(hw_timrot_timcount1)
|
||||
mxs_reg_32(hw_timrot_timctrl2)
|
||||
mxs_reg_32(hw_timrot_timcount2)
|
||||
mxs_reg_32(hw_timrot_timctrl3)
|
||||
mxs_reg_32(hw_timrot_timcount3)
|
||||
#elif defined(CONFIG_MX28)
|
||||
mxs_reg_32(hw_timrot_timctrl0)
|
||||
mxs_reg_32(hw_timrot_running_count0)
|
||||
mxs_reg_32(hw_timrot_fixed_count0)
|
||||
|
@ -47,6 +57,7 @@ struct mxs_timrot_regs {
|
|||
mxs_reg_32(hw_timrot_running_count3)
|
||||
mxs_reg_32(hw_timrot_fixed_count3)
|
||||
mxs_reg_32(hw_timrot_match_count3)
|
||||
#endif
|
||||
mxs_reg_32(hw_timrot_version)
|
||||
};
|
||||
#endif
|
||||
|
@ -71,7 +82,11 @@ struct mxs_timrot_regs {
|
|||
#define TIMROT_ROTCTRL_OVERSAMPLE_1X (0x3 << 10)
|
||||
#define TIMROT_ROTCTRL_POLARITY_B (1 << 9)
|
||||
#define TIMROT_ROTCTRL_POLARITY_A (1 << 8)
|
||||
#if defined(CONFIG_MX23)
|
||||
#define TIMROT_ROTCTRL_SELECT_B_MASK (0x7 << 4)
|
||||
#elif defined(CONFIG_MX28)
|
||||
#define TIMROT_ROTCTRL_SELECT_B_MASK (0xf << 4)
|
||||
#endif
|
||||
#define TIMROT_ROTCTRL_SELECT_B_OFFSET 4
|
||||
#define TIMROT_ROTCTRL_SELECT_B_NEVER_TICK (0x0 << 4)
|
||||
#define TIMROT_ROTCTRL_SELECT_B_PWM0 (0x1 << 4)
|
||||
|
@ -79,12 +94,21 @@ struct mxs_timrot_regs {
|
|||
#define TIMROT_ROTCTRL_SELECT_B_PWM2 (0x3 << 4)
|
||||
#define TIMROT_ROTCTRL_SELECT_B_PWM3 (0x4 << 4)
|
||||
#define TIMROT_ROTCTRL_SELECT_B_PWM4 (0x5 << 4)
|
||||
#if defined(CONFIG_MX23)
|
||||
#define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x6 << 4)
|
||||
#define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0x7 << 4)
|
||||
#elif defined(CONFIG_MX28)
|
||||
#define TIMROT_ROTCTRL_SELECT_B_PWM5 (0x6 << 4)
|
||||
#define TIMROT_ROTCTRL_SELECT_B_PWM6 (0x7 << 4)
|
||||
#define TIMROT_ROTCTRL_SELECT_B_PWM7 (0x8 << 4)
|
||||
#define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x9 << 4)
|
||||
#define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0xa << 4)
|
||||
#endif
|
||||
#if defined(CONFIG_MX23)
|
||||
#define TIMROT_ROTCTRL_SELECT_A_MASK 0x7
|
||||
#elif defined(CONFIG_MX28)
|
||||
#define TIMROT_ROTCTRL_SELECT_A_MASK 0xf
|
||||
#endif
|
||||
#define TIMROT_ROTCTRL_SELECT_A_OFFSET 0
|
||||
#define TIMROT_ROTCTRL_SELECT_A_NEVER_TICK 0x0
|
||||
#define TIMROT_ROTCTRL_SELECT_A_PWM0 0x1
|
||||
|
@ -92,18 +116,25 @@ struct mxs_timrot_regs {
|
|||
#define TIMROT_ROTCTRL_SELECT_A_PWM2 0x3
|
||||
#define TIMROT_ROTCTRL_SELECT_A_PWM3 0x4
|
||||
#define TIMROT_ROTCTRL_SELECT_A_PWM4 0x5
|
||||
#if defined(CONFIG_MX23)
|
||||
#define TIMROT_ROTCTRL_SELECT_A_ROTARYA 0x6
|
||||
#define TIMROT_ROTCTRL_SELECT_A_ROTARYB 0x7
|
||||
#elif defined(CONFIG_MX28)
|
||||
#define TIMROT_ROTCTRL_SELECT_A_PWM5 0x6
|
||||
#define TIMROT_ROTCTRL_SELECT_A_PWM6 0x7
|
||||
#define TIMROT_ROTCTRL_SELECT_A_PWM7 0x8
|
||||
#define TIMROT_ROTCTRL_SELECT_A_ROTARYA 0x9
|
||||
#define TIMROT_ROTCTRL_SELECT_A_ROTARYB 0xa
|
||||
#endif
|
||||
|
||||
#define TIMROT_ROTCOUNT_UPDOWN_MASK 0xffff
|
||||
#define TIMROT_ROTCOUNT_UPDOWN_OFFSET 0
|
||||
|
||||
#define TIMROT_TIMCTRLn_IRQ (1 << 15)
|
||||
#define TIMROT_TIMCTRLn_IRQ_EN (1 << 14)
|
||||
#if defined(CONFIG_MX28)
|
||||
#define TIMROT_TIMCTRLn_MATCH_MODE (1 << 11)
|
||||
#endif
|
||||
#define TIMROT_TIMCTRLn_POLARITY (1 << 8)
|
||||
#define TIMROT_TIMCTRLn_UPDATE (1 << 7)
|
||||
#define TIMROT_TIMCTRLn_RELOAD (1 << 6)
|
||||
|
@ -121,6 +152,15 @@ struct mxs_timrot_regs {
|
|||
#define TIMROT_TIMCTRLn_SELECT_PWM2 0x3
|
||||
#define TIMROT_TIMCTRLn_SELECT_PWM3 0x4
|
||||
#define TIMROT_TIMCTRLn_SELECT_PWM4 0x5
|
||||
#if defined(CONFIG_MX23)
|
||||
#define TIMROT_TIMCTRLn_SELECT_ROTARYA 0x6
|
||||
#define TIMROT_TIMCTRLn_SELECT_ROTARYB 0x7
|
||||
#define TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL 0x8
|
||||
#define TIMROT_TIMCTRLn_SELECT_8KHZ_XTAL 0x9
|
||||
#define TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL 0xa
|
||||
#define TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL 0xb
|
||||
#define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xc
|
||||
#elif defined(CONFIG_MX28)
|
||||
#define TIMROT_TIMCTRLn_SELECT_PWM5 0x6
|
||||
#define TIMROT_TIMCTRLn_SELECT_PWM6 0x7
|
||||
#define TIMROT_TIMCTRLn_SELECT_PWM7 0x8
|
||||
|
@ -131,15 +171,28 @@ struct mxs_timrot_regs {
|
|||
#define TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL 0xd
|
||||
#define TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL 0xe
|
||||
#define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xf
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MX23)
|
||||
#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK (0xffff << 16)
|
||||
#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 16
|
||||
#elif defined(CONFIG_MX28)
|
||||
#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK 0xffffffff
|
||||
#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 0
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MX23)
|
||||
#define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffff
|
||||
#define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0
|
||||
#elif defined(CONFIG_MX28)
|
||||
#define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffffffff
|
||||
#define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MX28)
|
||||
#define TIMROT_MATCH_COUNTn_MATCH_COUNT_MASK 0xffffffff
|
||||
#define TIMROT_MATCH_COUNTn_MATCH_COUNT_OFFSET 0
|
||||
#endif
|
||||
|
||||
#define TIMROT_TIMCTRL3_TEST_SIGNAL_MASK (0xf << 16)
|
||||
#define TIMROT_TIMCTRL3_TEST_SIGNAL_OFFSET 16
|
||||
|
@ -149,6 +202,15 @@ struct mxs_timrot_regs {
|
|||
#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM2 (0x3 << 16)
|
||||
#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM3 (0x4 << 16)
|
||||
#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM4 (0x5 << 16)
|
||||
#if defined(CONFIG_MX23)
|
||||
#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA (0x6 << 16)
|
||||
#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB (0x7 << 16)
|
||||
#define TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL (0x8 << 16)
|
||||
#define TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL (0x9 << 16)
|
||||
#define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xa << 16)
|
||||
#define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xb << 16)
|
||||
#define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xc << 16)
|
||||
#elif defined(CONFIG_MX28)
|
||||
#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM5 (0x6 << 16)
|
||||
#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM6 (0x7 << 16)
|
||||
#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM7 (0x8 << 16)
|
||||
|
@ -159,7 +221,46 @@ struct mxs_timrot_regs {
|
|||
#define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xd << 16)
|
||||
#define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xe << 16)
|
||||
#define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xf << 16)
|
||||
#endif
|
||||
#if defined(CONFIG_MX23)
|
||||
#define TIMROT_TIMCTRL3_IRQ (1 << 15)
|
||||
#define TIMROT_TIMCTRL3_IRQ_EN (1 << 14)
|
||||
#define TIMROT_TIMCTRL3_DUTU_VALID (1 << 10)
|
||||
#endif
|
||||
#define TIMROT_TIMCTRL3_DUTY_CYCLE (1 << 9)
|
||||
#if defined(CONFIG_MX23)
|
||||
#define TIMROT_TIMCTRL3_POLARITY_MASK (0x1 << 8)
|
||||
#define TIMROT_TIMCTRL3_POLARITY_OFFSET 8
|
||||
#define TIMROT_TIMCTRL3_POLARITY_POSITIVE (0x0 << 8)
|
||||
#define TIMROT_TIMCTRL3_POLARITY_NEGATIVE (0x1 << 8)
|
||||
#define TIMROT_TIMCTRL3_UPDATE (1 << 7)
|
||||
#define TIMROT_TIMCTRL3_RELOAD (1 << 6)
|
||||
#define TIMROT_TIMCTRL3_PRESCALE_MASK (0x3 << 4)
|
||||
#define TIMROT_TIMCTRL3_PRESCALE_OFFSET 4
|
||||
#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_1 (0x0 << 4)
|
||||
#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_2 (0x1 << 4)
|
||||
#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_4 (0x2 << 4)
|
||||
#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_8 (0x3 << 4)
|
||||
#define TIMROT_TIMCTRL3_SELECT_MASK 0xf
|
||||
#define TIMROT_TIMCTRL3_SELECT_OFFSET 0
|
||||
#define TIMROT_TIMCTRL3_SELECT_NEVER_TICK 0x0
|
||||
#define TIMROT_TIMCTRL3_SELECT_PWM0 0x1
|
||||
#define TIMROT_TIMCTRL3_SELECT_PWM1 0x2
|
||||
#define TIMROT_TIMCTRL3_SELECT_PWM2 0x3
|
||||
#define TIMROT_TIMCTRL3_SELECT_PWM3 0x4
|
||||
#define TIMROT_TIMCTRL3_SELECT_PWM4 0x5
|
||||
#define TIMROT_TIMCTRL3_SELECT_ROTARYA 0x6
|
||||
#define TIMROT_TIMCTRL3_SELECT_ROTARYB 0x7
|
||||
#define TIMROT_TIMCTRL3_SELECT_32KHZ_XTAL 0x8
|
||||
#define TIMROT_TIMCTRL3_SELECT_8KHZ_XTAL 0x9
|
||||
#define TIMROT_TIMCTRL3_SELECT_4KHZ_XTAL 0xa
|
||||
#define TIMROT_TIMCTRL3_SELECT_1KHZ_XTAL 0xb
|
||||
#define TIMROT_TIMCTRL3_SELECT_TICK_ALWAYS 0xc
|
||||
#define TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_MASK (0xffff << 16)
|
||||
#define TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_OFFSET 16
|
||||
#define TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_MASK 0xffff
|
||||
#define TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_OFFSET 0
|
||||
#endif
|
||||
|
||||
#define TIMROT_VERSION_MAJOR_MASK (0xff << 24)
|
||||
#define TIMROT_VERSION_MAJOR_OFFSET 24
|
||||
|
|
|
@ -0,0 +1,58 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Boundary Devices
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not write to the Free Software
|
||||
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
|
||||
* MA 02110-1301 USA
|
||||
*
|
||||
*/
|
||||
DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
|
||||
DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7974
|
||||
DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64
|
||||
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
|
||||
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
|
||||
DATA 4, MX6_MMDC_P0_MDOR, 0x005A1023
|
||||
DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
|
||||
DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
|
||||
DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
|
||||
DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
|
||||
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
|
||||
DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
|
||||
DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
|
||||
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
|
||||
DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
|
||||
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42720306
|
||||
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x026F0266
|
||||
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4273030A
|
||||
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02740240
|
||||
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x45393B3E
|
||||
DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x403A3747
|
||||
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x40434541
|
||||
DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x473E4A3B
|
||||
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0011000E
|
||||
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x000E001B
|
||||
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00190015
|
||||
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00070018
|
||||
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
|
||||
DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
|
||||
DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
|
|
@ -0,0 +1,58 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Boundary Devices
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not write to the Free Software
|
||||
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
|
||||
* MA 02110-1301 USA
|
||||
*
|
||||
*/
|
||||
DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
|
||||
DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E7974
|
||||
DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64
|
||||
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
|
||||
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
|
||||
DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023
|
||||
DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
|
||||
DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
|
||||
DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
|
||||
DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
|
||||
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
|
||||
DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
|
||||
DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
|
||||
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
|
||||
DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
|
||||
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43040319
|
||||
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03040279
|
||||
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43040321
|
||||
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03030251
|
||||
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4d434248
|
||||
DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x42413c4d
|
||||
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x34424543
|
||||
DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x49324933
|
||||
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001a0017
|
||||
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
|
||||
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00170027
|
||||
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x000a001f
|
||||
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
|
||||
DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
|
||||
DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
|
|
@ -0,0 +1,63 @@
|
|||
setenv bootargs enable_wait_mode=off
|
||||
setenv nextcon 0;
|
||||
|
||||
if hdmidet ; then
|
||||
setenv bootargs $bootargs video=mxcfb${nextcon}:dev=hdmi,1280x720M@60,if=RGB24
|
||||
setenv fbmem "fbmem=28M";
|
||||
setexpr nextcon $nextcon + 1
|
||||
else
|
||||
echo "------ no HDMI monitor";
|
||||
fi
|
||||
|
||||
i2c dev 2
|
||||
if i2c probe 0x04 ; then
|
||||
setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,LDB-XGA,if=RGB666
|
||||
if test "0" -eq $nextcon; then
|
||||
setenv fbmem "fbmem=10M";
|
||||
else
|
||||
setenv fbmem ${fbmem},10M
|
||||
fi
|
||||
setexpr nextcon $nextcon + 1
|
||||
else
|
||||
echo "------ no Freescale display";
|
||||
fi
|
||||
|
||||
if i2c probe 0x38 ; then
|
||||
setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1024x600M@60,if=RGB666
|
||||
if test "0" -eq $nextcon; then
|
||||
setenv fbmem "fbmem=10M";
|
||||
else
|
||||
setenv fbmem ${fbmem},10M
|
||||
fi
|
||||
setexpr nextcon $nextcon + 1
|
||||
else
|
||||
echo "------ no 1024x600 display";
|
||||
fi
|
||||
|
||||
if i2c probe 0x48 ; then
|
||||
setenv bootargs $bootargs video=mxcfb${nextcon}:dev=lcd,CLAA-WVGA,if=RGB666
|
||||
if test "0" -eq $nextcon; then
|
||||
setenv fbmem "fbmem=10M";
|
||||
else
|
||||
setenv fbmem ${fbmem},10M
|
||||
fi
|
||||
setexpr nextcon $nextcon + 1
|
||||
else
|
||||
echo "------ no 800x480 display";
|
||||
fi
|
||||
|
||||
while test "3" -ne $nextcon ; do
|
||||
setenv bootargs $bootargs video=mxcfb${nextcon}:off ;
|
||||
setexpr nextcon $nextcon + 1 ;
|
||||
done
|
||||
|
||||
setenv bootargs $bootargs $fbmem
|
||||
setenv bootargs "$bootargs console=ttymxc1,115200 vmalloc=400M consoleblank=0 rootwait"
|
||||
|
||||
if test "sata" = "${dtype}" ; then
|
||||
setenv bootargs "$bootargs root=/dev/sda1" ;
|
||||
else
|
||||
setenv "bootargs $bootargs root=/dev/mmcblk0p1" ;
|
||||
fi
|
||||
${fs}load ${dtype} ${disk}:1 10800000 /boot/uImage && bootm 10800000 ;
|
||||
echo "Error loading kernel image"
|
|
@ -0,0 +1,64 @@
|
|||
${dtype} dev ${disk}
|
||||
|
||||
setenv bootargs enable_wait_mode=off
|
||||
setenv nextcon 0;
|
||||
setenv bootargs $bootargs console=ttymxc1,115200 vmalloc=400M consoleblank=0 ;
|
||||
|
||||
i2c dev 2
|
||||
|
||||
if i2c probe 0x04 ; then
|
||||
setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,LDB-XGA,if=RGB666
|
||||
if test "0" -eq $nextcon; then
|
||||
setenv fbcon "fbcon=10M";
|
||||
else
|
||||
setenv fbcon ${fbcon},10M
|
||||
fi
|
||||
setexpr nextcon $nextcon + 1
|
||||
else
|
||||
echo "------ no Freescale display";
|
||||
fi
|
||||
|
||||
if i2c probe 0x38 ; then
|
||||
setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1024x600M@60,if=RGB666
|
||||
if test "0" -eq $nextcon; then
|
||||
setenv fbcon "fbcon=10M";
|
||||
else
|
||||
setenv fbcon ${fbcon},10M
|
||||
fi
|
||||
setexpr nextcon $nextcon + 1
|
||||
else
|
||||
echo "------ no 1024x600 display";
|
||||
fi
|
||||
|
||||
if i2c probe 0x48 ; then
|
||||
setenv bootargs $bootargs video=mxcfb${nextcon}:dev=lcd,CLAA-WVGA,if=RGB666 tsdev=tsc2004 calibration
|
||||
if test "0" -eq $nextcon; then
|
||||
setenv fbcon "fbcon=10M";
|
||||
else
|
||||
setenv fbcon ${fbcon},10M
|
||||
fi
|
||||
setexpr nextcon $nextcon + 1
|
||||
else
|
||||
echo "------ no 800x480 display";
|
||||
fi
|
||||
|
||||
if hdmidet ; then
|
||||
setenv bootargs $bootargs video=mxcfb${nextcon}:dev=hdmi,1280x720M@60,if=RGB24
|
||||
if test "0" -eq $nextcon; then
|
||||
setenv fbcon "fbcon=28M";
|
||||
else
|
||||
setenv fbcon ${fbcon},28M
|
||||
fi
|
||||
setexpr nextcon $nextcon + 1
|
||||
else
|
||||
echo "------ no HDMI monitor";
|
||||
fi
|
||||
|
||||
while test "3" -ne $nextcon ; do
|
||||
setenv bootargs $bootargs video=mxcfb${nextcon}:off ;
|
||||
setexpr nextcon $nextcon + 1 ;
|
||||
done
|
||||
|
||||
setenv bootargs $bootargs fbcon=$fbcon
|
||||
${fs}load ${dtype} ${disk}:1 10800000 uImage && ${fs}load ${dtype} ${disk}:1 12800000 uramdisk.img && bootm 10800000 12800000
|
||||
echo "Error loading kernel image"
|
|
@ -0,0 +1,64 @@
|
|||
${dtype} dev ${disk}
|
||||
|
||||
setenv bootargs enable_wait_mode=off
|
||||
setenv nextcon 0;
|
||||
setenv bootargs $bootargs console=ttymxc1,115200 vmalloc=400M consoleblank=0 ;
|
||||
|
||||
i2c dev 2
|
||||
|
||||
if i2c probe 0x04 ; then
|
||||
setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,LDB-XGA,if=RGB666
|
||||
if test "0" -eq $nextcon; then
|
||||
setenv fbcon "fbcon=10M";
|
||||
else
|
||||
setenv fbcon ${fbcon},10M
|
||||
fi
|
||||
setexpr nextcon $nextcon + 1
|
||||
else
|
||||
echo "------ no Freescale display";
|
||||
fi
|
||||
|
||||
if i2c probe 0x38 ; then
|
||||
setenv bootargs $bootargs video=mxcfb${nextcon}:dev=ldb,1024x600M@60,if=RGB666
|
||||
if test "0" -eq $nextcon; then
|
||||
setenv fbcon "fbcon=10M";
|
||||
else
|
||||
setenv fbcon ${fbcon},10M
|
||||
fi
|
||||
setexpr nextcon $nextcon + 1
|
||||
else
|
||||
echo "------ no 1024x600 display";
|
||||
fi
|
||||
|
||||
if i2c probe 0x48 ; then
|
||||
setenv bootargs $bootargs video=mxcfb${nextcon}:dev=lcd,CLAA-WVGA,if=RGB666 tsdev=tsc2004 calibration
|
||||
if test "0" -eq $nextcon; then
|
||||
setenv fbcon "fbcon=10M";
|
||||
else
|
||||
setenv fbcon ${fbcon},10M
|
||||
fi
|
||||
setexpr nextcon $nextcon + 1
|
||||
else
|
||||
echo "------ no 800x480 display";
|
||||
fi
|
||||
|
||||
if hdmidet ; then
|
||||
setenv bootargs $bootargs video=mxcfb${nextcon}:dev=hdmi,1280x720M@60,if=RGB24
|
||||
if test "0" -eq $nextcon; then
|
||||
setenv fbcon "fbcon=28M";
|
||||
else
|
||||
setenv fbcon ${fbcon},28M
|
||||
fi
|
||||
setexpr nextcon $nextcon + 1
|
||||
else
|
||||
echo "------ no HDMI monitor";
|
||||
fi
|
||||
|
||||
while test "3" -ne $nextcon ; do
|
||||
setenv bootargs $bootargs video=mxcfb${nextcon}:off ;
|
||||
setexpr nextcon $nextcon + 1 ;
|
||||
done
|
||||
|
||||
setenv bootargs $bootargs fbcon=$fbcon
|
||||
${fs}load ${dtype} ${disk}:1 10800000 uImage && ${fs}load ${dtype} ${disk}:1 12800000 uramdisk.img && bootm 10800000 12800000
|
||||
echo "Error loading kernel image"
|
|
@ -0,0 +1,45 @@
|
|||
setenv stdout serial,vga
|
||||
echo "check U-Boot" ;
|
||||
setenv offset 0x400
|
||||
if ${fs}load ${dtype} ${disk}:1 12000000 u-boot.imx || ${fs}load ${dtype} ${disk}:1 12000000 u-boot.nopadding ; then
|
||||
echo "read $filesize bytes from SD card" ;
|
||||
if sf probe || sf probe || \
|
||||
sf probe 1 27000000 || sf probe 1 27000000 ; then
|
||||
echo "probed SPI ROM" ;
|
||||
if sf read 0x12400000 $offset $filesize ; then
|
||||
if cmp.b 0x12000000 0x12400000 $filesize ; then
|
||||
echo "------- U-Boot versions match" ;
|
||||
else
|
||||
echo "Need U-Boot upgrade" ;
|
||||
echo "Program in 5 seconds" ;
|
||||
for n in 5 4 3 2 1 ; do
|
||||
echo $n ;
|
||||
sleep 1 ;
|
||||
done
|
||||
echo "erasing" ;
|
||||
sf erase 0 0x50000 ;
|
||||
# two steps to prevent bricking
|
||||
echo "programming" ;
|
||||
sf write 0x12000000 $offset $filesize ;
|
||||
echo "verifying" ;
|
||||
if sf read 0x12400000 $offset $filesize ; then
|
||||
if cmp.b 0x12000000 0x12400000 $filesize ; then
|
||||
while echo "---- U-Boot upgraded. reset" ; do
|
||||
sleep 120
|
||||
done
|
||||
else
|
||||
echo "Read verification error" ;
|
||||
fi
|
||||
else
|
||||
echo "Error re-reading EEPROM" ;
|
||||
fi
|
||||
fi
|
||||
else
|
||||
echo "Error reading boot loader from EEPROM" ;
|
||||
fi
|
||||
else
|
||||
echo "Error initializing EEPROM" ;
|
||||
fi ;
|
||||
else
|
||||
echo "No U-Boot image found on SD card" ;
|
||||
fi
|
|
@ -0,0 +1,58 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Boundary Devices
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not write to the Free Software
|
||||
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
|
||||
* MA 02110-1301 USA
|
||||
*
|
||||
*/
|
||||
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
|
||||
DATA 4, MX6_MMDC_P0_MDCFG0, 0x40435323
|
||||
DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63
|
||||
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
|
||||
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
|
||||
DATA 4, MX6_MMDC_P0_MDOR, 0x00431023
|
||||
DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
|
||||
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
|
||||
DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
|
||||
DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
|
||||
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
|
||||
DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
|
||||
DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
|
||||
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
|
||||
DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
|
||||
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42350231
|
||||
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42350231
|
||||
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021A0218
|
||||
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x021A0218
|
||||
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B4B4E49
|
||||
DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4B4B4E49
|
||||
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3035
|
||||
DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3F3F3035
|
||||
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0040003C
|
||||
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0032003E
|
||||
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0040003C
|
||||
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0032003E
|
||||
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
|
||||
DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
|
||||
DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
|
|
@ -0,0 +1,58 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Boundary Devices
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not write to the Free Software
|
||||
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
|
||||
* MA 02110-1301 USA
|
||||
*
|
||||
*/
|
||||
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
|
||||
DATA 4, MX6_MMDC_P0_MDCFG0, 0x696C5323
|
||||
DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63
|
||||
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
|
||||
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
|
||||
DATA 4, MX6_MMDC_P0_MDOR, 0x006C1023
|
||||
DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
|
||||
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
|
||||
DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
|
||||
DATA 4, MX6_MMDC_P0_MDCTL, 0x84190000
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
|
||||
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
|
||||
DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
|
||||
DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
|
||||
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
|
||||
DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
|
||||
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42350231
|
||||
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021A0218
|
||||
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42350231
|
||||
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x021A0218
|
||||
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B4B4E49
|
||||
DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4B4B4E49
|
||||
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3035
|
||||
DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3F3F3035
|
||||
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0040003C
|
||||
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0032003E
|
||||
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0040003C
|
||||
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0032003E
|
||||
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
|
||||
DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
|
||||
DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
|
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Boundary Devices
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not write to the Free Software
|
||||
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
|
||||
DATA 4, MX6_MMDC_P0_MDCFG0, 0x40435323
|
||||
DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63
|
||||
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
|
||||
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
|
||||
DATA 4, MX6_MMDC_P0_MDOR, 0x00431023
|
||||
DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
|
||||
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
|
||||
DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
|
||||
DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
|
||||
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
|
||||
DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
|
||||
DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
|
||||
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
|
||||
DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
|
||||
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x420F020F
|
||||
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x01760175
|
||||
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x41640171
|
||||
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x015E0160
|
||||
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x45464B4A
|
||||
DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x49484A46
|
||||
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x40402E32
|
||||
DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3A3A3231
|
||||
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x003A003A
|
||||
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0030002F
|
||||
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x002F0038
|
||||
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00270039
|
||||
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
|
||||
DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
|
||||
DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
|
|
@ -0,0 +1,58 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Boundary Devices
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not write to the Free Software
|
||||
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
|
||||
* MA 02110-1301 USA
|
||||
*
|
||||
*/
|
||||
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
|
||||
DATA 4, MX6_MMDC_P0_MDCFG0, 0x696C5323
|
||||
DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8D63
|
||||
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
|
||||
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
|
||||
DATA 4, MX6_MMDC_P0_MDOR, 0x006C1023
|
||||
DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
|
||||
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
|
||||
DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
|
||||
DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
|
||||
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
|
||||
DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
|
||||
DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
|
||||
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
|
||||
DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
|
||||
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42350231
|
||||
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021A0218
|
||||
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42350231
|
||||
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x021A0218
|
||||
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4B4B4E49
|
||||
DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4B4B4E49
|
||||
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3035
|
||||
DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3F3F3035
|
||||
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0040003C
|
||||
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0032003E
|
||||
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0040003C
|
||||
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0032003E
|
||||
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
|
||||
DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
|
||||
DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
|
|
@ -0,0 +1,41 @@
|
|||
#
|
||||
# Copyright (C) 2012-2013, Guennadi Liakhovetski <lg@denx.de>
|
||||
# (C) Copyright 2012-2013 Freescale Semiconductor, Inc.
|
||||
# Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS := nitrogen6x.o
|
||||
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
|
@ -0,0 +1,92 @@
|
|||
U-Boot for the Boundary Devices Nitrogen6X and
|
||||
Freescale i.MX6Q SabreLite boards
|
||||
|
||||
This file contains information for the port of
|
||||
U-Boot to the Boundary Devices Nitrogen6X and
|
||||
Freescale i.MX6Q SabreLite boards.
|
||||
|
||||
1. Boot source, boot from SPI NOR
|
||||
---------------------------------
|
||||
The configuration in this directory supports both the
|
||||
Nitrogen6X and Freescale SabreLite board, but in a
|
||||
different fashion from Freescale's implementation in
|
||||
board/freescale/mx6qsabrelite.
|
||||
|
||||
In particular, this image supports booting from SPI NOR
|
||||
and saving the environment to SPI NOR.
|
||||
|
||||
It does not support 'boot from SD' at offset 0x400
|
||||
except through the 'bmode' command.
|
||||
http://lists.denx.de/pipermail/u-boot/2012-August/131151.html
|
||||
|
||||
2. Boots using 6x_bootscript on SATA or SD card
|
||||
-----------------------------------------------
|
||||
The default bootcmd for these boards is configured
|
||||
to look for and source a boot script named '6x_bootscript'
|
||||
in the root of the first partition of the following
|
||||
devices:
|
||||
|
||||
sata 0
|
||||
mmc 0
|
||||
mmc 1
|
||||
|
||||
They're searched in the order listed above, trying both the
|
||||
ext2 and fat filesystems.
|
||||
|
||||
2. Maintaining the SPI NOR
|
||||
--------------------------
|
||||
A couple of convenience commands
|
||||
|
||||
clearenv - clear environment to factory default
|
||||
upgradeu - look and source a boot script named
|
||||
'6x_upgrade' to upgrade the U-Boot version
|
||||
in SPI NOR. The search is the same as for
|
||||
6x_bootscript described above.
|
||||
|
||||
3. Display support
|
||||
------------------
|
||||
U-Boot support for the following displays is configured by
|
||||
default:
|
||||
|
||||
HDMI - 1024 x 768 for maximum compatibility
|
||||
Hannstar-XGA - 1024 x 768 LVDS (Freescale part number MCIMX-LVDS1)
|
||||
wsvga-lvds - 1024 x 600 LVDS (Boundary p/n Nit6X_1024x600)
|
||||
wvga-rgb - 800 x 480 RGB (Boundary p/n Nit6X_800x480)
|
||||
|
||||
Since the ipuv3_fb display driver currently supports only a single display,
|
||||
this code auto-detects panel by probing the HDMI Phy for Hot Plug Detect
|
||||
or the I2C touch controller of the LVDS and RGB displays in the priority
|
||||
listed above.
|
||||
|
||||
Setting 'panel' environment variable to one of the names above will
|
||||
override auto-detection and force activation of the specified panel.
|
||||
|
||||
4. Building
|
||||
------------
|
||||
|
||||
To build U-Boot for one of the Nitrogen6x or SabreLite board:
|
||||
|
||||
make nitrogen6x_config
|
||||
make u-boot.imx
|
||||
|
||||
Note that 'nitrogen6x' is a placeholder. The complete list of supported
|
||||
board configurations is shown in tha MAINTAINERS file:
|
||||
nitrogen6q i.MX6Q/6D 1GB
|
||||
nitrogen6dl i.MX6DL 1GB
|
||||
nitrogen6s i.MX6S 512MB
|
||||
nitrogen6q2g i.MX6Q/6D 2GB
|
||||
nitrogen6dl2g i.MX6DL 2GB
|
||||
nitrogen6s1g i.MX6S 1GB
|
||||
|
||||
The -6q variants support either the i.MX6Quad or i.MX6Dual processors
|
||||
and are configured for a 64-bit memory bus at 1066 MHz.
|
||||
|
||||
The -6dl variants also use a 64-bit memory bus, operated at 800MHz.
|
||||
|
||||
The -6s variants use a 32-bit memory bus at 800MHz.
|
||||
|
||||
If you place the u-boot.imx into a single-partition SD card
|
||||
along with a binary version of the boot script 6x_upgrade.txt,
|
||||
you can program it using 'upgradeu':
|
||||
|
||||
U-Boot> run upgradeu
|
|
@ -0,0 +1,46 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Boundary Devices
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not write to the Free Software
|
||||
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
|
||||
* MA 02110-1301 USA
|
||||
*
|
||||
* Device Configuration Data (DCD)
|
||||
*
|
||||
* Each entry must have the format:
|
||||
* Addr-type Address Value
|
||||
*
|
||||
* where:
|
||||
* Addr-type register length (1,2 or 4 bytes)
|
||||
* Address absolute address of the register
|
||||
* value value to be stored in the register
|
||||
*/
|
||||
|
||||
/* set the default clock gate to save power */
|
||||
DATA 4, CCM_CCGR0, 0x00C03F3F
|
||||
DATA 4, CCM_CCGR1, 0x0030FC03
|
||||
DATA 4, CCM_CCGR2, 0x0FFFC000
|
||||
DATA 4, CCM_CCGR3, 0x3FF00000
|
||||
DATA 4, CCM_CCGR4, 0x00FFF300
|
||||
DATA 4, CCM_CCGR5, 0x0F0000C3
|
||||
DATA 4, CCM_CCGR6, 0x000003FF
|
||||
|
||||
/* enable AXI cache for VDOA/VPU/IPU */
|
||||
DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
|
||||
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
|
||||
DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
|
||||
DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
|
|
@ -0,0 +1,112 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Boundary Devices
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not write to the Free Software
|
||||
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
|
||||
* MA 02110-1301 USA
|
||||
*
|
||||
* Device Configuration Data (DCD)
|
||||
*
|
||||
* Each entry must have the format:
|
||||
* Addr-type Address Value
|
||||
*
|
||||
* where:
|
||||
* Addr-type register length (1,2 or 4 bytes)
|
||||
* Address absolute address of the register
|
||||
* value value to be stored in the register
|
||||
*/
|
||||
|
||||
/*
|
||||
* DDR3 settings
|
||||
* MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock),
|
||||
* memory bus width: 64 bits x16/x32/x64
|
||||
* MX6DL ddr is limited to 800 MHz(400 MHz clock)
|
||||
* memory bus width: 64 bits x16/x32/x64
|
||||
* MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
|
||||
* memory bus width: 32 bits x16/x32
|
||||
*/
|
||||
DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
|
||||
|
||||
DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
|
||||
/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
|
||||
DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
|
||||
|
||||
DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
|
||||
DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
|
||||
DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
|
||||
DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
|
||||
DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
|
||||
DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
|
||||
DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
|
||||
DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
|
||||
|
||||
DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
|
||||
DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
|
||||
DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
|
||||
DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
|
||||
|
||||
DATA 4, MX6_IOM_DRAM_RESET, 0x000e0030
|
||||
DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
|
||||
DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
|
||||
|
||||
DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
|
||||
DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
|
||||
|
||||
/* (differential input) */
|
||||
DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
|
||||
/* (differential input) */
|
||||
DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
|
||||
/* disable ddr pullups */
|
||||
DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
|
||||
DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
|
||||
/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
|
||||
DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
|
||||
|
||||
/* Read data DQ Byte0-3 delay */
|
||||
DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
|
||||
|
||||
/*
|
||||
* MDMISC mirroring interleaved (row/bank/col)
|
||||
*/
|
||||
DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
|
||||
|
||||
/*
|
||||
* MDSCR con_req
|
||||
*/
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
|
|
@ -0,0 +1,45 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Boundary Devices
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not write to the Free Software
|
||||
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
|
||||
* MA 02110-1301 USA
|
||||
*
|
||||
* Refer docs/README.imxmage for more details about how-to configure
|
||||
* and create imximage boot image
|
||||
*
|
||||
* The syntax is taken as close as possible with the kwbimage
|
||||
*/
|
||||
|
||||
/* image version */
|
||||
IMAGE_VERSION 2
|
||||
|
||||
/*
|
||||
* Boot Device : one of
|
||||
* spi, sd (the board has no nand neither onenand)
|
||||
*/
|
||||
BOOT_FROM sd
|
||||
|
||||
#define __ASSEMBLY__
|
||||
#include <config.h>
|
||||
#include "asm/arch/mx6-ddr.h"
|
||||
#include "asm/arch/iomux.h"
|
||||
#include "asm/arch/crm_regs.h"
|
||||
|
||||
#include "ddr-setup.cfg"
|
||||
#include "800mhz_4x128mx16.cfg"
|
||||
#include "clocks.cfg"
|
|
@ -0,0 +1,45 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Boundary Devices
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not write to the Free Software
|
||||
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
|
||||
* MA 02110-1301 USA
|
||||
*
|
||||
* Refer docs/README.imxmage for more details about how-to configure
|
||||
* and create imximage boot image
|
||||
*
|
||||
* The syntax is taken as close as possible with the kwbimage
|
||||
*/
|
||||
|
||||
/* image version */
|
||||
IMAGE_VERSION 2
|
||||
|
||||
/*
|
||||
* Boot Device : one of
|
||||
* spi, sd (the board has no nand neither onenand)
|
||||
*/
|
||||
BOOT_FROM sd
|
||||
|
||||
#define __ASSEMBLY__
|
||||
#include <config.h>
|
||||
#include "asm/arch/mx6-ddr.h"
|
||||
#include "asm/arch/iomux.h"
|
||||
#include "asm/arch/crm_regs.h"
|
||||
|
||||
#include "ddr-setup.cfg"
|
||||
#include "800mhz_4x256mx16.cfg"
|
||||
#include "clocks.cfg"
|
|
@ -0,0 +1,45 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Boundary Devices
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not write to the Free Software
|
||||
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
|
||||
* MA 02110-1301 USA
|
||||
*
|
||||
* Refer docs/README.imxmage for more details about how-to configure
|
||||
* and create imximage boot image
|
||||
*
|
||||
* The syntax is taken as close as possible with the kwbimage
|
||||
*/
|
||||
|
||||
/* image version */
|
||||
IMAGE_VERSION 2
|
||||
|
||||
/*
|
||||
* Boot Device : one of
|
||||
* spi, sd (the board has no nand neither onenand)
|
||||
*/
|
||||
BOOT_FROM sd
|
||||
|
||||
#define __ASSEMBLY__
|
||||
#include <config.h>
|
||||
#include "asm/arch/mx6-ddr.h"
|
||||
#include "asm/arch/iomux.h"
|
||||
#include "asm/arch/crm_regs.h"
|
||||
|
||||
#include "ddr-setup.cfg"
|
||||
#include "1066mhz_4x128mx16.cfg"
|
||||
#include "clocks.cfg"
|
|
@ -0,0 +1,45 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Boundary Devices
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not write to the Free Software
|
||||
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
|
||||
* MA 02110-1301 USA
|
||||
*
|
||||
* Refer docs/README.imxmage for more details about how-to configure
|
||||
* and create imximage boot image
|
||||
*
|
||||
* The syntax is taken as close as possible with the kwbimage
|
||||
*/
|
||||
|
||||
/* image version */
|
||||
IMAGE_VERSION 2
|
||||
|
||||
/*
|
||||
* Boot Device : one of
|
||||
* spi, sd (the board has no nand neither onenand)
|
||||
*/
|
||||
BOOT_FROM sd
|
||||
|
||||
#define __ASSEMBLY__
|
||||
#include <config.h>
|
||||
#include "asm/arch/mx6-ddr.h"
|
||||
#include "asm/arch/iomux.h"
|
||||
#include "asm/arch/crm_regs.h"
|
||||
|
||||
#include "ddr-setup.cfg"
|
||||
#include "1066mhz_4x256mx16.cfg"
|
||||
#include "clocks.cfg"
|
|
@ -0,0 +1,45 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Boundary Devices
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not write to the Free Software
|
||||
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
|
||||
* MA 02110-1301 USA
|
||||
*
|
||||
* Refer docs/README.imxmage for more details about how-to configure
|
||||
* and create imximage boot image
|
||||
*
|
||||
* The syntax is taken as close as possible with the kwbimage
|
||||
*/
|
||||
|
||||
/* image version */
|
||||
IMAGE_VERSION 2
|
||||
|
||||
/*
|
||||
* Boot Device : one of
|
||||
* spi, sd (the board has no nand neither onenand)
|
||||
*/
|
||||
BOOT_FROM sd
|
||||
|
||||
#define __ASSEMBLY__
|
||||
#include <config.h>
|
||||
#include "asm/arch/mx6-ddr.h"
|
||||
#include "asm/arch/iomux.h"
|
||||
#include "asm/arch/crm_regs.h"
|
||||
|
||||
#include "ddr-setup.cfg"
|
||||
#include "800mhz_2x128mx16.cfg"
|
||||
#include "clocks.cfg"
|
|
@ -0,0 +1,45 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Boundary Devices
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not write to the Free Software
|
||||
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
|
||||
* MA 02110-1301 USA
|
||||
*
|
||||
* Refer docs/README.imxmage for more details about how-to configure
|
||||
* and create imximage boot image
|
||||
*
|
||||
* The syntax is taken as close as possible with the kwbimage
|
||||
*/
|
||||
|
||||
/* image version */
|
||||
IMAGE_VERSION 2
|
||||
|
||||
/*
|
||||
* Boot Device : one of
|
||||
* spi, sd (the board has no nand neither onenand)
|
||||
*/
|
||||
BOOT_FROM sd
|
||||
|
||||
#define __ASSEMBLY__
|
||||
#include <config.h>
|
||||
#include "asm/arch/mx6-ddr.h"
|
||||
#include "asm/arch/iomux.h"
|
||||
#include "asm/arch/crm_regs.h"
|
||||
|
||||
#include "ddr-setup.cfg"
|
||||
#include "800mhz_2x256mx16.cfg"
|
||||
#include "clocks.cfg"
|
|
@ -0,0 +1,895 @@
|
|||
/*
|
||||
* Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
|
||||
* Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <malloc.h>
|
||||
#include <asm/arch/mx6-pins.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/imx-common/iomux-v3.h>
|
||||
#include <asm/imx-common/mxc_i2c.h>
|
||||
#include <asm/imx-common/boot_mode.h>
|
||||
#include <mmc.h>
|
||||
#include <fsl_esdhc.h>
|
||||
#include <micrel.h>
|
||||
#include <miiphy.h>
|
||||
#include <netdev.h>
|
||||
#include <linux/fb.h>
|
||||
#include <ipu_pixfmt.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/arch/mxc_hdmi.h>
|
||||
#include <i2c.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||
|
||||
#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
|
||||
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||
|
||||
#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
|
||||
|
||||
#define SPI_PAD_CTRL (PAD_CTL_HYS | \
|
||||
PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
|
||||
|
||||
#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
|
||||
|
||||
#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
|
||||
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
|
||||
|
||||
#define WEAK_PULLUP (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
|
||||
PAD_CTL_SRE_SLOW)
|
||||
|
||||
#define WEAK_PULLDOWN (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
|
||||
PAD_CTL_SRE_SLOW)
|
||||
|
||||
#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
iomux_v3_cfg_t const uart1_pads[] = {
|
||||
MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t const uart2_pads[] = {
|
||||
MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
|
||||
|
||||
/* I2C1, SGTL5000 */
|
||||
struct i2c_pads_info i2c_pad_info0 = {
|
||||
.scl = {
|
||||
.i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
|
||||
.gpio_mode = MX6_PAD_EIM_D21__GPIO_3_21 | PC,
|
||||
.gp = IMX_GPIO_NR(3, 21)
|
||||
},
|
||||
.sda = {
|
||||
.i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
|
||||
.gpio_mode = MX6_PAD_EIM_D28__GPIO_3_28 | PC,
|
||||
.gp = IMX_GPIO_NR(3, 28)
|
||||
}
|
||||
};
|
||||
|
||||
/* I2C2 Camera, MIPI */
|
||||
struct i2c_pads_info i2c_pad_info1 = {
|
||||
.scl = {
|
||||
.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
|
||||
.gpio_mode = MX6_PAD_KEY_COL3__GPIO_4_12 | PC,
|
||||
.gp = IMX_GPIO_NR(4, 12)
|
||||
},
|
||||
.sda = {
|
||||
.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
|
||||
.gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC,
|
||||
.gp = IMX_GPIO_NR(4, 13)
|
||||
}
|
||||
};
|
||||
|
||||
/* I2C3, J15 - RGB connector */
|
||||
struct i2c_pads_info i2c_pad_info2 = {
|
||||
.scl = {
|
||||
.i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
|
||||
.gpio_mode = MX6_PAD_GPIO_5__GPIO_1_5 | PC,
|
||||
.gp = IMX_GPIO_NR(1, 5)
|
||||
},
|
||||
.sda = {
|
||||
.i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
|
||||
.gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC,
|
||||
.gp = IMX_GPIO_NR(7, 11)
|
||||
}
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t const usdhc3_pads[] = {
|
||||
MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t const usdhc4_pads[] = {
|
||||
MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t const enet_pads1[] = {
|
||||
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
/* pin 35 - 1 (PHY_AD2) on reset */
|
||||
MX6_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
/* pin 32 - 1 - (MODE0) all */
|
||||
MX6_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
/* pin 31 - 1 - (MODE1) all */
|
||||
MX6_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
/* pin 28 - 1 - (MODE2) all */
|
||||
MX6_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
/* pin 27 - 1 - (MODE3) all */
|
||||
MX6_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
|
||||
MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
/* pin 42 PHY nRST */
|
||||
MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_ENET_RXD0__GPIO_1_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t const enet_pads2[] = {
|
||||
MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
};
|
||||
|
||||
/* wl1271 pads on nitrogen6x */
|
||||
iomux_v3_cfg_t const wl12xx_pads[] = {
|
||||
(MX6_PAD_NANDF_CS1__GPIO_6_14 & ~MUX_PAD_CTRL_MASK)
|
||||
| MUX_PAD_CTRL(WEAK_PULLDOWN),
|
||||
(MX6_PAD_NANDF_CS2__GPIO_6_15 & ~MUX_PAD_CTRL_MASK)
|
||||
| MUX_PAD_CTRL(OUTPUT_40OHM),
|
||||
(MX6_PAD_NANDF_CS3__GPIO_6_16 & ~MUX_PAD_CTRL_MASK)
|
||||
| MUX_PAD_CTRL(OUTPUT_40OHM),
|
||||
};
|
||||
#define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14)
|
||||
#define WL12XX_WL_ENABLE_GP IMX_GPIO_NR(6, 15)
|
||||
#define WL12XX_BT_ENABLE_GP IMX_GPIO_NR(6, 16)
|
||||
|
||||
/* Button assignments for J14 */
|
||||
static iomux_v3_cfg_t const button_pads[] = {
|
||||
/* Menu */
|
||||
MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
|
||||
/* Back */
|
||||
MX6_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
|
||||
/* Labelled Search (mapped to Power under Android) */
|
||||
MX6_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
|
||||
/* Home */
|
||||
MX6_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
|
||||
/* Volume Down */
|
||||
MX6_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
|
||||
/* Volume Up */
|
||||
MX6_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void setup_iomux_enet(void)
|
||||
{
|
||||
gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */
|
||||
gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */
|
||||
gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
|
||||
gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
|
||||
gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
|
||||
gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
|
||||
gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
|
||||
imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
|
||||
gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
|
||||
|
||||
/* Need delay 10ms according to KSZ9021 spec */
|
||||
udelay(1000 * 10);
|
||||
gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */
|
||||
gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
|
||||
}
|
||||
|
||||
iomux_v3_cfg_t const usb_pads[] = {
|
||||
MX6_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void setup_iomux_uart(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
|
||||
imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_MX6
|
||||
int board_ehci_hcd_init(int port)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
|
||||
|
||||
/* Reset USB hub */
|
||||
gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
|
||||
mdelay(2);
|
||||
gpio_set_value(IMX_GPIO_NR(7, 12), 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
struct fsl_esdhc_cfg usdhc_cfg[2] = {
|
||||
{USDHC3_BASE_ADDR},
|
||||
{USDHC4_BASE_ADDR},
|
||||
};
|
||||
|
||||
int board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
||||
int ret;
|
||||
|
||||
if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
|
||||
gpio_direction_input(IMX_GPIO_NR(7, 0));
|
||||
ret = !gpio_get_value(IMX_GPIO_NR(7, 0));
|
||||
} else {
|
||||
gpio_direction_input(IMX_GPIO_NR(2, 6));
|
||||
ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
s32 status = 0;
|
||||
u32 index = 0;
|
||||
|
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
||||
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
|
||||
|
||||
for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
|
||||
switch (index) {
|
||||
case 0:
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
|
||||
break;
|
||||
case 1:
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
|
||||
break;
|
||||
default:
|
||||
printf("Warning: you configured more USDHC controllers"
|
||||
"(%d) then supported by the board (%d)\n",
|
||||
index + 1, CONFIG_SYS_FSL_USDHC_NUM);
|
||||
return status;
|
||||
}
|
||||
|
||||
status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
#endif
|
||||
|
||||
u32 get_board_rev(void)
|
||||
{
|
||||
return 0x63000;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MXC_SPI
|
||||
iomux_v3_cfg_t const ecspi1_pads[] = {
|
||||
/* SS1 */
|
||||
MX6_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
};
|
||||
|
||||
void setup_spi(void)
|
||||
{
|
||||
gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
|
||||
imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
|
||||
ARRAY_SIZE(ecspi1_pads));
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
/* min rx data delay */
|
||||
ksz9021_phy_extended_write(phydev,
|
||||
MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
|
||||
/* min tx data delay */
|
||||
ksz9021_phy_extended_write(phydev,
|
||||
MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
|
||||
/* max rx/tx clock delay, min rx/tx control */
|
||||
ksz9021_phy_extended_write(phydev,
|
||||
MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
|
||||
if (phydev->drv->config)
|
||||
phydev->drv->config(phydev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
uint32_t base = IMX_FEC_BASE;
|
||||
struct mii_dev *bus = NULL;
|
||||
struct phy_device *phydev = NULL;
|
||||
int ret;
|
||||
|
||||
setup_iomux_enet();
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
bus = fec_get_miibus(base, -1);
|
||||
if (!bus)
|
||||
return 0;
|
||||
/* scan phy 4,5,6,7 */
|
||||
phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
|
||||
if (!phydev) {
|
||||
free(bus);
|
||||
return 0;
|
||||
}
|
||||
printf("using phy at %d\n", phydev->addr);
|
||||
ret = fec_probe(bis, -1, base, bus, phydev);
|
||||
if (ret) {
|
||||
printf("FEC MXC: %s:failed\n", __func__);
|
||||
free(phydev);
|
||||
free(bus);
|
||||
}
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void setup_buttons(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(button_pads,
|
||||
ARRAY_SIZE(button_pads));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CMD_SATA
|
||||
|
||||
int setup_sata(void)
|
||||
{
|
||||
struct iomuxc_base_regs *const iomuxc_regs
|
||||
= (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
|
||||
int ret = enable_sata_clock();
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
clrsetbits_le32(&iomuxc_regs->gpr[13],
|
||||
IOMUXC_GPR13_SATA_MASK,
|
||||
IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
|
||||
|IOMUXC_GPR13_SATA_PHY_7_SATA2M
|
||||
|IOMUXC_GPR13_SATA_SPEED_3G
|
||||
|(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
|
||||
|IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
|
||||
|IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
|
||||
|IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
|
||||
|IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
|
||||
|IOMUXC_GPR13_SATA_PHY_1_SLOW);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_VIDEO_IPUV3)
|
||||
|
||||
static iomux_v3_cfg_t const backlight_pads[] = {
|
||||
/* Backlight on RGB connector: J15 */
|
||||
MX6_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
#define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
|
||||
|
||||
/* Backlight on LVDS connector: J6 */
|
||||
MX6_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const rgb_pads[] = {
|
||||
MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
|
||||
MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
|
||||
MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2,
|
||||
MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3,
|
||||
MX6_PAD_DI0_PIN4__GPIO_4_20,
|
||||
MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
|
||||
MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
|
||||
MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
|
||||
MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
|
||||
MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
|
||||
MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
|
||||
MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
|
||||
MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
|
||||
MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
|
||||
MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
|
||||
MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
|
||||
MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
|
||||
MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
|
||||
MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
|
||||
MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
|
||||
MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
|
||||
MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
|
||||
MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
|
||||
MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
|
||||
MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
|
||||
MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
|
||||
MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
|
||||
MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
|
||||
MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
|
||||
};
|
||||
|
||||
struct display_info_t {
|
||||
int bus;
|
||||
int addr;
|
||||
int pixfmt;
|
||||
int (*detect)(struct display_info_t const *dev);
|
||||
void (*enable)(struct display_info_t const *dev);
|
||||
struct fb_videomode mode;
|
||||
};
|
||||
|
||||
|
||||
static int detect_hdmi(struct display_info_t const *dev)
|
||||
{
|
||||
struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
|
||||
return readb(&hdmi->phy_stat0) & HDMI_PHY_HPD;
|
||||
}
|
||||
|
||||
static void enable_hdmi(struct display_info_t const *dev)
|
||||
{
|
||||
struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
|
||||
u8 reg;
|
||||
printf("%s: setup HDMI monitor\n", __func__);
|
||||
reg = readb(&hdmi->phy_conf0);
|
||||
reg |= HDMI_PHY_CONF0_PDZ_MASK;
|
||||
writeb(reg, &hdmi->phy_conf0);
|
||||
|
||||
udelay(3000);
|
||||
reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
|
||||
writeb(reg, &hdmi->phy_conf0);
|
||||
udelay(3000);
|
||||
reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
|
||||
writeb(reg, &hdmi->phy_conf0);
|
||||
writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
|
||||
}
|
||||
|
||||
static int detect_i2c(struct display_info_t const *dev)
|
||||
{
|
||||
return ((0 == i2c_set_bus_num(dev->bus))
|
||||
&&
|
||||
(0 == i2c_probe(dev->addr)));
|
||||
}
|
||||
|
||||
static void enable_lvds(struct display_info_t const *dev)
|
||||
{
|
||||
struct iomuxc *iomux = (struct iomuxc *)
|
||||
IOMUXC_BASE_ADDR;
|
||||
u32 reg = readl(&iomux->gpr[2]);
|
||||
reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
|
||||
writel(reg, &iomux->gpr[2]);
|
||||
gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
|
||||
}
|
||||
|
||||
static void enable_rgb(struct display_info_t const *dev)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
rgb_pads,
|
||||
ARRAY_SIZE(rgb_pads));
|
||||
gpio_direction_output(RGB_BACKLIGHT_GP, 1);
|
||||
}
|
||||
|
||||
static struct display_info_t const displays[] = {{
|
||||
.bus = -1,
|
||||
.addr = 0,
|
||||
.pixfmt = IPU_PIX_FMT_RGB24,
|
||||
.detect = detect_hdmi,
|
||||
.enable = enable_hdmi,
|
||||
.mode = {
|
||||
.name = "HDMI",
|
||||
.refresh = 60,
|
||||
.xres = 1024,
|
||||
.yres = 768,
|
||||
.pixclock = 15385,
|
||||
.left_margin = 220,
|
||||
.right_margin = 40,
|
||||
.upper_margin = 21,
|
||||
.lower_margin = 7,
|
||||
.hsync_len = 60,
|
||||
.vsync_len = 10,
|
||||
.sync = FB_SYNC_EXT,
|
||||
.vmode = FB_VMODE_NONINTERLACED
|
||||
} }, {
|
||||
.bus = 2,
|
||||
.addr = 0x4,
|
||||
.pixfmt = IPU_PIX_FMT_LVDS666,
|
||||
.detect = detect_i2c,
|
||||
.enable = enable_lvds,
|
||||
.mode = {
|
||||
.name = "Hannstar-XGA",
|
||||
.refresh = 60,
|
||||
.xres = 1024,
|
||||
.yres = 768,
|
||||
.pixclock = 15385,
|
||||
.left_margin = 220,
|
||||
.right_margin = 40,
|
||||
.upper_margin = 21,
|
||||
.lower_margin = 7,
|
||||
.hsync_len = 60,
|
||||
.vsync_len = 10,
|
||||
.sync = FB_SYNC_EXT,
|
||||
.vmode = FB_VMODE_NONINTERLACED
|
||||
} }, {
|
||||
.bus = 2,
|
||||
.addr = 0x38,
|
||||
.pixfmt = IPU_PIX_FMT_LVDS666,
|
||||
.detect = detect_i2c,
|
||||
.enable = enable_lvds,
|
||||
.mode = {
|
||||
.name = "wsvga-lvds",
|
||||
.refresh = 60,
|
||||
.xres = 1024,
|
||||
.yres = 600,
|
||||
.pixclock = 15385,
|
||||
.left_margin = 220,
|
||||
.right_margin = 40,
|
||||
.upper_margin = 21,
|
||||
.lower_margin = 7,
|
||||
.hsync_len = 60,
|
||||
.vsync_len = 10,
|
||||
.sync = FB_SYNC_EXT,
|
||||
.vmode = FB_VMODE_NONINTERLACED
|
||||
} }, {
|
||||
.bus = 2,
|
||||
.addr = 0x48,
|
||||
.pixfmt = IPU_PIX_FMT_RGB666,
|
||||
.detect = detect_i2c,
|
||||
.enable = enable_rgb,
|
||||
.mode = {
|
||||
.name = "wvga-rgb",
|
||||
.refresh = 57,
|
||||
.xres = 800,
|
||||
.yres = 480,
|
||||
.pixclock = 37037,
|
||||
.left_margin = 40,
|
||||
.right_margin = 60,
|
||||
.upper_margin = 10,
|
||||
.lower_margin = 10,
|
||||
.hsync_len = 20,
|
||||
.vsync_len = 10,
|
||||
.sync = 0,
|
||||
.vmode = FB_VMODE_NONINTERLACED
|
||||
} } };
|
||||
|
||||
int board_video_skip(void)
|
||||
{
|
||||
int i;
|
||||
int ret;
|
||||
char const *panel = getenv("panel");
|
||||
if (!panel) {
|
||||
for (i = 0; i < ARRAY_SIZE(displays); i++) {
|
||||
struct display_info_t const *dev = displays+i;
|
||||
if (dev->detect(dev)) {
|
||||
panel = dev->mode.name;
|
||||
printf("auto-detected panel %s\n", panel);
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!panel) {
|
||||
panel = displays[0].mode.name;
|
||||
printf("No panel detected: default to %s\n", panel);
|
||||
}
|
||||
} else {
|
||||
for (i = 0; i < ARRAY_SIZE(displays); i++) {
|
||||
if (!strcmp(panel, displays[i].mode.name))
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (i < ARRAY_SIZE(displays)) {
|
||||
ret = ipuv3_fb_init(&displays[i].mode, 0,
|
||||
displays[i].pixfmt);
|
||||
if (!ret) {
|
||||
displays[i].enable(displays+i);
|
||||
printf("Display: %s (%ux%u)\n",
|
||||
displays[i].mode.name,
|
||||
displays[i].mode.xres,
|
||||
displays[i].mode.yres);
|
||||
} else
|
||||
printf("LCD %s cannot be configured: %d\n",
|
||||
displays[i].mode.name, ret);
|
||||
} else {
|
||||
printf("unsupported panel %s\n", panel);
|
||||
ret = -EINVAL;
|
||||
}
|
||||
return (0 != ret);
|
||||
}
|
||||
|
||||
static void setup_display(void)
|
||||
{
|
||||
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
|
||||
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
||||
struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
|
||||
|
||||
int reg;
|
||||
|
||||
/* Turn on LDB0,IPU,IPU DI0 clocks */
|
||||
reg = __raw_readl(&mxc_ccm->CCGR3);
|
||||
reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET
|
||||
|MXC_CCM_CCGR3_LDB_DI0_MASK;
|
||||
writel(reg, &mxc_ccm->CCGR3);
|
||||
|
||||
/* Turn on HDMI PHY clock */
|
||||
reg = __raw_readl(&mxc_ccm->CCGR2);
|
||||
reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
|
||||
|MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
|
||||
writel(reg, &mxc_ccm->CCGR2);
|
||||
|
||||
/* clear HDMI PHY reset */
|
||||
writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
|
||||
|
||||
/* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
|
||||
writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
|
||||
writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);
|
||||
|
||||
/* set LDB0, LDB1 clk select to 011/011 */
|
||||
reg = readl(&mxc_ccm->cs2cdr);
|
||||
reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
|
||||
|MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
|
||||
reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
|
||||
|(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
|
||||
writel(reg, &mxc_ccm->cs2cdr);
|
||||
|
||||
reg = readl(&mxc_ccm->cscmr2);
|
||||
reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
|
||||
writel(reg, &mxc_ccm->cscmr2);
|
||||
|
||||
reg = readl(&mxc_ccm->chsccdr);
|
||||
reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
|
||||
|MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
|
||||
|MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
|
||||
reg |= (CHSCCDR_CLK_SEL_LDB_DI0
|
||||
<<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
|
||||
|(CHSCCDR_PODF_DIVIDE_BY_3
|
||||
<<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
|
||||
|(CHSCCDR_IPU_PRE_CLK_540M_PFD
|
||||
<<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
|
||||
writel(reg, &mxc_ccm->chsccdr);
|
||||
|
||||
reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
|
||||
|IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
|
||||
|IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
|
||||
|IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
|
||||
|IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
|
||||
|IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
|
||||
|IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
|
||||
|IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
|
||||
|IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
|
||||
writel(reg, &iomux->gpr[2]);
|
||||
|
||||
reg = readl(&iomux->gpr[3]);
|
||||
reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
|
||||
| (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
|
||||
<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
|
||||
writel(reg, &iomux->gpr[3]);
|
||||
|
||||
/* backlights off until needed */
|
||||
imx_iomux_v3_setup_multiple_pads(backlight_pads,
|
||||
ARRAY_SIZE(backlight_pads));
|
||||
gpio_direction_input(LVDS_BACKLIGHT_GP);
|
||||
gpio_direction_input(RGB_BACKLIGHT_GP);
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
setup_iomux_uart();
|
||||
|
||||
/* Disable wl1271 For Nitrogen6w */
|
||||
gpio_direction_input(WL12XX_WL_IRQ_GP);
|
||||
gpio_direction_output(WL12XX_WL_ENABLE_GP, 0);
|
||||
gpio_direction_output(WL12XX_BT_ENABLE_GP, 0);
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads));
|
||||
setup_buttons();
|
||||
|
||||
#if defined(CONFIG_VIDEO_IPUV3)
|
||||
setup_display();
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Do not overwrite the console
|
||||
* Use always serial for U-Boot console
|
||||
*/
|
||||
int overwrite_console(void)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
||||
|
||||
#ifdef CONFIG_MXC_SPI
|
||||
setup_spi();
|
||||
#endif
|
||||
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
|
||||
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
|
||||
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
|
||||
|
||||
#ifdef CONFIG_CMD_SATA
|
||||
setup_sata();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
if (gpio_get_value(WL12XX_WL_IRQ_GP))
|
||||
puts("Board: Nitrogen6X\n");
|
||||
else
|
||||
puts("Board: SABRE Lite\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct button_key {
|
||||
char const *name;
|
||||
unsigned gpnum;
|
||||
char ident;
|
||||
};
|
||||
|
||||
static struct button_key const buttons[] = {
|
||||
{"back", IMX_GPIO_NR(2, 2), 'B'},
|
||||
{"home", IMX_GPIO_NR(2, 4), 'H'},
|
||||
{"menu", IMX_GPIO_NR(2, 1), 'M'},
|
||||
{"search", IMX_GPIO_NR(2, 3), 'S'},
|
||||
{"volup", IMX_GPIO_NR(7, 13), 'V'},
|
||||
{"voldown", IMX_GPIO_NR(4, 5), 'v'},
|
||||
};
|
||||
|
||||
/*
|
||||
* generate a null-terminated string containing the buttons pressed
|
||||
* returns number of keys pressed
|
||||
*/
|
||||
static int read_keys(char *buf)
|
||||
{
|
||||
int i, numpressed = 0;
|
||||
for (i = 0; i < ARRAY_SIZE(buttons); i++) {
|
||||
if (!gpio_get_value(buttons[i].gpnum))
|
||||
buf[numpressed++] = buttons[i].ident;
|
||||
}
|
||||
buf[numpressed] = '\0';
|
||||
return numpressed;
|
||||
}
|
||||
|
||||
static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
char envvalue[ARRAY_SIZE(buttons)+1];
|
||||
int numpressed = read_keys(envvalue);
|
||||
setenv("keybd", envvalue);
|
||||
return numpressed == 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
kbd, 1, 1, do_kbd,
|
||||
"Tests for keypresses, sets 'keybd' environment variable",
|
||||
"Returns 0 (true) to shell if key is pressed."
|
||||
);
|
||||
|
||||
#ifdef CONFIG_PREBOOT
|
||||
static char const kbd_magic_prefix[] = "key_magic";
|
||||
static char const kbd_command_prefix[] = "key_cmd";
|
||||
|
||||
static void preboot_keys(void)
|
||||
{
|
||||
int numpressed;
|
||||
char keypress[ARRAY_SIZE(buttons)+1];
|
||||
numpressed = read_keys(keypress);
|
||||
if (numpressed) {
|
||||
char *kbd_magic_keys = getenv("magic_keys");
|
||||
char *suffix;
|
||||
/*
|
||||
* loop over all magic keys
|
||||
*/
|
||||
for (suffix = kbd_magic_keys; *suffix; ++suffix) {
|
||||
char *keys;
|
||||
char magic[sizeof(kbd_magic_prefix) + 1];
|
||||
sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
|
||||
keys = getenv(magic);
|
||||
if (keys) {
|
||||
if (!strcmp(keys, keypress))
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (*suffix) {
|
||||
char cmd_name[sizeof(kbd_command_prefix) + 1];
|
||||
char *cmd;
|
||||
sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
|
||||
cmd = getenv(cmd_name);
|
||||
if (cmd) {
|
||||
setenv("preboot", cmd);
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
static const struct boot_mode board_boot_modes[] = {
|
||||
/* 4 bit bus width */
|
||||
{"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
|
||||
{"mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
|
||||
{NULL, 0},
|
||||
};
|
||||
#endif
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
#ifdef CONFIG_PREBOOT
|
||||
preboot_keys();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
add_board_boot_modes(board_boot_modes);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
|
@ -57,6 +57,10 @@ int board_early_init_f(void)
|
|||
mxs_iomux_setup_pad(MX28_PAD_AUART3_TX__GPIO_3_13 |
|
||||
MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP);
|
||||
gpio_direction_output(MX28_PAD_AUART3_TX__GPIO_3_13, 0);
|
||||
|
||||
mxs_iomux_setup_pad(MX28_PAD_AUART3_RX__GPIO_3_12 |
|
||||
MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP);
|
||||
gpio_direction_output(MX28_PAD_AUART3_RX__GPIO_3_12, 0);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
|
|
|
@ -109,12 +109,12 @@ DATA 4 0x021b4828 0x33333333
|
|||
DATA 4 0x021b0018 0x00081740
|
||||
|
||||
DATA 4 0x021b001c 0x00008000
|
||||
DATA 4 0x021b000c 0x555A7975
|
||||
DATA 4 0x021b0010 0xFF538E64
|
||||
DATA 4 0x021b000c 0x555A7974
|
||||
DATA 4 0x021b0010 0xDB538F64
|
||||
DATA 4 0x021b0014 0x01FF00DB
|
||||
DATA 4 0x021b002c 0x000026D2
|
||||
|
||||
DATA 4 0x021b0030 0x005B0E21
|
||||
DATA 4 0x021b0030 0x005A1023
|
||||
DATA 4 0x021b0008 0x09444040
|
||||
DATA 4 0x021b0004 0x00025576
|
||||
DATA 4 0x021b0040 0x00000027
|
||||
|
@ -126,8 +126,8 @@ DATA 4 0x021b001c 0x00008033
|
|||
DATA 4 0x021b001c 0x0000803B
|
||||
DATA 4 0x021b001c 0x00428031
|
||||
DATA 4 0x021b001c 0x00428039
|
||||
DATA 4 0x021b001c 0x09408030
|
||||
DATA 4 0x021b001c 0x09408038
|
||||
DATA 4 0x021b001c 0x19308030
|
||||
DATA 4 0x021b001c 0x19308038
|
||||
|
||||
DATA 4 0x021b001c 0x04008040
|
||||
DATA 4 0x021b001c 0x04008048
|
||||
|
|
|
@ -98,6 +98,16 @@ const iomux_cfg_t iomux_setup[] = {
|
|||
(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
|
||||
};
|
||||
|
||||
#define HW_DRAM_CTL14 (0x38 >> 2)
|
||||
#define CS_MAP 0x3
|
||||
#define INTAREF 0x2
|
||||
#define HW_DRAM_CTL14_CONFIG (INTAREF << 8 | CS_MAP)
|
||||
|
||||
void mxs_adjust_memory_params(uint32_t *dram_vals)
|
||||
{
|
||||
dram_vals[HW_DRAM_CTL14] = HW_DRAM_CTL14_CONFIG;
|
||||
}
|
||||
|
||||
void board_init_ll(void)
|
||||
{
|
||||
mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
|
||||
|
|
|
@ -23,7 +23,7 @@
|
|||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/mx6x_pins.h>
|
||||
#include <asm/arch/mx6q_pins.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/gpio.h>
|
||||
|
@ -55,53 +55,53 @@ int dram_init(void)
|
|||
}
|
||||
|
||||
iomux_v3_cfg_t const uart4_pads[] = {
|
||||
MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t const usdhc3_pads[] = {
|
||||
MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_NANDF_CS0__GPIO_6_11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
|
||||
MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NANDF_CS0__GPIO_6_11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t const usdhc4_pads[] = {
|
||||
MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t const enet_pads[] = {
|
||||
MX6Q_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
};
|
||||
|
||||
|
||||
|
|
|
@ -22,7 +22,7 @@
|
|||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <asm/arch/mx6x_pins.h>
|
||||
#include <asm/arch/mx6q_pins.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/imx-common/iomux-v3.h>
|
||||
|
@ -54,26 +54,26 @@ int dram_init(void)
|
|||
}
|
||||
|
||||
iomux_v3_cfg_t const uart4_pads[] = {
|
||||
MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t const enet_pads[] = {
|
||||
MX6Q_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void setup_iomux_enet(void)
|
||||
|
@ -82,18 +82,18 @@ static void setup_iomux_enet(void)
|
|||
}
|
||||
|
||||
iomux_v3_cfg_t const usdhc3_pads[] = {
|
||||
MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_NANDF_CS2__GPIO_6_15 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NANDF_CS2__GPIO_6_15 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void setup_iomux_uart(void)
|
||||
|
|
|
@ -25,7 +25,7 @@
|
|||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <asm/arch/mx6x_pins.h>
|
||||
#include <asm/arch/mx6q_pins.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/imx-common/iomux-v3.h>
|
||||
|
@ -46,12 +46,12 @@
|
|||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||
|
||||
#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
|
||||
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||
PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
|
||||
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||
|
||||
#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||
|
@ -72,19 +72,19 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
|
||||
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
|
||||
|
||||
return 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
iomux_v3_cfg_t const uart1_pads[] = {
|
||||
MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t const uart2_pads[] = {
|
||||
MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
|
||||
|
@ -92,13 +92,13 @@ iomux_v3_cfg_t const uart2_pads[] = {
|
|||
/* I2C1, SGTL5000 */
|
||||
struct i2c_pads_info i2c_pad_info0 = {
|
||||
.scl = {
|
||||
.i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
|
||||
.gpio_mode = MX6Q_PAD_EIM_D21__GPIO_3_21 | PC,
|
||||
.i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
|
||||
.gpio_mode = MX6_PAD_EIM_D21__GPIO_3_21 | PC,
|
||||
.gp = IMX_GPIO_NR(3, 21)
|
||||
},
|
||||
.sda = {
|
||||
.i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
|
||||
.gpio_mode = MX6Q_PAD_EIM_D28__GPIO_3_28 | PC,
|
||||
.i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
|
||||
.gpio_mode = MX6_PAD_EIM_D28__GPIO_3_28 | PC,
|
||||
.gp = IMX_GPIO_NR(3, 28)
|
||||
}
|
||||
};
|
||||
|
@ -106,13 +106,13 @@ struct i2c_pads_info i2c_pad_info0 = {
|
|||
/* I2C2 Camera, MIPI */
|
||||
struct i2c_pads_info i2c_pad_info1 = {
|
||||
.scl = {
|
||||
.i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
|
||||
.gpio_mode = MX6Q_PAD_KEY_COL3__GPIO_4_12 | PC,
|
||||
.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
|
||||
.gpio_mode = MX6_PAD_KEY_COL3__GPIO_4_12 | PC,
|
||||
.gp = IMX_GPIO_NR(4, 12)
|
||||
},
|
||||
.sda = {
|
||||
.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
|
||||
.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO_4_13 | PC,
|
||||
.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
|
||||
.gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC,
|
||||
.gp = IMX_GPIO_NR(4, 13)
|
||||
}
|
||||
};
|
||||
|
@ -120,86 +120,86 @@ struct i2c_pads_info i2c_pad_info1 = {
|
|||
/* I2C3, J15 - RGB connector */
|
||||
struct i2c_pads_info i2c_pad_info2 = {
|
||||
.scl = {
|
||||
.i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL | PC,
|
||||
.gpio_mode = MX6Q_PAD_GPIO_5__GPIO_1_5 | PC,
|
||||
.i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
|
||||
.gpio_mode = MX6_PAD_GPIO_5__GPIO_1_5 | PC,
|
||||
.gp = IMX_GPIO_NR(1, 5)
|
||||
},
|
||||
.sda = {
|
||||
.i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA | PC,
|
||||
.gpio_mode = MX6Q_PAD_GPIO_16__GPIO_7_11 | PC,
|
||||
.i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
|
||||
.gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC,
|
||||
.gp = IMX_GPIO_NR(7, 11)
|
||||
}
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t const usdhc3_pads[] = {
|
||||
MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
|
||||
MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t const usdhc4_pads[] = {
|
||||
MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
|
||||
MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t const enet_pads1[] = {
|
||||
MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
/* pin 35 - 1 (PHY_AD2) on reset */
|
||||
MX6Q_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
/* pin 32 - 1 - (MODE0) all */
|
||||
MX6Q_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
/* pin 31 - 1 - (MODE1) all */
|
||||
MX6Q_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
/* pin 28 - 1 - (MODE2) all */
|
||||
MX6Q_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
/* pin 27 - 1 - (MODE3) all */
|
||||
MX6Q_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
|
||||
MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
/* pin 42 PHY nRST */
|
||||
MX6Q_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t const enet_pads2[] = {
|
||||
MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
};
|
||||
|
||||
/* Button assignments for J14 */
|
||||
static iomux_v3_cfg_t const button_pads[] = {
|
||||
/* Menu */
|
||||
MX6Q_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
|
||||
MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
|
||||
/* Back */
|
||||
MX6Q_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
|
||||
MX6_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
|
||||
/* Labelled Search (mapped to Power under Android) */
|
||||
MX6Q_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
|
||||
MX6_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
|
||||
/* Home */
|
||||
MX6Q_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
|
||||
MX6_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
|
||||
/* Volume Down */
|
||||
MX6Q_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
|
||||
MX6_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
|
||||
/* Volume Up */
|
||||
MX6Q_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
|
||||
MX6_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void setup_iomux_enet(void)
|
||||
|
@ -221,13 +221,13 @@ static void setup_iomux_enet(void)
|
|||
}
|
||||
|
||||
iomux_v3_cfg_t const usb_pads[] = {
|
||||
MX6Q_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void setup_iomux_uart(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
|
||||
imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
|
||||
imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_MX6
|
||||
|
@ -246,55 +246,55 @@ int board_ehci_hcd_init(int port)
|
|||
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
struct fsl_esdhc_cfg usdhc_cfg[2] = {
|
||||
{USDHC3_BASE_ADDR},
|
||||
{USDHC4_BASE_ADDR},
|
||||
{USDHC3_BASE_ADDR},
|
||||
{USDHC4_BASE_ADDR},
|
||||
};
|
||||
|
||||
int board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
||||
int ret;
|
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
||||
int ret;
|
||||
|
||||
if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
|
||||
if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
|
||||
gpio_direction_input(IMX_GPIO_NR(7, 0));
|
||||
ret = !gpio_get_value(IMX_GPIO_NR(7, 0));
|
||||
} else {
|
||||
} else {
|
||||
gpio_direction_input(IMX_GPIO_NR(2, 6));
|
||||
ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
return ret;
|
||||
}
|
||||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
s32 status = 0;
|
||||
u32 index = 0;
|
||||
s32 status = 0;
|
||||
u32 index = 0;
|
||||
|
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
||||
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
|
||||
|
||||
for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
|
||||
switch (index) {
|
||||
case 0:
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
|
||||
break;
|
||||
case 1:
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
|
||||
for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
|
||||
switch (index) {
|
||||
case 0:
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
|
||||
break;
|
||||
case 1:
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
|
||||
break;
|
||||
default:
|
||||
printf("Warning: you configured more USDHC controllers"
|
||||
printf("Warning: you configured more USDHC controllers"
|
||||
"(%d) then supported by the board (%d)\n",
|
||||
index + 1, CONFIG_SYS_FSL_USDHC_NUM);
|
||||
return status;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
|
||||
}
|
||||
status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
|
||||
}
|
||||
|
||||
return status;
|
||||
return status;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
@ -306,10 +306,10 @@ u32 get_board_rev(void)
|
|||
#ifdef CONFIG_MXC_SPI
|
||||
iomux_v3_cfg_t const ecspi1_pads[] = {
|
||||
/* SS1 */
|
||||
MX6Q_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
MX6_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
};
|
||||
|
||||
void setup_spi(void)
|
||||
|
@ -403,44 +403,44 @@ int setup_sata(void)
|
|||
|
||||
static iomux_v3_cfg_t const backlight_pads[] = {
|
||||
/* Backlight on RGB connector: J15 */
|
||||
MX6Q_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
#define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
|
||||
|
||||
/* Backlight on LVDS connector: J6 */
|
||||
MX6Q_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const rgb_pads[] = {
|
||||
MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
|
||||
MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15,
|
||||
MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2,
|
||||
MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3,
|
||||
MX6Q_PAD_DI0_PIN4__GPIO_4_20,
|
||||
MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
|
||||
MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
|
||||
MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
|
||||
MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
|
||||
MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
|
||||
MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
|
||||
MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
|
||||
MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
|
||||
MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
|
||||
MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
|
||||
MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
|
||||
MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
|
||||
MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
|
||||
MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
|
||||
MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
|
||||
MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
|
||||
MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
|
||||
MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
|
||||
MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
|
||||
MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
|
||||
MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
|
||||
MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
|
||||
MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
|
||||
MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
|
||||
MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
|
||||
MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
|
||||
MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2,
|
||||
MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3,
|
||||
MX6_PAD_DI0_PIN4__GPIO_4_20,
|
||||
MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
|
||||
MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
|
||||
MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
|
||||
MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
|
||||
MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
|
||||
MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
|
||||
MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
|
||||
MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
|
||||
MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
|
||||
MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
|
||||
MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
|
||||
MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
|
||||
MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
|
||||
MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
|
||||
MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
|
||||
MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
|
||||
MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
|
||||
MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
|
||||
MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
|
||||
MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
|
||||
MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
|
||||
MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
|
||||
MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
|
||||
MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
|
||||
};
|
||||
|
||||
struct display_info_t {
|
||||
|
@ -455,32 +455,26 @@ struct display_info_t {
|
|||
|
||||
static int detect_hdmi(struct display_info_t const *dev)
|
||||
{
|
||||
return __raw_readb(HDMI_ARB_BASE_ADDR+HDMI_PHY_STAT0) & HDMI_PHY_HPD;
|
||||
struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
|
||||
return readb(&hdmi->phy_stat0) & HDMI_PHY_HPD;
|
||||
}
|
||||
|
||||
static void enable_hdmi(struct display_info_t const *dev)
|
||||
{
|
||||
struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
|
||||
u8 reg;
|
||||
printf("%s: setup HDMI monitor\n", __func__);
|
||||
reg = __raw_readb(
|
||||
HDMI_ARB_BASE_ADDR
|
||||
+HDMI_PHY_CONF0);
|
||||
reg = readb(&hdmi->phy_conf0);
|
||||
reg |= HDMI_PHY_CONF0_PDZ_MASK;
|
||||
__raw_writeb(reg,
|
||||
HDMI_ARB_BASE_ADDR
|
||||
+HDMI_PHY_CONF0);
|
||||
writeb(reg, &hdmi->phy_conf0);
|
||||
|
||||
udelay(3000);
|
||||
reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
|
||||
__raw_writeb(reg,
|
||||
HDMI_ARB_BASE_ADDR
|
||||
+HDMI_PHY_CONF0);
|
||||
writeb(reg, &hdmi->phy_conf0);
|
||||
udelay(3000);
|
||||
reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
|
||||
__raw_writeb(reg,
|
||||
HDMI_ARB_BASE_ADDR
|
||||
+HDMI_PHY_CONF0);
|
||||
__raw_writeb(HDMI_MC_PHYRSTZ_ASSERT,
|
||||
HDMI_ARB_BASE_ADDR+HDMI_MC_PHYRSTZ);
|
||||
writeb(reg, &hdmi->phy_conf0);
|
||||
writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
|
||||
}
|
||||
|
||||
static int detect_i2c(struct display_info_t const *dev)
|
||||
|
@ -638,6 +632,7 @@ static void setup_display(void)
|
|||
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
|
||||
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
||||
struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
|
||||
|
||||
int reg;
|
||||
|
||||
|
@ -654,8 +649,7 @@ static void setup_display(void)
|
|||
writel(reg, &mxc_ccm->CCGR2);
|
||||
|
||||
/* clear HDMI PHY reset */
|
||||
__raw_writeb(HDMI_MC_PHYRSTZ_DEASSERT,
|
||||
HDMI_ARB_BASE_ADDR+HDMI_MC_PHYRSTZ);
|
||||
writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
|
||||
|
||||
/* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
|
||||
writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
|
||||
|
@ -732,8 +726,8 @@ int overwrite_console(void)
|
|||
|
||||
int board_init(void)
|
||||
{
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
||||
|
||||
#ifdef CONFIG_MXC_SPI
|
||||
setup_spi();
|
||||
|
@ -746,14 +740,14 @@ int board_init(void)
|
|||
setup_sata();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: MX6Q-Sabre Lite\n");
|
||||
puts("Board: MX6Q-Sabre Lite\n");
|
||||
|
||||
return 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct button_key {
|
||||
|
|
|
@ -22,7 +22,7 @@
|
|||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <asm/arch/mx6x_pins.h>
|
||||
#include <asm/arch/mx6q_pins.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/imx-common/iomux-v3.h>
|
||||
|
@ -52,28 +52,28 @@ int dram_init(void)
|
|||
}
|
||||
|
||||
iomux_v3_cfg_t const uart1_pads[] = {
|
||||
MX6Q_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6Q_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t const enet_pads[] = {
|
||||
MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
/* AR8031 PHY Reset */
|
||||
MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_ENET_CRS_DV__GPIO_1_25 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void setup_iomux_enet(void)
|
||||
|
@ -87,44 +87,44 @@ static void setup_iomux_enet(void)
|
|||
}
|
||||
|
||||
iomux_v3_cfg_t const usdhc2_pads[] = {
|
||||
MX6Q_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
|
||||
MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t const usdhc3_pads[] = {
|
||||
MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_NANDF_D0__GPIO_2_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
|
||||
MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_NANDF_D0__GPIO_2_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t const usdhc4_pads[] = {
|
||||
MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void setup_iomux_uart(void)
|
||||
|
|
|
@ -23,11 +23,15 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/iomux-mx23.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#ifdef CONFIG_STATUS_LED
|
||||
#include <status_led.h>
|
||||
#endif
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
@ -42,6 +46,11 @@ int board_early_init_f(void)
|
|||
/* SSP0 clock at 96MHz */
|
||||
mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
|
||||
|
||||
#ifdef CONFIG_CMD_USB
|
||||
/* Enable LAN9512 */
|
||||
gpio_direction_output(MX23_PAD_GPMI_ALE__GPIO_0_17, 1);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -67,5 +76,9 @@ int board_init(void)
|
|||
/* Adress of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
|
||||
|
||||
#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
|
||||
status_led_set(STATUS_LED_BOOT, STATUS_LED_STATE);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -84,6 +84,10 @@ const iomux_cfg_t iomux_setup[] = {
|
|||
MX23_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
|
||||
MX23_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
|
||||
|
||||
/* Green LED */
|
||||
MX23_PAD_SSP1_DETECT__GPIO_2_1 |
|
||||
(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL),
|
||||
|
||||
/* MMC 0 */
|
||||
MX23_PAD_SSP1_CMD__SSP1_CMD | MUX_CONFIG_SSP,
|
||||
MX23_PAD_SSP1_DATA0__SSP1_DATA0 | MUX_CONFIG_SSP,
|
||||
|
@ -91,6 +95,10 @@ const iomux_cfg_t iomux_setup[] = {
|
|||
MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP,
|
||||
MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP,
|
||||
MX23_PAD_SSP1_SCK__SSP1_SCK | MUX_CONFIG_SSP,
|
||||
|
||||
/* Ethernet */
|
||||
MX23_PAD_GPMI_ALE__GPIO_0_17 |
|
||||
(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
|
||||
};
|
||||
|
||||
void board_init_ll(void)
|
||||
|
|
|
@ -257,6 +257,12 @@ mx6qsabreauto arm armv7 mx6qsabreauto freesca
|
|||
mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
|
||||
mx6qsabresd arm armv7 mx6qsabresd freescale mx6 mx6qsabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
|
||||
eco5pk arm armv7 eco5pk 8dtech omap3
|
||||
nitrogen6dl arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024
|
||||
nitrogen6dl2g arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048
|
||||
nitrogen6q arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024
|
||||
nitrogen6q2g arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048
|
||||
nitrogen6s arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512
|
||||
nitrogen6s1g arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024
|
||||
cm_t35 arm armv7 cm_t35 - omap3
|
||||
omap3_overo arm armv7 overo - omap3
|
||||
omap3_pandora arm armv7 pandora - omap3
|
||||
|
|
|
@ -110,13 +110,15 @@ int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
|||
if (led_commands[i].on)
|
||||
led_commands[i].on();
|
||||
else
|
||||
__led_set(led_commands[i].mask, STATUS_LED_ON);
|
||||
__led_set(led_commands[i].mask,
|
||||
STATUS_LED_ON);
|
||||
break;
|
||||
case LED_OFF:
|
||||
if (led_commands[i].off)
|
||||
led_commands[i].off();
|
||||
else
|
||||
__led_set(led_commands[i].mask, STATUS_LED_OFF);
|
||||
__led_set(led_commands[i].mask,
|
||||
STATUS_LED_OFF);
|
||||
break;
|
||||
case LED_TOGGLE:
|
||||
if (led_commands[i].toggle)
|
||||
|
|
|
@ -196,7 +196,7 @@ static int do_sata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
|||
U_BOOT_CMD(
|
||||
sata, 5, 1, do_sata,
|
||||
"SATA sub system",
|
||||
"sata init - init SATA sub system\n"
|
||||
"init - init SATA sub system\n"
|
||||
"sata info - show available SATA devices\n"
|
||||
"sata device [dev] - show or set current device\n"
|
||||
"sata part [dev] - print partition table\n"
|
||||
|
|
|
@ -53,12 +53,6 @@ struct mxsmmc_priv {
|
|||
struct mxs_dma_desc *desc;
|
||||
};
|
||||
|
||||
#if defined(CONFIG_MX23)
|
||||
static const unsigned int mxsmmc_id_offset = 1;
|
||||
#elif defined(CONFIG_MX28)
|
||||
static const unsigned int mxsmmc_id_offset = 0;
|
||||
#endif
|
||||
|
||||
#define MXSMMC_MAX_TIMEOUT 10000
|
||||
#define MXSMMC_SMALL_TRANSFER 512
|
||||
|
||||
|
@ -137,7 +131,7 @@ static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data)
|
|||
priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
|
||||
(data_count << MXS_DMA_DESC_BYTES_OFFSET);
|
||||
|
||||
dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id + mxsmmc_id_offset;
|
||||
dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id;
|
||||
mxs_dma_desc_append(dmach, priv->desc);
|
||||
if (mxs_dma_go(dmach)) {
|
||||
bounce_buffer_stop(&bbstate);
|
||||
|
@ -390,15 +384,9 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int))
|
|||
struct mmc *mmc = NULL;
|
||||
struct mxsmmc_priv *priv = NULL;
|
||||
int ret;
|
||||
#if defined(CONFIG_MX23)
|
||||
const unsigned int mxsmmc_max_id = 2;
|
||||
const unsigned int mxsmmc_clk_id = 0;
|
||||
#elif defined(CONFIG_MX28)
|
||||
const unsigned int mxsmmc_max_id = 4;
|
||||
const unsigned int mxsmmc_clk_id = id;
|
||||
#endif
|
||||
const unsigned int mxsmmc_clk_id = mxs_ssp_clock_by_bus(id);
|
||||
|
||||
if (id >= mxsmmc_max_id)
|
||||
if (!mxs_ssp_bus_id_valid(id))
|
||||
return -ENODEV;
|
||||
|
||||
mmc = malloc(sizeof(struct mmc));
|
||||
|
@ -418,7 +406,7 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int))
|
|||
return -ENOMEM;
|
||||
}
|
||||
|
||||
ret = mxs_dma_init_channel(id + mxsmmc_id_offset);
|
||||
ret = mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + id);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
|
@ -40,17 +40,6 @@
|
|||
|
||||
#define MXSSSP_SMALL_TRANSFER 512
|
||||
|
||||
/*
|
||||
* CONFIG_MXS_SPI_DMA_ENABLE: Experimental mixed PIO/DMA support for MXS SPI
|
||||
* host. Use with utmost caution!
|
||||
*
|
||||
* Enabling this is not yet recommended since this
|
||||
* still doesn't support transfers to/from unaligned
|
||||
* addresses. Therefore this driver will not work
|
||||
* for example with saving environment. This is
|
||||
* caused by DMA alignment constraints on MXS.
|
||||
*/
|
||||
|
||||
struct mxs_spi_slave {
|
||||
struct spi_slave slave;
|
||||
uint32_t max_khz;
|
||||
|
@ -70,7 +59,7 @@ void spi_init(void)
|
|||
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
|
||||
{
|
||||
/* MXS SPI: 4 ports and 3 chip selects maximum */
|
||||
if (bus > 3 || cs > 2)
|
||||
if (!mxs_ssp_bus_id_valid(bus) || cs > 2)
|
||||
return 0;
|
||||
else
|
||||
return 1;
|
||||
|
@ -92,7 +81,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
|
|||
if (!mxs_slave)
|
||||
return NULL;
|
||||
|
||||
if (mxs_dma_init_channel(bus))
|
||||
if (mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + bus))
|
||||
goto err_init;
|
||||
|
||||
mxs_slave->slave.bus = bus;
|
||||
|
@ -168,7 +157,12 @@ static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave,
|
|||
|
||||
while (length--) {
|
||||
/* We transfer 1 byte */
|
||||
#if defined(CONFIG_MX23)
|
||||
writel(SSP_CTRL0_XFER_COUNT_MASK, &ssp_regs->hw_ssp_ctrl0_clr);
|
||||
writel(1, &ssp_regs->hw_ssp_ctrl0_set);
|
||||
#elif defined(CONFIG_MX28)
|
||||
writel(1, &ssp_regs->hw_ssp_xfer_size);
|
||||
#endif
|
||||
|
||||
if ((flags & SPI_XFER_END) && !length)
|
||||
mxs_spi_end_xfer(ssp_regs);
|
||||
|
@ -226,6 +220,12 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
|
|||
int tl;
|
||||
int ret = 0;
|
||||
|
||||
#if defined(CONFIG_MX23)
|
||||
const int mxs_spi_pio_words = 1;
|
||||
#elif defined(CONFIG_MX28)
|
||||
const int mxs_spi_pio_words = 4;
|
||||
#endif
|
||||
|
||||
ALLOC_CACHE_ALIGN_BUFFER(struct mxs_dma_desc, desc, desc_count);
|
||||
|
||||
memset(desc, 0, sizeof(struct mxs_dma_desc) * desc_count);
|
||||
|
@ -281,7 +281,7 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
|
|||
|
||||
dp->cmd.data |=
|
||||
((tl & 0xffff) << MXS_DMA_DESC_BYTES_OFFSET) |
|
||||
(4 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
|
||||
(mxs_spi_pio_words << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
|
||||
MXS_DMA_DESC_HALT_ON_TERMINATE |
|
||||
MXS_DMA_DESC_TERMINATE_FLUSH;
|
||||
|
||||
|
@ -298,15 +298,19 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
|
|||
}
|
||||
|
||||
/*
|
||||
* Write CTRL0, CMD0, CMD1, XFER_SIZE registers. It is
|
||||
* Write CTRL0, CMD0, CMD1 and XFER_SIZE registers in
|
||||
* case of MX28, write only CTRL0 in case of MX23 due
|
||||
* to the difference in register layout. It is utterly
|
||||
* essential that the XFER_SIZE register is written on
|
||||
* a per-descriptor basis with the same size as is the
|
||||
* descriptor!
|
||||
*/
|
||||
dp->cmd.pio_words[0] = ctrl0;
|
||||
#ifdef CONFIG_MX28
|
||||
dp->cmd.pio_words[1] = 0;
|
||||
dp->cmd.pio_words[2] = 0;
|
||||
dp->cmd.pio_words[3] = tl;
|
||||
#endif
|
||||
|
||||
mxs_dma_desc_append(dmach, dp);
|
||||
|
||||
|
@ -332,12 +336,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
|
|||
char dummy;
|
||||
int write = 0;
|
||||
char *data = NULL;
|
||||
|
||||
#ifdef CONFIG_MXS_SPI_DMA_ENABLE
|
||||
int dma = 1;
|
||||
#else
|
||||
int dma = 0;
|
||||
#endif
|
||||
|
||||
if (bitlen == 0) {
|
||||
if (flags & SPI_XFER_END) {
|
||||
|
|
|
@ -21,7 +21,6 @@
|
|||
#include <asm/io.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/mx6x_pins.h>
|
||||
#include <asm/imx-common/iomux-v3.h>
|
||||
|
||||
#include "ehci.h"
|
||||
|
|
|
@ -21,91 +21,107 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/regs-common.h>
|
||||
#include <asm/arch/regs-base.h>
|
||||
#include <asm/arch/regs-clkctrl-mx28.h>
|
||||
#include <asm/arch/regs-usb.h>
|
||||
#include <asm/arch/regs-usbphy.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include "ehci.h"
|
||||
|
||||
#if (CONFIG_EHCI_MXS_PORT != 0) && (CONFIG_EHCI_MXS_PORT != 1)
|
||||
#error "MXS EHCI: Invalid port selected!"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_EHCI_MXS_PORT
|
||||
#error "MXS EHCI: Please define correct port using CONFIG_EHCI_MXS_PORT!"
|
||||
#endif
|
||||
|
||||
static struct ehci_mxs {
|
||||
struct mxs_usb_regs *usb_regs;
|
||||
struct mxs_usbphy_regs *phy_regs;
|
||||
} ehci_mxs;
|
||||
|
||||
int mxs_ehci_get_port(struct ehci_mxs *mxs_usb, int port)
|
||||
{
|
||||
uint32_t usb_base, phy_base;
|
||||
switch (port) {
|
||||
case 0:
|
||||
usb_base = MXS_USBCTRL0_BASE;
|
||||
phy_base = MXS_USBPHY0_BASE;
|
||||
break;
|
||||
case 1:
|
||||
usb_base = MXS_USBCTRL1_BASE;
|
||||
phy_base = MXS_USBPHY1_BASE;
|
||||
break;
|
||||
default:
|
||||
printf("CONFIG_EHCI_MXS_PORT (port = %d)\n", port);
|
||||
return -1;
|
||||
}
|
||||
|
||||
mxs_usb->usb_regs = (struct mxs_usb_regs *)usb_base;
|
||||
mxs_usb->phy_regs = (struct mxs_usbphy_regs *)phy_base;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* This DIGCTL register ungates clock to USB */
|
||||
#define HW_DIGCTL_CTRL 0x8001c000
|
||||
#define HW_DIGCTL_CTRL_USB0_CLKGATE (1 << 2)
|
||||
#define HW_DIGCTL_CTRL_USB1_CLKGATE (1 << 16)
|
||||
|
||||
struct ehci_mxs_port {
|
||||
uint32_t usb_regs;
|
||||
struct mxs_usbphy_regs *phy_regs;
|
||||
|
||||
struct mxs_register_32 *pll;
|
||||
uint32_t pll_en_bits;
|
||||
uint32_t pll_dis_bits;
|
||||
uint32_t gate_bits;
|
||||
};
|
||||
|
||||
static const struct ehci_mxs_port mxs_port[] = {
|
||||
#ifdef CONFIG_EHCI_MXS_PORT0
|
||||
{
|
||||
MXS_USBCTRL0_BASE,
|
||||
(struct mxs_usbphy_regs *)MXS_USBPHY0_BASE,
|
||||
(struct mxs_register_32 *)(MXS_CLKCTRL_BASE +
|
||||
offsetof(struct mxs_clkctrl_regs,
|
||||
hw_clkctrl_pll0ctrl0_reg)),
|
||||
CLKCTRL_PLL0CTRL0_EN_USB_CLKS | CLKCTRL_PLL0CTRL0_POWER,
|
||||
CLKCTRL_PLL0CTRL0_EN_USB_CLKS,
|
||||
HW_DIGCTL_CTRL_USB0_CLKGATE,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_EHCI_MXS_PORT1
|
||||
{
|
||||
MXS_USBCTRL1_BASE,
|
||||
(struct mxs_usbphy_regs *)MXS_USBPHY1_BASE,
|
||||
(struct mxs_register_32 *)(MXS_CLKCTRL_BASE +
|
||||
offsetof(struct mxs_clkctrl_regs,
|
||||
hw_clkctrl_pll1ctrl0_reg)),
|
||||
CLKCTRL_PLL1CTRL0_EN_USB_CLKS | CLKCTRL_PLL1CTRL0_POWER,
|
||||
CLKCTRL_PLL1CTRL0_EN_USB_CLKS,
|
||||
HW_DIGCTL_CTRL_USB1_CLKGATE,
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
static int ehci_mxs_toggle_clock(const struct ehci_mxs_port *port, int enable)
|
||||
{
|
||||
struct mxs_register_32 *digctl_ctrl =
|
||||
(struct mxs_register_32 *)HW_DIGCTL_CTRL;
|
||||
int pll_offset, dig_offset;
|
||||
|
||||
if (enable) {
|
||||
pll_offset = offsetof(struct mxs_register_32, reg_set);
|
||||
dig_offset = offsetof(struct mxs_register_32, reg_clr);
|
||||
writel(port->gate_bits, (u32)&digctl_ctrl->reg + dig_offset);
|
||||
writel(port->pll_en_bits, (u32)port->pll + pll_offset);
|
||||
} else {
|
||||
pll_offset = offsetof(struct mxs_register_32, reg_clr);
|
||||
dig_offset = offsetof(struct mxs_register_32, reg_set);
|
||||
writel(port->pll_dis_bits, (u32)port->pll + pll_offset);
|
||||
writel(port->gate_bits, (u32)&digctl_ctrl->reg + dig_offset);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
|
||||
{
|
||||
|
||||
int ret;
|
||||
uint32_t usb_base, cap_base;
|
||||
struct mxs_register_32 *digctl_ctrl =
|
||||
(struct mxs_register_32 *)HW_DIGCTL_CTRL;
|
||||
struct mxs_clkctrl_regs *clkctrl_regs =
|
||||
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
|
||||
const struct ehci_mxs_port *port;
|
||||
|
||||
ret = mxs_ehci_get_port(&ehci_mxs, CONFIG_EHCI_MXS_PORT);
|
||||
if ((index < 0) || (index >= ARRAY_SIZE(mxs_port))) {
|
||||
printf("Invalid port index (index = %d)!\n", index);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
port = &mxs_port[index];
|
||||
|
||||
/* Reset the PHY block */
|
||||
writel(USBPHY_CTRL_SFTRST, &port->phy_regs->hw_usbphy_ctrl_set);
|
||||
udelay(10);
|
||||
writel(USBPHY_CTRL_SFTRST | USBPHY_CTRL_CLKGATE,
|
||||
&port->phy_regs->hw_usbphy_ctrl_clr);
|
||||
|
||||
/* Enable USB clock */
|
||||
ret = ehci_mxs_toggle_clock(port, 1);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Reset the PHY block */
|
||||
writel(USBPHY_CTRL_SFTRST, &ehci_mxs.phy_regs->hw_usbphy_ctrl_set);
|
||||
udelay(10);
|
||||
writel(USBPHY_CTRL_SFTRST | USBPHY_CTRL_CLKGATE,
|
||||
&ehci_mxs.phy_regs->hw_usbphy_ctrl_clr);
|
||||
|
||||
/* Enable USB clock */
|
||||
writel(CLKCTRL_PLL0CTRL0_EN_USB_CLKS | CLKCTRL_PLL0CTRL0_POWER,
|
||||
&clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
|
||||
writel(CLKCTRL_PLL1CTRL0_EN_USB_CLKS | CLKCTRL_PLL1CTRL0_POWER,
|
||||
&clkctrl_regs->hw_clkctrl_pll1ctrl0_set);
|
||||
|
||||
writel(HW_DIGCTL_CTRL_USB0_CLKGATE | HW_DIGCTL_CTRL_USB1_CLKGATE,
|
||||
&digctl_ctrl->reg_clr);
|
||||
|
||||
/* Start USB PHY */
|
||||
writel(0, &ehci_mxs.phy_regs->hw_usbphy_pwd);
|
||||
writel(0, &port->phy_regs->hw_usbphy_pwd);
|
||||
|
||||
/* Enable UTMI+ Level 2 and Level 3 compatibility */
|
||||
writel(USBPHY_CTRL_ENUTMILEVEL3 | USBPHY_CTRL_ENUTMILEVEL2 | 1,
|
||||
&ehci_mxs.phy_regs->hw_usbphy_ctrl_set);
|
||||
&port->phy_regs->hw_usbphy_ctrl_set);
|
||||
|
||||
usb_base = ((uint32_t)ehci_mxs.usb_regs) + 0x100;
|
||||
usb_base = port->usb_regs + 0x100;
|
||||
*hccr = (struct ehci_hccr *)usb_base;
|
||||
|
||||
cap_base = ehci_readl(&(*hccr)->cr_capbase);
|
||||
|
@ -118,19 +134,19 @@ int ehci_hcd_stop(int index)
|
|||
{
|
||||
int ret;
|
||||
uint32_t usb_base, cap_base, tmp;
|
||||
struct mxs_register_32 *digctl_ctrl =
|
||||
(struct mxs_register_32 *)HW_DIGCTL_CTRL;
|
||||
struct mxs_clkctrl_regs *clkctrl_regs =
|
||||
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
|
||||
struct ehci_hccr *hccr;
|
||||
struct ehci_hcor *hcor;
|
||||
const struct ehci_mxs_port *port;
|
||||
|
||||
ret = mxs_ehci_get_port(&ehci_mxs, CONFIG_EHCI_MXS_PORT);
|
||||
if (ret)
|
||||
return ret;
|
||||
if ((index < 0) || (index >= ARRAY_SIZE(mxs_port))) {
|
||||
printf("Invalid port index (index = %d)!\n", index);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
port = &mxs_port[index];
|
||||
|
||||
/* Stop the USB port */
|
||||
usb_base = ((uint32_t)ehci_mxs.usb_regs) + 0x100;
|
||||
usb_base = port->usb_regs + 0x100;
|
||||
hccr = (struct ehci_hccr *)usb_base;
|
||||
cap_base = ehci_readl(&hccr->cr_capbase);
|
||||
hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base));
|
||||
|
@ -144,17 +160,10 @@ int ehci_hcd_stop(int index)
|
|||
USBPHY_PWD_RXPWD1PT1 | USBPHY_PWD_RXPWDENV |
|
||||
USBPHY_PWD_TXPWDV2I | USBPHY_PWD_TXPWDIBIAS |
|
||||
USBPHY_PWD_TXPWDFS;
|
||||
writel(tmp, &ehci_mxs.phy_regs->hw_usbphy_pwd);
|
||||
writel(tmp, &port->phy_regs->hw_usbphy_pwd);
|
||||
|
||||
/* Disable USB clock */
|
||||
writel(CLKCTRL_PLL0CTRL0_EN_USB_CLKS,
|
||||
&clkctrl_regs->hw_clkctrl_pll0ctrl0_clr);
|
||||
writel(CLKCTRL_PLL1CTRL0_EN_USB_CLKS,
|
||||
&clkctrl_regs->hw_clkctrl_pll1ctrl0_clr);
|
||||
ret = ehci_mxs_toggle_clock(port, 0);
|
||||
|
||||
/* Gate off the USB clock */
|
||||
writel(HW_DIGCTL_CTRL_USB0_CLKGATE | HW_DIGCTL_CTRL_USB1_CLKGATE,
|
||||
&digctl_ctrl->reg_set);
|
||||
|
||||
return 0;
|
||||
return ret;
|
||||
}
|
||||
|
|
|
@ -182,7 +182,8 @@
|
|||
#ifdef CONFIG_CMD_USB
|
||||
#define CONFIG_USB_EHCI
|
||||
#define CONFIG_USB_EHCI_MXS
|
||||
#define CONFIG_EHCI_MXS_PORT 1
|
||||
#define CONFIG_EHCI_MXS_PORT1
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
||||
#define CONFIG_EHCI_IS_TDI
|
||||
#define CONFIG_USB_STORAGE
|
||||
#endif
|
||||
|
|
|
@ -233,7 +233,9 @@
|
|||
#ifdef CONFIG_CMD_USB
|
||||
#define CONFIG_USB_EHCI
|
||||
#define CONFIG_USB_EHCI_MXS
|
||||
#define CONFIG_EHCI_MXS_PORT 1
|
||||
#define CONFIG_EHCI_MXS_PORT0
|
||||
#define CONFIG_EHCI_MXS_PORT1
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
||||
#define CONFIG_EHCI_IS_TDI
|
||||
#define CONFIG_USB_STORAGE
|
||||
#endif
|
||||
|
@ -244,7 +246,6 @@
|
|||
#ifdef CONFIG_CMD_SPI
|
||||
#define CONFIG_HARD_SPI
|
||||
#define CONFIG_MXS_SPI
|
||||
#define CONFIG_MXS_SPI_DMA_ENABLE
|
||||
#define CONFIG_SPI_HALF_DUPLEX
|
||||
#define CONFIG_DEFAULT_SPI_BUS 2
|
||||
#define CONFIG_DEFAULT_SPI_CS 0
|
||||
|
|
|
@ -19,6 +19,8 @@
|
|||
#ifndef __MX23_OLINUXINO_CONFIG_H__
|
||||
#define __MX23_OLINUXINO_CONFIG_H__
|
||||
|
||||
#include <asm/arch/iomux-mx23.h>
|
||||
|
||||
/*
|
||||
* SoC configurations
|
||||
*/
|
||||
|
@ -53,10 +55,14 @@
|
|||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
#define CONFIG_CMD_CACHE
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_GPIO
|
||||
#define CONFIG_CMD_LED
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_USB
|
||||
|
||||
/*
|
||||
* Memory configurations
|
||||
|
@ -111,6 +117,17 @@
|
|||
#define CONFIG_CONS_INDEX 0
|
||||
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
|
||||
|
||||
/*
|
||||
* Status LED
|
||||
*/
|
||||
#define CONFIG_STATUS_LED
|
||||
#define CONFIG_GPIO_LED
|
||||
#define CONFIG_BOARD_SPECIFIC_LED
|
||||
#define STATUS_LED_BOOT 0
|
||||
#define STATUS_LED_BIT MX23_PAD_SSP1_DETECT__GPIO_2_1
|
||||
#define STATUS_LED_STATE STATUS_LED_ON
|
||||
#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
|
||||
|
||||
/*
|
||||
* MMC Driver
|
||||
*/
|
||||
|
@ -126,6 +143,22 @@
|
|||
*/
|
||||
#define CONFIG_APBH_DMA
|
||||
|
||||
/* USB */
|
||||
#ifdef CONFIG_CMD_USB
|
||||
#define CONFIG_USB_EHCI
|
||||
#define CONFIG_USB_EHCI_MXS
|
||||
#define CONFIG_EHCI_MXS_PORT0
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
||||
#define CONFIG_EHCI_IS_TDI
|
||||
#define CONFIG_USB_STORAGE
|
||||
#endif
|
||||
|
||||
/* Ethernet */
|
||||
#ifdef CONFIG_CMD_NET
|
||||
#define CONFIG_USB_HOST_ETHER
|
||||
#define CONFIG_USB_ETHER_SMSC95XX
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Boot Linux
|
||||
*/
|
||||
|
@ -167,6 +200,7 @@
|
|||
"fdt_file=imx23-olinuxino.dtb\0" \
|
||||
"fdt_addr=0x41000000\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"ip_dyn=yes\0" \
|
||||
"mmcdev=0\0" \
|
||||
"mmcpart=2\0" \
|
||||
"mmcroot=/dev/mmcblk0p3 rw rootwait\0" \
|
||||
|
@ -192,6 +226,31 @@
|
|||
"fi; " \
|
||||
"else " \
|
||||
"bootm; " \
|
||||
"fi;\0" \
|
||||
"netargs=setenv bootargs console=${console_mainline},${baudrate} " \
|
||||
"root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||
"netboot=echo Booting from net ...; " \
|
||||
"usb start; " \
|
||||
"run netargs; " \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"${get_cmd} ${uimage}; " \
|
||||
"if test ${boot_fdt} = yes; then " \
|
||||
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
|
||||
"bootm ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootm; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi;" \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootm; " \
|
||||
"fi;\0"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
|
@ -201,10 +260,9 @@
|
|||
"else " \
|
||||
"if run loaduimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else " \
|
||||
"echo ERR: Fail to boot from MMC; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else exit; fi"
|
||||
"else run netboot; fi"
|
||||
|
||||
#endif /* __MX23_OLINUXINO_CONFIG_H__ */
|
||||
|
|
|
@ -33,8 +33,6 @@
|
|||
#define CONFIG_MACH_TYPE MACH_TYPE_MX23EVK
|
||||
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
#define CONFIG_SYS_ICACHE_OFF
|
||||
#define CONFIG_SYS_DCACHE_OFF
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define CONFIG_ARCH_MISC_INIT
|
||||
|
||||
|
@ -60,6 +58,7 @@
|
|||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_GPIO
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_CMD_BOOTZ
|
||||
|
||||
/* Memory configurations */
|
||||
|
@ -112,7 +111,6 @@
|
|||
#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
|
||||
#define CONFIG_CONS_INDEX 0
|
||||
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
/* DMA */
|
||||
#define CONFIG_APBH_DMA
|
||||
|
@ -125,6 +123,16 @@
|
|||
#define CONFIG_MXS_MMC
|
||||
#endif
|
||||
|
||||
/* USB */
|
||||
#ifdef CONFIG_CMD_USB
|
||||
#define CONFIG_USB_EHCI
|
||||
#define CONFIG_USB_EHCI_MXS
|
||||
#define CONFIG_EHCI_MXS_PORT0
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
||||
#define CONFIG_EHCI_IS_TDI
|
||||
#define CONFIG_USB_STORAGE
|
||||
#endif
|
||||
|
||||
/* Boot Linux */
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
|
|
|
@ -181,7 +181,8 @@
|
|||
#ifdef CONFIG_CMD_USB
|
||||
#define CONFIG_USB_EHCI
|
||||
#define CONFIG_USB_EHCI_MXS
|
||||
#define CONFIG_EHCI_MXS_PORT 1
|
||||
#define CONFIG_EHCI_MXS_PORT1
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
||||
#define CONFIG_EHCI_IS_TDI
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_USB_HOST_ETHER
|
||||
|
@ -202,7 +203,6 @@
|
|||
#ifdef CONFIG_CMD_SPI
|
||||
#define CONFIG_HARD_SPI
|
||||
#define CONFIG_MXS_SPI
|
||||
#define CONFIG_MXS_SPI_DMA_ENABLE
|
||||
#define CONFIG_SPI_HALF_DUPLEX
|
||||
#define CONFIG_DEFAULT_SPI_BUS 2
|
||||
#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0
|
||||
|
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef __MX6_COMMON_H
|
||||
#define __MX6_COMMON_H
|
||||
|
||||
#define CONFIG_ARM_ERRATA_743622
|
||||
#define CONFIG_ARM_ERRATA_751472
|
||||
|
||||
#endif
|
|
@ -24,6 +24,9 @@
|
|||
|
||||
#define CONFIG_MX6
|
||||
#define CONFIG_MX6Q
|
||||
|
||||
#include "mx6_common.h"
|
||||
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
|
||||
|
|
|
@ -19,6 +19,9 @@
|
|||
|
||||
#define CONFIG_MX6
|
||||
#define CONFIG_MX6Q
|
||||
|
||||
#include "mx6_common.h"
|
||||
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
|
||||
|
@ -171,6 +174,7 @@
|
|||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x10000000
|
||||
#define CONFIG_SYS_MEMTEST_END 0x10010000
|
||||
#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
|
|
@ -24,6 +24,9 @@
|
|||
|
||||
#define CONFIG_MX6
|
||||
#define CONFIG_MX6Q
|
||||
|
||||
#include "mx6_common.h"
|
||||
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
|
||||
|
@ -241,6 +244,7 @@
|
|||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x10000000
|
||||
#define CONFIG_SYS_MEMTEST_END 0x10010000
|
||||
#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
|
|
@ -0,0 +1,285 @@
|
|||
/*
|
||||
* Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Configuration settings for the Boundary Devices Nitrogen6X
|
||||
* and Freescale i.MX6Q Sabre Lite boards.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define CONFIG_MX6
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
|
||||
#define CONFIG_MACH_TYPE 3769
|
||||
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/imx-common/gpio.h>
|
||||
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_INITRD_TAG
|
||||
#define CONFIG_REVISION_TAG
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define CONFIG_MISC_INIT_R
|
||||
#define CONFIG_MXC_GPIO
|
||||
|
||||
#define CONFIG_MXC_UART
|
||||
#define CONFIG_MXC_UART_BASE UART2_BASE
|
||||
|
||||
#define CONFIG_CMD_SF
|
||||
#ifdef CONFIG_CMD_SF
|
||||
#define CONFIG_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH_SST
|
||||
#define CONFIG_MXC_SPI
|
||||
#define CONFIG_SF_DEFAULT_BUS 0
|
||||
#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(3, 19)<<8))
|
||||
#define CONFIG_SF_DEFAULT_SPEED 25000000
|
||||
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
|
||||
#endif
|
||||
|
||||
/* I2C Configs */
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
|
||||
/* OCOTP Configs */
|
||||
#define CONFIG_CMD_IMXOTP
|
||||
#ifdef CONFIG_CMD_IMXOTP
|
||||
#define CONFIG_IMX_OTP
|
||||
#define IMX_OTP_BASE OCOTP_BASE_ADDR
|
||||
#define IMX_OTP_ADDR_MAX 0x7F
|
||||
#define IMX_OTP_DATA_ERROR_VAL 0xBADABADA
|
||||
#define IMX_OTPWRITE_ENABLED
|
||||
#endif
|
||||
|
||||
/* MMC Configs */
|
||||
#define CONFIG_FSL_ESDHC
|
||||
#define CONFIG_FSL_USDHC
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 2
|
||||
|
||||
#define CONFIG_MMC
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_BOUNCE_BUFFER
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
#ifdef CONFIG_MX6Q
|
||||
#define CONFIG_CMD_SATA
|
||||
#endif
|
||||
|
||||
/*
|
||||
* SATA Configs
|
||||
*/
|
||||
#ifdef CONFIG_CMD_SATA
|
||||
#define CONFIG_DWC_AHSATA
|
||||
#define CONFIG_SYS_SATA_MAX_DEVICE 1
|
||||
#define CONFIG_DWC_AHSATA_PORT_ID 0
|
||||
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
|
||||
#define CONFIG_LBA48
|
||||
#define CONFIG_LIBATA
|
||||
#endif
|
||||
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_FEC_MXC
|
||||
#define CONFIG_MII
|
||||
#define IMX_FEC_BASE ENET_BASE_ADDR
|
||||
#define CONFIG_FEC_XCV_TYPE RGMII
|
||||
#define CONFIG_ETHPRIME "FEC"
|
||||
#define CONFIG_FEC_MXC_PHYADDR 6
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_MICREL
|
||||
#define CONFIG_PHY_MICREL_KSZ9021
|
||||
|
||||
/* USB Configs */
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_USB_EHCI
|
||||
#define CONFIG_USB_EHCI_MX6
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_USB_HOST_ETHER
|
||||
#define CONFIG_USB_ETHER_ASIX
|
||||
#define CONFIG_USB_ETHER_SMSC95XX
|
||||
#define CONFIG_MXC_USB_PORT 1
|
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
|
||||
#define CONFIG_MXC_USB_FLAGS 0
|
||||
|
||||
/* Miscellaneous commands */
|
||||
#define CONFIG_CMD_BMODE
|
||||
#define CONFIG_CMD_SETEXPR
|
||||
|
||||
/* Framebuffer and LCD */
|
||||
#define CONFIG_VIDEO
|
||||
#define CONFIG_VIDEO_IPUV3
|
||||
#define CONFIG_CFB_CONSOLE
|
||||
#define CONFIG_VGA_AS_SINGLE_DEVICE
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
|
||||
#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
|
||||
#define CONFIG_VIDEO_BMP_RLE8
|
||||
#define CONFIG_SPLASH_SCREEN
|
||||
#define CONFIG_BMP_16BPP
|
||||
#define CONFIG_VIDEO_LOGO
|
||||
#define CONFIG_IPUV3_CLK 260000000
|
||||
#define CONFIG_CMD_HDMIDETECT
|
||||
#define CONFIG_CONSOLE_MUX
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
/* Command definition */
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#undef CONFIG_CMD_IMLS
|
||||
|
||||
#define CONFIG_BOOTDELAY 1
|
||||
|
||||
#define CONFIG_PREBOOT ""
|
||||
|
||||
#define CONFIG_LOADADDR 0x12000000
|
||||
#define CONFIG_SYS_TEXT_BASE 0x17800000
|
||||
|
||||
#ifdef CONFIG_CMD_SATA
|
||||
#define CONFIG_DRIVE_SATA "sata "
|
||||
#else
|
||||
#define CONFIG_DRIVE_SATA
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CMD_MMC
|
||||
#define CONFIG_DRIVE_MMC "mmc "
|
||||
#else
|
||||
#define CONFIG_DRIVE_MMC
|
||||
#endif
|
||||
|
||||
#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"console=ttymxc1\0" \
|
||||
"clearenv=if sf probe || sf probe || sf probe 1 ; then " \
|
||||
"sf erase 0xc0000 0x2000 && " \
|
||||
"echo restored environment to factory default ; fi\0" \
|
||||
"bootcmd=for dtype in " CONFIG_DRIVE_TYPES \
|
||||
"; do " \
|
||||
"for disk in 0 1 ; do ${dtype} dev ${disk} ;" \
|
||||
"for fs in fat ext2 ; do " \
|
||||
"${fs}load " \
|
||||
"${dtype} ${disk}:1 " \
|
||||
"10008000 " \
|
||||
"/6x_bootscript" \
|
||||
"&& source 10008000 ; " \
|
||||
"done ; " \
|
||||
"done ; " \
|
||||
"done; " \
|
||||
"setenv stdout serial,vga ; " \
|
||||
"echo ; echo 6x_bootscript not found ; " \
|
||||
"echo ; echo serial console at 115200, 8N1 ; echo ; " \
|
||||
"echo details at http://boundarydevices.com/6q_bootscript ; " \
|
||||
"setenv stdout serial\0" \
|
||||
"upgradeu=for dtype in " CONFIG_DRIVE_TYPES \
|
||||
"; do " \
|
||||
"for disk in 0 1 ; do ${dtype} dev ${disk} ;" \
|
||||
"for fs in fat ext2 ; do " \
|
||||
"${fs}load ${dtype} ${disk}:1 10008000 " \
|
||||
"/6x_upgrade " \
|
||||
"&& source 10008000 ; " \
|
||||
"done ; " \
|
||||
"done ; " \
|
||||
"done\0" \
|
||||
|
||||
/* Miscellaneous configurable options */
|
||||
#define CONFIG_SYS_LONGHELP
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT "U-Boot > "
|
||||
#define CONFIG_AUTO_COMPLETE
|
||||
#define CONFIG_SYS_CBSIZE 1024
|
||||
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_MAXARGS 16
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x10000000
|
||||
#define CONFIG_SYS_MEMTEST_END 0x10010000
|
||||
#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
|
||||
/* Physical Memory Map */
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
/* FLASH and environment organization */
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
|
||||
#define CONFIG_ENV_SIZE (8 * 1024)
|
||||
|
||||
/* #define CONFIG_ENV_IS_IN_MMC */
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
|
||||
#if defined(CONFIG_ENV_IS_IN_MMC)
|
||||
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0
|
||||
#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
|
||||
#define CONFIG_ENV_OFFSET (768 * 1024)
|
||||
#define CONFIG_ENV_SECT_SIZE (8 * 1024)
|
||||
#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
|
||||
#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
|
||||
#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
|
||||
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
|
||||
#endif
|
||||
|
||||
#define CONFIG_OF_LIBFDT
|
||||
#define CONFIG_CMD_BOOTZ
|
||||
|
||||
#define CONFIG_SYS_DCACHE_OFF
|
||||
|
||||
#ifndef CONFIG_SYS_DCACHE_OFF
|
||||
#define CONFIG_CMD_CACHE
|
||||
#endif
|
||||
|
||||
#define CONFIG_CMD_BMP
|
||||
|
||||
#define CONFIG_CMD_TIME
|
||||
#define CONFIG_SYS_ALT_MEMTEST
|
||||
|
||||
#endif /* __CONFIG_H */
|
|
@ -170,7 +170,8 @@
|
|||
#ifdef CONFIG_CMD_USB
|
||||
#define CONFIG_USB_EHCI
|
||||
#define CONFIG_USB_EHCI_MXS
|
||||
#define CONFIG_EHCI_MXS_PORT 0
|
||||
#define CONFIG_EHCI_MXS_PORT0
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
||||
#define CONFIG_EHCI_IS_TDI
|
||||
#define CONFIG_USB_STORAGE
|
||||
#endif
|
||||
|
|
Loading…
Reference in New Issue