video: Remove the old parade driver
We have a new one which uses driver model and device tree configuration. Remove the old one. Signed-off-by: Simon Glass <sjg@chromium.org>utp
Simon Glass
parent
24696e2f21
commit
68964dbc83
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@ -51,7 +51,6 @@ obj-$(CONFIG_VIDEO_VESA) += vesa_fb.o
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obj-$(CONFIG_FORMIKE) += formike.o
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obj-$(CONFIG_LG4573) += lg4573.o
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obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
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obj-$(CONFIG_VIDEO_PARADE) += parade.o
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obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
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@ -1,231 +0,0 @@
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/*
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* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* This file is a driver for Parade dP<->LVDS bridges. The original submission
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* is for the ps8625 chip.
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*/
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#include <config.h>
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#include <common.h>
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#include <i2c.h>
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#include <fdtdec.h>
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#include <asm/gpio.h>
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/*
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* Initialization of the chip is a process of writing certaing values into
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* certain registers over i2c bus. The chip in fact responds to a range of
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* addresses on the i2c bus, so for each written value three parameters are
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* required: i2c address, register address and the actual value.
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*
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* The base address is derived from the device tree, only address offset is
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* stored in the table below.
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*/
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/**
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* struct reg_data() - data for a parade register write
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*
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* @addr_off offset from the i2c base address for parade
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* @reg_addr register address to write
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* @value value to be written
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*/
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struct reg_data {
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uint8_t addr_off;
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uint8_t reg;
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uint8_t value;
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} _packed;
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#define END_OF_TABLE 0xff /* Ficticious offset */
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static const struct reg_data parade_values[] = {
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{0x02, 0xa1, 0x01}, /* HPD low */
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/*
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* SW setting
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* [1:0] SW output 1.2V voltage is lower to 96%
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*/
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{0x04, 0x14, 0x01},
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/*
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* RCO SS setting
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* [5:4] = b01 0.5%, b10 1%, b11 1.5%
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*/
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{0x04, 0xe3, 0x20},
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{0x04, 0xe2, 0x80}, /* [7] RCO SS enable */
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/*
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* RPHY Setting
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* [3:2] CDR tune wait cycle before
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* measure for fine tune b00: 1us,
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* 01: 0.5us, 10:2us, 11:4us.
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*/
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{0x04, 0x8a, 0x0c},
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{0x04, 0x89, 0x08}, /* [3] RFD always on */
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/*
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* CTN lock in/out:
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* 20000ppm/80000ppm. Lock out 2
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* times.
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*/
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{0x04, 0x71, 0x2d},
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/*
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* 2.7G CDR settings
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* NOF=40LSB for HBR CDR setting
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*/
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{0x04, 0x7d, 0x07},
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{0x04, 0x7b, 0x00}, /* [1:0] Fmin=+4bands */
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{0x04, 0x7a, 0xfd}, /* [7:5] DCO_FTRNG=+-40% */
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/*
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* 1.62G CDR settings
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* [5:2]NOF=64LSB [1:0]DCO scale is 2/5
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*/
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{0x04, 0xc0, 0x12},
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{0x04, 0xc1, 0x92}, /* Gitune=-37% */
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{0x04, 0xc2, 0x1c}, /* Fbstep=100% */
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{0x04, 0x32, 0x80}, /* [7] LOS signal disable */
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/*
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* RPIO Setting
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* [7:4] LVDS driver bias current :
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* 75% (250mV swing)
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*/
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{0x04, 0x00, 0xb0},
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/*
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* [7:6] Right-bar GPIO output strength is 8mA
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*/
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{0x04, 0x15, 0x40},
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/* EQ Training State Machine Setting */
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{0x04, 0x54, 0x10}, /* RCO calibration start */
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/* [4:0] MAX_LANE_COUNT set to one lane */
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{0x01, 0x02, 0x81},
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/* [4:0] LANE_COUNT_SET set to one lane */
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{0x01, 0x21, 0x81},
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{0x00, 0x52, 0x20},
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{0x00, 0xf1, 0x03}, /* HPD CP toggle enable */
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{0x00, 0x62, 0x41},
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/* Counter number, add 1ms counter delay */
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{0x00, 0xf6, 0x01},
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/*
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* [6]PWM function control by
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* DPCD0040f[7], default is PWM
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* block always works.
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*/
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{0x00, 0x77, 0x06},
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/*
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* 04h Adjust VTotal tolerance to
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* fix the 30Hz no display issue
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*/
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{0x00, 0x4c, 0x04},
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/* DPCD00400='h00, Parade OUI = 'h001cf8 */
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{0x01, 0xc0, 0x00},
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{0x01, 0xc1, 0x1c}, /* DPCD00401='h1c */
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{0x01, 0xc2, 0xf8}, /* DPCD00402='hf8 */
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/*
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* DPCD403~408 = ASCII code
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* D2SLV5='h4432534c5635
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*/
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{0x01, 0xc3, 0x44},
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{0x01, 0xc4, 0x32}, /* DPCD404 */
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{0x01, 0xc5, 0x53}, /* DPCD405 */
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{0x01, 0xc6, 0x4c}, /* DPCD406 */
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{0x01, 0xc7, 0x56}, /* DPCD407 */
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{0x01, 0xc8, 0x35}, /* DPCD408 */
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/*
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* DPCD40A, Initial Code major revision
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* '01'
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*/
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{0x01, 0xca, 0x01},
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/* DPCD40B, Initial Code minor revision '05' */
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{0x01, 0xcb, 0x05},
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/* DPCD720, Select internal PWM */
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{0x01, 0xa5, 0xa0},
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/*
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* FFh for 100% PWM of brightness, 0h for 0%
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* brightness
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*/
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{0x01, 0xa7, 0xff},
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/*
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* Set LVDS output as 6bit-VESA mapping,
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* single LVDS channel
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*/
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{0x01, 0xcc, 0x13},
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/* Enable SSC set by register */
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{0x02, 0xb1, 0x20},
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/*
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* Set SSC enabled and +/-1% central
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* spreading
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*/
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{0x04, 0x10, 0x16},
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/* MPU Clock source: LC => RCO */
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{0x04, 0x59, 0x60},
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{0x04, 0x54, 0x14}, /* LC -> RCO */
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{0x02, 0xa1, 0x91}, /* HPD high */
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{END_OF_TABLE}
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};
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/**
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* Write values table into the Parade eDP bridge
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*
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* @return 0 on success, non-0 on failure
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*/
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static int parade_write_regs(int base_addr, const struct reg_data *table)
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{
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int ret = 0;
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while (!ret && (table->addr_off != END_OF_TABLE)) {
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ret = i2c_write(base_addr + table->addr_off,
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table->reg, 1,
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(uint8_t *)&table->value,
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sizeof(table->value));
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table++;
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}
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return ret;
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}
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int parade_init(const void *blob)
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{
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struct gpio_desc rst_gpio;
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struct gpio_desc slp_gpio;
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int bus, old_bus;
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int parent;
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int node;
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int addr;
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int ret;
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node = fdtdec_next_compatible(blob, 0, COMPAT_PARADE_PS8625);
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if (node < 0)
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return 0;
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parent = fdt_parent_offset(blob, node);
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if (parent < 0) {
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debug("%s: Could not find parent i2c node\n", __func__);
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return -1;
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}
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addr = fdtdec_get_int(blob, node, "reg", -1);
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if (addr < 0) {
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debug("%s: Could not find i2c address\n", __func__);
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return -1;
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}
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gpio_request_by_name_nodev(blob, node, "sleep-gpio", 0, &slp_gpio,
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GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
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mdelay(10);
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gpio_request_by_name_nodev(blob, node, "reset-gpio", 0, &rst_gpio,
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GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
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bus = i2c_get_bus_num_fdt(parent);
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old_bus = i2c_get_bus_num();
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debug("%s: Using i2c bus %d\n", __func__, bus);
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/*
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* TODO(sjg@chromium.org): Hmmm we seem to need some sort of delay
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* here.
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*/
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mdelay(40);
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i2c_set_bus_num(bus);
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ret = parade_write_regs(addr, parade_values);
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i2c_set_bus_num(old_bus);
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return ret;
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}
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@ -32,8 +32,6 @@
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#define CONFIG_SYS_PROMPT "Peach-Pi # "
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#define CONFIG_IDENT_STRING " for Peach-Pi"
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#define CONFIG_VIDEO_PARADE
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/* Display */
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#define CONFIG_LCD
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#ifdef CONFIG_LCD
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@ -32,8 +32,6 @@
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#define CONFIG_SYS_PROMPT "Peach-Pit # "
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#define CONFIG_IDENT_STRING " for Peach-Pit"
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#define CONFIG_VIDEO_PARADE
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/* DRAM Memory Banks */
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#define CONFIG_NR_DRAM_BANKS 4
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#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
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@ -172,7 +172,6 @@ enum fdt_compat_id {
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COMPAT_SANDBOX_LCD_SDL, /* Sandbox LCD emulation with SDL */
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COMPAT_NXP_PTN3460, /* NXP PTN3460 DP/LVDS bridge */
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COMPAT_SAMSUNG_EXYNOS_SYSMMU, /* Exynos sysmmu */
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COMPAT_PARADE_PS8625, /* Parade PS8622 EDP->LVDS bridge */
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COMPAT_INTEL_MICROCODE, /* Intel microcode update */
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COMPAT_MEMORY_SPD, /* Memory SPD information */
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COMPAT_INTEL_PANTHERPOINT_AHCI, /* Intel Pantherpoint AHCI */
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@ -1,18 +0,0 @@
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/*
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* (C) Copyright 2012 Samsung Electronics
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* Donghwa Lee <dh09.lee@samsung.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __PARADE_H__
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#define __PARADE_H__
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/* Initialize the Parade dP<->LVDS bridge if present */
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#ifdef CONFIG_VIDEO_PARADE
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int parade_init(const void *blob);
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#else
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static inline int parade_init(const void *blob) { return -1; }
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#endif
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#endif /* __PARADE_H__ */
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@ -64,7 +64,6 @@ static const char * const compat_names[COMPAT_COUNT] = {
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COMPAT(SANDBOX_LCD_SDL, "sandbox,lcd-sdl"),
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COMPAT(COMPAT_NXP_PTN3460, "nxp,ptn3460"),
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COMPAT(SAMSUNG_EXYNOS_SYSMMU, "samsung,sysmmu-v3.3"),
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COMPAT(PARADE_PS8625, "parade,ps8625"),
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COMPAT(INTEL_MICROCODE, "intel,microcode"),
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COMPAT(MEMORY_SPD, "memory-spd"),
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COMPAT(INTEL_PANTHERPOINT_AHCI, "intel,pantherpoint-ahci"),
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