davinci_nand: cleanup II (CONFIG_SYS_DAVINCI_BROKEN_ECC)
Remove CONFIG_SYS_DAVINCI_BROKEN_ECC option. It's not just nasty; it's also unused by any current boards, and doesn't even match the main U-Boot distributions from TI (which use soft ECC, or 4-bit ECC on newer chips that support it). DaVinci GIT kernels since 2.6.24, and mainline Linux since 2.6.30, match non-BROKEN code paths for 1-bit HW ECC. The BROKEN code paths do seem to partially match what MontaVista/TI kernels (4.0/2.6.10, and 5.0/2.6.18) do ... but only for small pages. Large page support is really broken (and it's unclear just what software it was trying to match!), and the ECC layout was making three more bytes available for use by filesystem (or whatever) code. Since this option itself seems broken, remove it. Add a comment about the MV/TI compat issue, and the most straightforward way to address it (should someone really need to solve it). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Scott Wood <scottwood@freescale.com>utp
David Brownell
Scott Wood
parent
fcb7747775
commit
6e29ed8e57
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@ -101,15 +101,6 @@ Configuration Options:
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CONFIG_SYS_NAND_MAX_CHIPS
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The maximum number of NAND chips per device to be supported.
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CONFIG_SYS_DAVINCI_BROKEN_ECC
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Versions of U-Boot <= 1.3.3 and Montavista Linux kernels
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generated bogus ECCs on large-page NAND. Both large and small page
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NAND ECCs were incompatible with the Linux davinci git tree (since
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NAND was integrated in 2.6.24).
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Turn this ON if you want backwards compatibility.
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Turn this OFF if you want U-Boot and the Linux davinci git kernel
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to use the same ECC format.
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NOTE:
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=====
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@ -86,45 +86,12 @@ static void nand_davinci_select_chip(struct mtd_info *mtd, int chip)
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}
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#ifdef CONFIG_SYS_NAND_HW_ECC
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#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
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/* Linux-compatible ECC uses MTD defaults. */
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/* These layouts are not compatible with Linux or RBL/UBL. */
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#ifdef CONFIG_SYS_NAND_LARGEPAGE
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static struct nand_ecclayout davinci_nand_ecclayout = {
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.eccbytes = 12,
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.eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
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.oobfree = {
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{.offset = 2, .length = 6},
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{.offset = 12, .length = 12},
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{.offset = 28, .length = 12},
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{.offset = 44, .length = 12},
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{.offset = 60, .length = 4}
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}
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};
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#elif defined(CONFIG_SYS_NAND_SMALLPAGE)
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static struct nand_ecclayout davinci_nand_ecclayout = {
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.eccbytes = 3,
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.eccpos = {0, 1, 2},
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.oobfree = {
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{.offset = 6, .length = 2},
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{.offset = 8, .length = 8}
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}
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};
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#else
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#error "Either CONFIG_SYS_NAND_LARGEPAGE or CONFIG_SYS_NAND_SMALLPAGE must be defined!"
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#endif
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#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
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static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
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{
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int dummy;
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dummy = emif_regs->NANDF1ECC;
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#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
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dummy = emif_regs->NANDF2ECC;
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dummy = emif_regs->NANDF3ECC;
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dummy = emif_regs->NANDF4ECC;
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#endif
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/* FIXME: only chipselect 0 is supported for now */
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emif_regs->NANDFCR |= 1 << 8;
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@ -149,29 +116,6 @@ static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
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static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
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{
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u_int32_t tmp;
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#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
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/*
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* This is not how you should read ECCs on large page Davinci devices.
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* The region parameter gets you ECCs for flash chips on different chip
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* selects, not the 4x512 byte pages in a 2048 byte page.
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*
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* Preserved for backwards compatibility though.
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*/
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int region, n;
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struct nand_chip *this = mtd->priv;
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n = (this->ecc.size/512);
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region = 1;
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while (n--) {
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tmp = nand_davinci_readecc(mtd, region);
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*ecc_code++ = tmp;
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*ecc_code++ = tmp >> 16;
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*ecc_code++ = ((tmp >> 8) & 0x0f) | ((tmp >> 20) & 0xf0);
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region++;
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}
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#else
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const int region = 1;
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tmp = nand_davinci_readecc(mtd, region);
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@ -186,148 +130,26 @@ static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u
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*ecc_code++ = tmp;
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*ecc_code++ = tmp >> 8;
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*ecc_code++ = tmp >> 16;
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#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
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return(0);
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/* NOTE: the above code matches mainline Linux:
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* .PQR.stu ==> ~PQRstu
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*
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* MontaVista/TI kernels encode those bytes differently, use
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* complicated (and allegedly sometimes-wrong) correction code,
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* and usually shipped with U-Boot that uses software ECC:
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* .PQR.stu ==> PsQRtu
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*
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* If you need MV/TI compatible NAND I/O in U-Boot, it should
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* be possible to (a) change the mangling above, (b) reverse
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* that mangling in nand_davinci_correct_data() below.
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*/
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return 0;
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}
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#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
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static void nand_davinci_gen_true_ecc(u_int8_t *ecc_buf)
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{
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u_int32_t tmp = ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xf0) << 20) | ((ecc_buf[2] & 0x0f) << 8);
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ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) | P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
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ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) | P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
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ecc_buf[2] = ~( P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) | P1e(tmp) | P2048o(tmp) | P2048e(tmp));
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}
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static int nand_davinci_compare_ecc(u_int8_t *ecc_nand, u_int8_t *ecc_calc, u_int8_t *page_data)
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{
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u_int32_t i;
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u_int8_t tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
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u_int8_t comp0_bit[8], comp1_bit[8], comp2_bit[8];
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u_int8_t ecc_bit[24];
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u_int8_t ecc_sum = 0;
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u_int8_t find_bit = 0;
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u_int32_t find_byte = 0;
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int is_ecc_ff;
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is_ecc_ff = ((*ecc_nand == 0xff) && (*(ecc_nand + 1) == 0xff) && (*(ecc_nand + 2) == 0xff));
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nand_davinci_gen_true_ecc(ecc_nand);
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nand_davinci_gen_true_ecc(ecc_calc);
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for (i = 0; i <= 2; i++) {
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*(ecc_nand + i) = ~(*(ecc_nand + i));
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*(ecc_calc + i) = ~(*(ecc_calc + i));
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}
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for (i = 0; i < 8; i++) {
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tmp0_bit[i] = *ecc_nand % 2;
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*ecc_nand = *ecc_nand / 2;
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}
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for (i = 0; i < 8; i++) {
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tmp1_bit[i] = *(ecc_nand + 1) % 2;
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*(ecc_nand + 1) = *(ecc_nand + 1) / 2;
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}
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for (i = 0; i < 8; i++) {
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tmp2_bit[i] = *(ecc_nand + 2) % 2;
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*(ecc_nand + 2) = *(ecc_nand + 2) / 2;
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}
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for (i = 0; i < 8; i++) {
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comp0_bit[i] = *ecc_calc % 2;
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*ecc_calc = *ecc_calc / 2;
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}
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for (i = 0; i < 8; i++) {
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comp1_bit[i] = *(ecc_calc + 1) % 2;
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*(ecc_calc + 1) = *(ecc_calc + 1) / 2;
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}
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for (i = 0; i < 8; i++) {
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comp2_bit[i] = *(ecc_calc + 2) % 2;
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*(ecc_calc + 2) = *(ecc_calc + 2) / 2;
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}
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for (i = 0; i< 6; i++)
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ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
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for (i = 0; i < 8; i++)
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ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
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for (i = 0; i < 8; i++)
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ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
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ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
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ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
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for (i = 0; i < 24; i++)
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ecc_sum += ecc_bit[i];
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switch (ecc_sum) {
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case 0:
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/* Not reached because this function is not called if
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ECC values are equal */
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return 0;
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case 1:
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/* Uncorrectable error */
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MTDDEBUG (MTD_DEBUG_LEVEL0,
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"ECC UNCORRECTED_ERROR 1\n");
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return(-1);
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case 12:
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/* Correctable error */
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find_byte = (ecc_bit[23] << 8) +
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(ecc_bit[21] << 7) +
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(ecc_bit[19] << 6) +
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(ecc_bit[17] << 5) +
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(ecc_bit[15] << 4) +
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(ecc_bit[13] << 3) +
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(ecc_bit[11] << 2) +
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(ecc_bit[9] << 1) +
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ecc_bit[7];
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find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
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MTDDEBUG (MTD_DEBUG_LEVEL0, "Correcting single bit ECC "
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"error at offset: %d, bit: %d\n",
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find_byte, find_bit);
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page_data[find_byte] ^= (1 << find_bit);
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return(0);
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default:
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if (is_ecc_ff) {
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if (ecc_calc[0] == 0 && ecc_calc[1] == 0 && ecc_calc[2] == 0)
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return(0);
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}
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MTDDEBUG (MTD_DEBUG_LEVEL0,
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"UNCORRECTED_ERROR default\n");
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return(-1);
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}
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}
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#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
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static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc)
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{
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struct nand_chip *this = mtd->priv;
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#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
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int block_count = 0, i, rc;
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block_count = (this->ecc.size/512);
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for (i = 0; i < block_count; i++) {
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if (memcmp(read_ecc, calc_ecc, 3) != 0) {
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rc = nand_davinci_compare_ecc(read_ecc, calc_ecc, dat);
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if (rc < 0) {
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return(rc);
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}
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}
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read_ecc += 3;
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calc_ecc += 3;
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dat += 512;
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}
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#else
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u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) |
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(read_ecc[2] << 16);
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u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) |
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@ -361,7 +183,6 @@ static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *
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return -1;
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}
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}
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#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
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return(0);
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}
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#endif /* CONFIG_SYS_NAND_HW_ECC */
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@ -416,21 +237,8 @@ int board_nand_init(struct nand_chip *nand)
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#endif
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#ifdef CONFIG_SYS_NAND_HW_ECC
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nand->ecc.mode = NAND_ECC_HW;
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#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
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nand->ecc.layout = &davinci_nand_ecclayout;
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#ifdef CONFIG_SYS_NAND_LARGEPAGE
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nand->ecc.size = 2048;
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nand->ecc.bytes = 12;
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#elif defined(CONFIG_SYS_NAND_SMALLPAGE)
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nand->ecc.size = 512;
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nand->ecc.bytes = 3;
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#else
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#error "Either CONFIG_SYS_NAND_LARGEPAGE or CONFIG_SYS_NAND_SMALLPAGE must be defined!"
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#endif
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#else
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nand->ecc.size = 512;
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nand->ecc.bytes = 3;
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#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
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nand->ecc.calculate = nand_davinci_calculate_ecc;
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nand->ecc.correct = nand_davinci_correct_data;
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nand->ecc.hwctl = nand_davinci_enable_hwecc;
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@ -35,73 +35,4 @@
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#define NAND_READ_END 0x30
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#define NAND_STATUS 0x70
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#ifdef CONFIG_SYS_NAND_HW_ECC
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#define NAND_Ecc_P1e (1 << 0)
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#define NAND_Ecc_P2e (1 << 1)
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#define NAND_Ecc_P4e (1 << 2)
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#define NAND_Ecc_P8e (1 << 3)
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#define NAND_Ecc_P16e (1 << 4)
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#define NAND_Ecc_P32e (1 << 5)
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#define NAND_Ecc_P64e (1 << 6)
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#define NAND_Ecc_P128e (1 << 7)
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#define NAND_Ecc_P256e (1 << 8)
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#define NAND_Ecc_P512e (1 << 9)
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#define NAND_Ecc_P1024e (1 << 10)
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#define NAND_Ecc_P2048e (1 << 11)
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#define NAND_Ecc_P1o (1 << 16)
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#define NAND_Ecc_P2o (1 << 17)
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#define NAND_Ecc_P4o (1 << 18)
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#define NAND_Ecc_P8o (1 << 19)
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#define NAND_Ecc_P16o (1 << 20)
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#define NAND_Ecc_P32o (1 << 21)
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#define NAND_Ecc_P64o (1 << 22)
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#define NAND_Ecc_P128o (1 << 23)
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#define NAND_Ecc_P256o (1 << 24)
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#define NAND_Ecc_P512o (1 << 25)
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#define NAND_Ecc_P1024o (1 << 26)
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#define NAND_Ecc_P2048o (1 << 27)
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#define TF(v) (v ? 1 : 0)
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#define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0)
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#define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1)
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#define P1e(a) (TF(a & NAND_Ecc_P1e) << 2)
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#define P1o(a) (TF(a & NAND_Ecc_P1o) << 3)
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#define P2e(a) (TF(a & NAND_Ecc_P2e) << 4)
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#define P2o(a) (TF(a & NAND_Ecc_P2o) << 5)
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#define P4e(a) (TF(a & NAND_Ecc_P4e) << 6)
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#define P4o(a) (TF(a & NAND_Ecc_P4o) << 7)
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#define P8e(a) (TF(a & NAND_Ecc_P8e) << 0)
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#define P8o(a) (TF(a & NAND_Ecc_P8o) << 1)
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#define P16e(a) (TF(a & NAND_Ecc_P16e) << 2)
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#define P16o(a) (TF(a & NAND_Ecc_P16o) << 3)
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#define P32e(a) (TF(a & NAND_Ecc_P32e) << 4)
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#define P32o(a) (TF(a & NAND_Ecc_P32o) << 5)
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#define P64e(a) (TF(a & NAND_Ecc_P64e) << 6)
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#define P64o(a) (TF(a & NAND_Ecc_P64o) << 7)
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#define P128e(a) (TF(a & NAND_Ecc_P128e) << 0)
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#define P128o(a) (TF(a & NAND_Ecc_P128o) << 1)
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#define P256e(a) (TF(a & NAND_Ecc_P256e) << 2)
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#define P256o(a) (TF(a & NAND_Ecc_P256o) << 3)
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#define P512e(a) (TF(a & NAND_Ecc_P512e) << 4)
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#define P512o(a) (TF(a & NAND_Ecc_P512o) << 5)
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#define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6)
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#define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7)
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#define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0)
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#define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1)
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#define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2)
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#define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3)
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#define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4)
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#define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5)
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#define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6)
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#define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7)
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#define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0)
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#define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1)
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#endif
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||||
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#endif
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||||
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|
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|||
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Reference in New Issue