1
0
Fork 0

[FIX] remove cute code

utp
Michal Simek 2007-08-06 23:41:53 +02:00
parent f500d9fdeb
commit 706714d97a
3 changed files with 314 additions and 292 deletions

View File

@ -41,76 +41,78 @@
static unsigned int etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
static u8 EMACAddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 };
static u8 emacaddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 };
static XEmac Emac;
static xemac emac;
void eth_halt(void)
{
return;
#ifdef DEBUG
puts ("eth_halt\n");
#endif
}
int eth_init(bd_t * bis)
{
u32 HelpReg;
u32 helpreg;
#ifdef DEBUG
printf("EMAC Initialization Started\n\r");
#endif
if (Emac.IsStarted) {
if (emac.isstarted) {
puts("Emac is started\n");
return 0;
}
memset (&Emac, 0, sizeof (XEmac));
memset (&emac, 0, sizeof (xemac));
Emac.BaseAddress = XILINX_EMAC_BASEADDR;
emac.baseaddress = XILINX_EMAC_BASEADDR;
/* Setting up FIFOs */
Emac.RecvFifo.RegBaseAddress = Emac.BaseAddress +
emac.recvfifo.regbaseaddress = emac.baseaddress +
XEM_PFIFO_RXREG_OFFSET;
Emac.RecvFifo.DataBaseAddress = Emac.BaseAddress +
emac.recvfifo.databaseaddress = emac.baseaddress +
XEM_PFIFO_RXDATA_OFFSET;
out_be32 (Emac.RecvFifo.RegBaseAddress, XPF_RESET_FIFO_MASK);
out_be32 (emac.recvfifo.regbaseaddress, XPF_RESET_FIFO_MASK);
Emac.SendFifo.RegBaseAddress = Emac.BaseAddress +
emac.sendfifo.regbaseaddress = emac.baseaddress +
XEM_PFIFO_TXREG_OFFSET;
Emac.SendFifo.DataBaseAddress = Emac.BaseAddress +
emac.sendfifo.databaseaddress = emac.baseaddress +
XEM_PFIFO_TXDATA_OFFSET;
out_be32 (Emac.SendFifo.RegBaseAddress, XPF_RESET_FIFO_MASK);
out_be32 (emac.sendfifo.regbaseaddress, XPF_RESET_FIFO_MASK);
/* Reset the entire IPIF */
out_be32 (Emac.BaseAddress + XIIF_V123B_RESETR_OFFSET,
out_be32 (emac.baseaddress + XIIF_V123B_RESETR_OFFSET,
XIIF_V123B_RESET_MASK);
/* Stopping EMAC for setting up MAC */
HelpReg = in_be32 (Emac.BaseAddress + XEM_ECR_OFFSET);
HelpReg &= ~(XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK);
out_be32 (Emac.BaseAddress + XEM_ECR_OFFSET, HelpReg);
helpreg = in_be32 (emac.baseaddress + XEM_ECR_OFFSET);
helpreg &= ~(XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK);
out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg);
if (!getenv("ethaddr")) {
memcpy(bis->bi_enetaddr, EMACAddr, ENET_ADDR_LENGTH);
memcpy(bis->bi_enetaddr, emacaddr, ENET_ADDR_LENGTH);
}
/* Set the device station address high and low registers */
HelpReg = (bis->bi_enetaddr[0] << 8) | bis->bi_enetaddr[1];
out_be32 (Emac.BaseAddress + XEM_SAH_OFFSET, HelpReg);
HelpReg = (bis->bi_enetaddr[2] << 24) | (bis->bi_enetaddr[3] << 16) |
helpreg = (bis->bi_enetaddr[0] << 8) | bis->bi_enetaddr[1];
out_be32 (emac.baseaddress + XEM_SAH_OFFSET, helpreg);
helpreg = (bis->bi_enetaddr[2] << 24) | (bis->bi_enetaddr[3] << 16) |
(bis->bi_enetaddr[4] << 8) | bis->bi_enetaddr[5];
out_be32 (Emac.BaseAddress + XEM_SAL_OFFSET, HelpReg);
out_be32 (emac.baseaddress + XEM_SAL_OFFSET, helpreg);
HelpReg = XEM_ECR_UNICAST_ENABLE_MASK | XEM_ECR_BROAD_ENABLE_MASK |
helpreg = XEM_ECR_UNICAST_ENABLE_MASK | XEM_ECR_BROAD_ENABLE_MASK |
XEM_ECR_FULL_DUPLEX_MASK | XEM_ECR_XMIT_FCS_ENABLE_MASK |
XEM_ECR_XMIT_PAD_ENABLE_MASK | XEM_ECR_PHY_ENABLE_MASK;
out_be32 (Emac.BaseAddress + XEM_ECR_OFFSET, HelpReg);
out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg);
Emac.IsStarted = 1;
emac.isstarted = 1;
/* Enable the transmitter, and receiver */
HelpReg = in_be32 (Emac.BaseAddress + XEM_ECR_OFFSET);
HelpReg &= ~(XEM_ECR_XMIT_RESET_MASK | XEM_ECR_RECV_RESET_MASK);
HelpReg |= (XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK);
out_be32 (Emac.BaseAddress + XEM_ECR_OFFSET, HelpReg);
helpreg = in_be32 (emac.baseaddress + XEM_ECR_OFFSET);
helpreg &= ~(XEM_ECR_XMIT_RESET_MASK | XEM_ECR_RECV_RESET_MASK);
helpreg |= (XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK);
out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg);
printf("EMAC Initialization complete\n\r");
return 0;
@ -118,12 +120,12 @@ int eth_init(bd_t * bis)
int eth_send(volatile void *ptr, int len)
{
u32 IntrStatus;
u32 XmitStatus;
u32 FifoCount;
u32 WordCount;
u32 ExtraByteCount;
u32 *WordBuffer = (u32 *) ptr;
u32 intrstatus;
u32 xmitstatus;
u32 fifocount;
u32 wordcount;
u32 extrabytecount;
u32 *wordbuffer = (u32 *) ptr;
if (len > ENET_MAX_MTU)
len = ENET_MAX_MTU;
@ -135,20 +137,20 @@ int eth_send(volatile void *ptr, int len)
* continue. The upper layer software should reset the device to resolve
* the error.
*/
IntrStatus = in_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET);
if (IntrStatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK |
intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET);
if (intrstatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK |
XEM_EIR_XMIT_LFIFO_OVER_MASK)) {
#ifdef DEBUG
puts ("Transmitting overrun error\n");
#endif
return 0;
} else if (IntrStatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK |
} else if (intrstatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK |
XEM_EIR_XMIT_LFIFO_UNDER_MASK)) {
#ifdef DEBUG
puts ("Transmitting underrun error\n");
#endif
return 0;
} else if (in_be32 (Emac.SendFifo.RegBaseAddress +
} else if (in_be32 (emac.sendfifo.regbaseaddress +
XPF_COUNT_STATUS_REG_OFFSET) & XPF_DEADLOCK_MASK) {
#ifdef DEBUG
puts("Transmitting fifo error\n");
@ -165,9 +167,9 @@ int eth_send(volatile void *ptr, int len)
* Clear the latched LFIFO_FULL bit so next time around the most
* current status is represented
*/
if (IntrStatus & XEM_EIR_XMIT_LFIFO_FULL_MASK) {
out_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET, IntrStatus
& XEM_EIR_XMIT_LFIFO_FULL_MASK);
if (intrstatus & XEM_EIR_XMIT_LFIFO_FULL_MASK) {
out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET,
intrstatus & XEM_EIR_XMIT_LFIFO_FULL_MASK);
#ifdef DEBUG
puts ("Fifo is full\n");
#endif
@ -175,72 +177,72 @@ int eth_send(volatile void *ptr, int len)
}
/* get the count of how many words may be inserted into the FIFO */
FifoCount = in_be32 (Emac.SendFifo.RegBaseAddress +
fifocount = in_be32 (emac.sendfifo.regbaseaddress +
XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK;
WordCount = len >> 2;
ExtraByteCount = len & 0x3;
wordcount = len >> 2;
extrabytecount = len & 0x3;
if (FifoCount < WordCount) {
if (fifocount < wordcount) {
#ifdef DEBUG
puts ("Sending packet is larger then size of FIFO\n");
#endif
return 0;
}
for (FifoCount = 0; FifoCount < WordCount; FifoCount++) {
out_be32 (Emac.SendFifo.DataBaseAddress, WordBuffer[FifoCount]);
for (fifocount = 0; fifocount < wordcount; fifocount++) {
out_be32 (emac.sendfifo.databaseaddress, wordbuffer[fifocount]);
}
if (ExtraByteCount > 0) {
u32 LastWord = 0;
u8 *ExtraBytesBuffer = (u8 *) (WordBuffer + WordCount);
if (extrabytecount > 0) {
u32 lastword = 0;
u8 *extrabytesbuffer = (u8 *) (wordbuffer + wordcount);
if (ExtraByteCount == 1) {
LastWord = ExtraBytesBuffer[0] << 24;
} else if (ExtraByteCount == 2) {
LastWord = ExtraBytesBuffer[0] << 24 |
ExtraBytesBuffer[1] << 16;
} else if (ExtraByteCount == 3) {
LastWord = ExtraBytesBuffer[0] << 24 |
ExtraBytesBuffer[1] << 16 |
ExtraBytesBuffer[2] << 8;
if (extrabytecount == 1) {
lastword = extrabytesbuffer[0] << 24;
} else if (extrabytecount == 2) {
lastword = extrabytesbuffer[0] << 24 |
extrabytesbuffer[1] << 16;
} else if (extrabytecount == 3) {
lastword = extrabytesbuffer[0] << 24 |
extrabytesbuffer[1] << 16 |
extrabytesbuffer[2] << 8;
}
out_be32 (Emac.SendFifo.DataBaseAddress, LastWord);
out_be32 (emac.sendfifo.databaseaddress, lastword);
}
/* Loop on the MAC's status to wait for any pause to complete */
IntrStatus = in_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET);
while ((IntrStatus & XEM_EIR_XMIT_PAUSE_MASK) != 0) {
IntrStatus = in_be32 ((Emac.BaseAddress) +
intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET);
while ((intrstatus & XEM_EIR_XMIT_PAUSE_MASK) != 0) {
intrstatus = in_be32 ((emac.baseaddress) +
XIIF_V123B_IISR_OFFSET);
/* Clear the pause status from the transmit status register */
out_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET,
IntrStatus & XEM_EIR_XMIT_PAUSE_MASK);
out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET,
intrstatus & XEM_EIR_XMIT_PAUSE_MASK);
}
/*
* Set the MAC's transmit packet length register to tell it to transmit
*/
out_be32 (Emac.BaseAddress + XEM_TPLR_OFFSET, len);
out_be32 (emac.baseaddress + XEM_TPLR_OFFSET, len);
/*
* Loop on the MAC's status to wait for the transmit to complete.
* The transmit status is in the FIFO when the XMIT_DONE bit is set.
*/
do {
IntrStatus = in_be32 ((Emac.BaseAddress) +
intrstatus = in_be32 ((emac.baseaddress) +
XIIF_V123B_IISR_OFFSET);
}
while ((IntrStatus & XEM_EIR_XMIT_DONE_MASK) == 0);
while ((intrstatus & XEM_EIR_XMIT_DONE_MASK) == 0);
XmitStatus = in_be32 (Emac.BaseAddress + XEM_TSR_OFFSET);
xmitstatus = in_be32 (emac.baseaddress + XEM_TSR_OFFSET);
if (IntrStatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK |
if (intrstatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK |
XEM_EIR_XMIT_LFIFO_OVER_MASK)) {
#ifdef DEBUG
puts ("Transmitting overrun error\n");
#endif
return 0;
} else if (IntrStatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK |
} else if (intrstatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK |
XEM_EIR_XMIT_LFIFO_UNDER_MASK)) {
#ifdef DEBUG
puts ("Transmitting underrun error\n");
@ -249,15 +251,15 @@ int eth_send(volatile void *ptr, int len)
}
/* Clear the interrupt status register of transmit statuses */
out_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET,
IntrStatus & XEM_EIR_XMIT_ALL_MASK);
out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET,
intrstatus & XEM_EIR_XMIT_ALL_MASK);
/*
* Collision errors are stored in the transmit status register
* instead of the interrupt status register
*/
if ((XmitStatus & XEM_TSR_EXCESS_DEFERRAL_MASK) ||
(XmitStatus & XEM_TSR_LATE_COLLISION_MASK)) {
if ((xmitstatus & XEM_TSR_EXCESS_DEFERRAL_MASK) ||
(xmitstatus & XEM_TSR_LATE_COLLISION_MASK)) {
#ifdef DEBUG
puts ("Transmitting collision error\n");
#endif
@ -268,17 +270,17 @@ int eth_send(volatile void *ptr, int len)
int eth_rx(void)
{
u32 PktLength;
u32 IntrStatus;
u32 FifoCount;
u32 WordCount;
u32 ExtraByteCount;
u32 LastWord;
u8 *ExtraBytesBuffer;
u32 pktlength;
u32 intrstatus;
u32 fifocount;
u32 wordcount;
u32 extrabytecount;
u32 lastword;
u8 *extrabytesbuffer;
if (in_be32 (Emac.RecvFifo.RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET)
if (in_be32 (emac.recvfifo.regbaseaddress + XPF_COUNT_STATUS_REG_OFFSET)
& XPF_DEADLOCK_MASK) {
out_be32 (Emac.RecvFifo.RegBaseAddress, XPF_RESET_FIFO_MASK);
out_be32 (emac.recvfifo.regbaseaddress, XPF_RESET_FIFO_MASK);
#ifdef DEBUG
puts ("Receiving FIFO deadlock\n");
#endif
@ -286,17 +288,18 @@ int eth_rx(void)
}
/*
* Get the interrupt status to know what happened (whether an error occurred
* and/or whether frames have been received successfully). When clearing the
* intr status register, clear only statuses that pertain to receive.
* Get the interrupt status to know what happened (whether an error
* occurred and/or whether frames have been received successfully).
* When clearing the intr status register, clear only statuses that
* pertain to receive.
*/
IntrStatus = in_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET);
intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET);
/*
* Before reading from the length FIFO, make sure the length FIFO is not
* empty. We could cause an underrun error if we try to read from an
* empty FIFO.
*/
if (!(IntrStatus & XEM_EIR_RECV_DONE_MASK)) {
if (!(intrstatus & XEM_EIR_RECV_DONE_MASK)) {
#ifdef DEBUG
/* puts("Receiving FIFO is empty\n"); */
#endif
@ -307,8 +310,8 @@ int eth_rx(void)
* Determine, from the MAC, the length of the next packet available
* in the data FIFO (there should be a non-zero length here)
*/
PktLength = in_be32 (Emac.BaseAddress + XEM_RPLR_OFFSET);
if (!PktLength) {
pktlength = in_be32 (emac.baseaddress + XEM_RPLR_OFFSET);
if (!pktlength) {
return 0;
}
@ -320,53 +323,53 @@ int eth_rx(void)
* in the IPIF, which means it may indicate a non-empty condition even
* though there is something in the FIFO.
*/
out_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET,
out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET,
XEM_EIR_RECV_DONE_MASK);
FifoCount = in_be32 (Emac.RecvFifo.RegBaseAddress +
fifocount = in_be32 (emac.recvfifo.regbaseaddress +
XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK;
if ((FifoCount * 4) < PktLength) {
if ((fifocount * 4) < pktlength) {
#ifdef DEBUG
puts ("Receiving FIFO is smaller than packet size.\n");
#endif
return 0;
}
WordCount = PktLength >> 2;
ExtraByteCount = PktLength & 0x3;
wordcount = pktlength >> 2;
extrabytecount = pktlength & 0x3;
for (FifoCount = 0; FifoCount < WordCount; FifoCount++) {
etherrxbuff[FifoCount] =
in_be32 (Emac.RecvFifo.DataBaseAddress);
for (fifocount = 0; fifocount < wordcount; fifocount++) {
etherrxbuff[fifocount] =
in_be32 (emac.recvfifo.databaseaddress);
}
/*
* if there are extra bytes to handle, read the last word from the FIFO
* and insert the extra bytes into the buffer
*/
if (ExtraByteCount > 0) {
ExtraBytesBuffer = (u8 *) (etherrxbuff + WordCount);
if (extrabytecount > 0) {
extrabytesbuffer = (u8 *) (etherrxbuff + wordcount);
LastWord = in_be32 (Emac.RecvFifo.DataBaseAddress);
lastword = in_be32 (emac.recvfifo.databaseaddress);
/*
* one extra byte in the last word, put the byte into the next
* location of the buffer, bytes in a word of the FIFO are
* ordered from most significant byte to least
*/
if (ExtraByteCount == 1) {
ExtraBytesBuffer[0] = (u8) (LastWord >> 24);
} else if (ExtraByteCount == 2) {
ExtraBytesBuffer[0] = (u8) (LastWord >> 24);
ExtraBytesBuffer[1] = (u8) (LastWord >> 16);
} else if (ExtraByteCount == 3) {
ExtraBytesBuffer[0] = (u8) (LastWord >> 24);
ExtraBytesBuffer[1] = (u8) (LastWord >> 16);
ExtraBytesBuffer[2] = (u8) (LastWord >> 8);
if (extrabytecount == 1) {
extrabytesbuffer[0] = (u8) (lastword >> 24);
} else if (extrabytecount == 2) {
extrabytesbuffer[0] = (u8) (lastword >> 24);
extrabytesbuffer[1] = (u8) (lastword >> 16);
} else if (extrabytecount == 3) {
extrabytesbuffer[0] = (u8) (lastword >> 24);
extrabytesbuffer[1] = (u8) (lastword >> 16);
extrabytesbuffer[2] = (u8) (lastword >> 8);
}
}
NetReceive((uchar *)etherrxbuff, PktLength);
NetReceive((uchar *)etherrxbuff, pktlength);
return 1;
}
#endif

View File

@ -26,16 +26,16 @@
*/
typedef struct {
u32 RegBaseAddress; /* Base address of registers */
u32 DataBaseAddress; /* Base address of data for FIFOs */
} XPacketFifoV100b;
u32 regbaseaddress; /* Base address of registers */
u32 databaseaddress; /* Base address of data for FIFOs */
} xpacketfifov100b;
typedef struct {
u32 BaseAddress; /* Base address (of IPIF) */
u32 IsStarted; /* Device is currently started 0-no, 1-yes */
XPacketFifoV100b RecvFifo; /* FIFO used to receive frames */
XPacketFifoV100b SendFifo; /* FIFO used to send frames */
} XEmac;
u32 baseaddress; /* Base address (of IPIF) */
u32 isstarted; /* Device is currently started 0-no, 1-yes */
xpacketfifov100b recvfifo; /* FIFO used to receive frames */
xpacketfifov100b sendfifo; /* FIFO used to send frames */
} xemac;
#define XIIF_V123B_IISR_OFFSET 32UL /* IP interrupt status register */
#define XIIF_V123B_RESET_MASK 0xAUL
@ -66,10 +66,14 @@ typedef struct {
#define XEM_PFIFO_OFFSET 0x2000UL
#define XEM_PFIFO_TXREG_OFFSET (XEM_PFIFO_OFFSET + 0x0) /* Tx registers */
#define XEM_PFIFO_RXREG_OFFSET (XEM_PFIFO_OFFSET + 0x10) /* Rx registers */
#define XEM_PFIFO_TXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x100) /* Tx keyhole */
#define XEM_PFIFO_RXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x200) /* Rx keyhole */
/* Tx registers */
#define XEM_PFIFO_TXREG_OFFSET (XEM_PFIFO_OFFSET + 0x0)
/* Rx registers */
#define XEM_PFIFO_RXREG_OFFSET (XEM_PFIFO_OFFSET + 0x10)
/* Tx keyhole */
#define XEM_PFIFO_TXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x100)
/* Rx keyhole */
#define XEM_PFIFO_RXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x200)
/*
@ -82,46 +86,63 @@ typedef struct {
XEM_EIR_XMIT_SFIFO_EMPTY_MASK |\
XEM_EIR_XMIT_LFIFO_FULL_MASK)
#define XEM_EIR_XMIT_DONE_MASK 0x00000001UL /* Xmit complete */
#define XEM_EIR_RECV_DONE_MASK 0x00000002UL /* Recv complete */
#define XEM_EIR_XMIT_ERROR_MASK 0x00000004UL /* Xmit error */
#define XEM_EIR_RECV_ERROR_MASK 0x00000008UL /* Recv error */
#define XEM_EIR_XMIT_SFIFO_EMPTY_MASK 0x00000010UL /* Xmit status fifo empty */
#define XEM_EIR_RECV_LFIFO_EMPTY_MASK 0x00000020UL /* Recv length fifo empty */
#define XEM_EIR_XMIT_LFIFO_FULL_MASK 0x00000040UL /* Xmit length fifo full */
#define XEM_EIR_RECV_LFIFO_OVER_MASK 0x00000080UL /* Recv length fifo
* overrun */
#define XEM_EIR_RECV_LFIFO_UNDER_MASK 0x00000100UL /* Recv length fifo
* underrun */
#define XEM_EIR_XMIT_SFIFO_OVER_MASK 0x00000200UL /* Xmit status fifo
* overrun */
#define XEM_EIR_XMIT_SFIFO_UNDER_MASK 0x00000400UL /* Transmit status fifo
* underrun */
#define XEM_EIR_XMIT_LFIFO_OVER_MASK 0x00000800UL /* Transmit length fifo
* overrun */
#define XEM_EIR_XMIT_LFIFO_UNDER_MASK 0x00001000UL /* Transmit length fifo
* underrun */
#define XEM_EIR_XMIT_PAUSE_MASK 0x00002000UL /* Transmit pause pkt
* received */
/* Xmit complete */
#define XEM_EIR_XMIT_DONE_MASK 0x00000001UL
/* Recv complete */
#define XEM_EIR_RECV_DONE_MASK 0x00000002UL
/* Xmit error */
#define XEM_EIR_XMIT_ERROR_MASK 0x00000004UL
/* Recv error */
#define XEM_EIR_RECV_ERROR_MASK 0x00000008UL
/* Xmit status fifo empty */
#define XEM_EIR_XMIT_SFIFO_EMPTY_MASK 0x00000010UL
/* Recv length fifo empty */
#define XEM_EIR_RECV_LFIFO_EMPTY_MASK 0x00000020UL
/* Xmit length fifo full */
#define XEM_EIR_XMIT_LFIFO_FULL_MASK 0x00000040UL
/* Recv length fifo overrun */
#define XEM_EIR_RECV_LFIFO_OVER_MASK 0x00000080UL
/* Recv length fifo underrun */
#define XEM_EIR_RECV_LFIFO_UNDER_MASK 0x00000100UL
/* Xmit status fifo overrun */
#define XEM_EIR_XMIT_SFIFO_OVER_MASK 0x00000200UL
/* Transmit status fifo underrun */
#define XEM_EIR_XMIT_SFIFO_UNDER_MASK 0x00000400UL
/* Transmit length fifo overrun */
#define XEM_EIR_XMIT_LFIFO_OVER_MASK 0x00000800UL
/* Transmit length fifo underrun */
#define XEM_EIR_XMIT_LFIFO_UNDER_MASK 0x00001000UL
/* Transmit pause pkt received */
#define XEM_EIR_XMIT_PAUSE_MASK 0x00002000UL
/*
* EMAC Control Register (ECR)
*/
#define XEM_ECR_FULL_DUPLEX_MASK 0x80000000UL /* Full duplex mode */
#define XEM_ECR_XMIT_RESET_MASK 0x40000000UL /* Reset transmitter */
#define XEM_ECR_XMIT_ENABLE_MASK 0x20000000UL /* Enable transmitter */
#define XEM_ECR_RECV_RESET_MASK 0x10000000UL /* Reset receiver */
#define XEM_ECR_RECV_ENABLE_MASK 0x08000000UL /* Enable receiver */
#define XEM_ECR_PHY_ENABLE_MASK 0x04000000UL /* Enable PHY */
#define XEM_ECR_XMIT_PAD_ENABLE_MASK 0x02000000UL /* Enable xmit pad
* insert */
#define XEM_ECR_XMIT_FCS_ENABLE_MASK 0x01000000UL /* Enable xmit FCS
* insert */
#define XEM_ECR_UNICAST_ENABLE_MASK 0x00020000UL /* Enable unicast
* addr */
#define XEM_ECR_BROAD_ENABLE_MASK 0x00008000UL /* Enable broadcast
* addr */
/* Full duplex mode */
#define XEM_ECR_FULL_DUPLEX_MASK 0x80000000UL
/* Reset transmitter */
#define XEM_ECR_XMIT_RESET_MASK 0x40000000UL
/* Enable transmitter */
#define XEM_ECR_XMIT_ENABLE_MASK 0x20000000UL
/* Reset receiver */
#define XEM_ECR_RECV_RESET_MASK 0x10000000UL
/* Enable receiver */
#define XEM_ECR_RECV_ENABLE_MASK 0x08000000UL
/* Enable PHY */
#define XEM_ECR_PHY_ENABLE_MASK 0x04000000UL
/* Enable xmit pad insert */
#define XEM_ECR_XMIT_PAD_ENABLE_MASK 0x02000000UL
/* Enable xmit FCS insert */
#define XEM_ECR_XMIT_FCS_ENABLE_MASK 0x01000000UL
/* Enable unicast addr */
#define XEM_ECR_UNICAST_ENABLE_MASK 0x00020000UL
/* Enable broadcast addr */
#define XEM_ECR_BROAD_ENABLE_MASK 0x00008000UL
/* Transmit Status Register (TSR) */
#define XEM_TSR_EXCESS_DEFERRAL_MASK 0x80000000UL /* Transmit excess deferral */
#define XEM_TSR_LATE_COLLISION_MASK 0x01000000UL /* Transmit late collision */
/*
* Transmit Status Register (TSR)
*/
/* Transmit excess deferral */
#define XEM_TSR_EXCESS_DEFERRAL_MASK 0x80000000UL
/* Transmit late collision */
#define XEM_TSR_LATE_COLLISION_MASK 0x01000000UL

View File

@ -64,76 +64,73 @@
#define XEL_RSR_RECV_IE_MASK 0x00000008UL
typedef struct {
unsigned int BaseAddress; /* Base address for device (IPIF) */
unsigned int NextTxBufferToUse; /* Next TX buffer to write to */
unsigned int NextRxBufferToUse; /* Next RX buffer to read from */
unsigned char DeviceId; /* Unique ID of device - for future */
} XEmacLite;
unsigned int baseaddress; /* Base address for device (IPIF) */
unsigned int nexttxbuffertouse; /* Next TX buffer to write to */
unsigned int nextrxbuffertouse; /* Next RX buffer to read from */
unsigned char deviceid; /* Unique ID of device - for future */
} xemaclite;
static XEmacLite EmacLite;
static xemaclite emaclite;
static char etherrxbuff[PKTSIZE_ALIGN]; /* Receive buffer */
static char etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
/* hardcoded MAC address for the Xilinx EMAC Core when env is nowhere*/
#ifdef CFG_ENV_IS_NOWHERE
static u8 EMACAddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 };
static u8 emacaddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 };
#endif
void XEmacLite_AlignedRead (u32 * SrcPtr, void *DestPtr, unsigned ByteCount)
void xemaclite_alignedread (u32 * srcptr, void *destptr, unsigned bytecount)
{
unsigned i;
unsigned Length = ByteCount;
u32 AlignBuffer;
u32 *To32Ptr;
u32 *From32Ptr;
u8 *To8Ptr;
u8 *From8Ptr;
unsigned int i;
u32 alignbuffer;
u32 *to32ptr;
u32 *from32ptr;
u8 *to8ptr;
u8 *from8ptr;
From32Ptr = (u32 *) SrcPtr;
from32ptr = (u32 *) srcptr;
/* Word aligned buffer, no correction needed. */
To32Ptr = (u32 *) DestPtr;
while (Length > 3) {
*To32Ptr++ = *From32Ptr++;
Length -= 4;
to32ptr = (u32 *) destptr;
while (bytecount > 3) {
*to32ptr++ = *from32ptr++;
bytecount -= 4;
}
To8Ptr = (u8 *) To32Ptr;
to8ptr = (u8 *) to32ptr;
AlignBuffer = *From32Ptr++;
From8Ptr = (u8 *) & AlignBuffer;
alignbuffer = *from32ptr++;
from8ptr = (u8 *) & alignbuffer;
for (i = 0; i < Length; i++) {
*To8Ptr++ = *From8Ptr++;
for (i = 0; i < bytecount; i++) {
*to8ptr++ = *from8ptr++;
}
}
void XEmacLite_AlignedWrite (void *SrcPtr, u32 * DestPtr, unsigned ByteCount)
void xemaclite_alignedwrite (void *srcptr, u32 destptr, unsigned bytecount)
{
unsigned i;
unsigned Length = ByteCount;
u32 AlignBuffer;
u32 *To32Ptr;
u32 *From32Ptr;
u8 *To8Ptr;
u8 *From8Ptr;
To32Ptr = DestPtr;
u32 alignbuffer;
u32 *to32ptr = (u32 *) destptr;
u32 *from32ptr;
u8 *to8ptr;
u8 *from8ptr;
From32Ptr = (u32 *) SrcPtr;
while (Length > 3) {
from32ptr = (u32 *) srcptr;
while (bytecount > 3) {
*To32Ptr++ = *From32Ptr++;
Length -= 4;
*to32ptr++ = *from32ptr++;
bytecount -= 4;
}
AlignBuffer = 0;
To8Ptr = (u8 *) & AlignBuffer;
From8Ptr = (u8 *) From32Ptr;
alignbuffer = 0;
to8ptr = (u8 *) & alignbuffer;
from8ptr = (u8 *) from32ptr;
for (i = 0; i < Length; i++) {
*To8Ptr++ = *From8Ptr++;
for (i = 0; i < bytecount; i++) {
*to8ptr++ = *from8ptr++;
}
*To32Ptr++ = AlignBuffer;
*to32ptr++ = alignbuffer;
}
void eth_halt (void)
@ -148,37 +145,38 @@ int eth_init (bd_t * bis)
#ifdef DEBUG
puts ("EmacLite Initialization Started\n");
#endif
memset (&EmacLite, 0, sizeof (XEmacLite));
EmacLite.BaseAddress = XILINX_EMACLITE_BASEADDR;
memset (&emaclite, 0, sizeof (xemaclite));
emaclite.baseaddress = XILINX_EMACLITE_BASEADDR;
if (!getenv("ethaddr")) {
memcpy(bis->bi_enetaddr, emacaddr, ENET_ADDR_LENGTH);
}
#ifdef CFG_ENV_IS_NOWHERE
memcpy (bis->bi_enetaddr, EMACAddr, ENET_ADDR_LENGTH);
#endif
/*
* TX - TX_PING & TX_PONG initialization
*/
/* Restart PING TX */
out_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET, 0);
out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, 0);
/* Copy MAC address */
XEmacLite_AlignedWrite (bis->bi_enetaddr,
EmacLite.BaseAddress, ENET_ADDR_LENGTH);
xemaclite_alignedwrite (bis->bi_enetaddr,
emaclite.baseaddress, ENET_ADDR_LENGTH);
/* Set the length */
out_be32 (EmacLite.BaseAddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
out_be32 (emaclite.baseaddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
/* Update the MAC address in the EMAC Lite */
out_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR);
out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR);
/* Wait for EMAC Lite to finish with the MAC address update */
while ((in_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET) &
while ((in_be32 (emaclite.baseaddress + XEL_TSR_OFFSET) &
XEL_TSR_PROG_MAC_ADDR) != 0) ;
#ifdef XILINX_EMACLITE_TX_PING_PONG
/* The same operation with PONG TX */
out_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0);
XEmacLite_AlignedWrite (bis->bi_enetaddr,
EmacLite.BaseAddress + XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH);
out_be32 (EmacLite.BaseAddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
out_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET,
out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0);
xemaclite_alignedwrite (bis->bi_enetaddr, emaclite.baseaddress +
XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH);
out_be32 (emaclite.baseaddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET,
XEL_TSR_PROG_MAC_ADDR);
while ((in_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET +
while ((in_be32 (emaclite.baseaddress + XEL_TSR_OFFSET +
XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0) ;
#endif
@ -186,9 +184,9 @@ int eth_init (bd_t * bis)
* RX - RX_PING & RX_PONG initialization
*/
/* Write out the value to flush the RX buffer */
out_be32 (EmacLite.BaseAddress + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK);
out_be32 (emaclite.baseaddress + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK);
#ifdef XILINX_EMACLITE_RX_PING_PONG
out_be32 (EmacLite.BaseAddress + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET,
out_be32 (emaclite.baseaddress + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET,
XEL_RSR_RECV_IE_MASK);
#endif
@ -198,39 +196,39 @@ int eth_init (bd_t * bis)
return 0;
}
int XEmacLite_TxBufferAvailable (XEmacLite * InstancePtr)
int xemaclite_txbufferavailable (xemaclite * instanceptr)
{
u32 Register;
u32 TxPingBusy;
u32 TxPongBusy;
u32 reg;
u32 txpingbusy;
u32 txpongbusy;
/*
* Read the other buffer register
* and determine if the other buffer is available
*/
Register = in_be32 (InstancePtr->BaseAddress +
InstancePtr->NextTxBufferToUse + 0);
TxPingBusy = ((Register & XEL_TSR_XMIT_BUSY_MASK) ==
reg = in_be32 (instanceptr->baseaddress +
instanceptr->nexttxbuffertouse + 0);
txpingbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
XEL_TSR_XMIT_BUSY_MASK);
Register = in_be32 (InstancePtr->BaseAddress +
(InstancePtr->NextTxBufferToUse ^ XEL_TSR_OFFSET) + 0);
TxPongBusy = ((Register & XEL_TSR_XMIT_BUSY_MASK) ==
reg = in_be32 (instanceptr->baseaddress +
(instanceptr->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0);
txpongbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
XEL_TSR_XMIT_BUSY_MASK);
return (!(TxPingBusy && TxPongBusy));
return (!(txpingbusy && txpongbusy));
}
int eth_send (volatile void *ptr, int len) {
unsigned int Register;
unsigned int BaseAddress;
unsigned int reg;
unsigned int baseaddress;
unsigned maxtry = 1000;
if (len > ENET_MAX_MTU)
len = ENET_MAX_MTU;
while (!XEmacLite_TxBufferAvailable (&EmacLite) && maxtry) {
while (!xemaclite_txbufferavailable (&emaclite) && maxtry) {
udelay (10);
maxtry--;
}
@ -238,62 +236,62 @@ int eth_send (volatile void *ptr, int len) {
if (!maxtry) {
printf ("Error: Timeout waiting for ethernet TX buffer\n");
/* Restart PING TX */
out_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET, 0);
out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, 0);
#ifdef XILINX_EMACLITE_TX_PING_PONG
out_be32 (EmacLite.BaseAddress + XEL_TSR_OFFSET +
out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET +
XEL_BUFFER_OFFSET, 0);
#endif
return 0;
}
/* Determine the expected TX buffer address */
BaseAddress = (EmacLite.BaseAddress + EmacLite.NextTxBufferToUse);
baseaddress = (emaclite.baseaddress + emaclite.nexttxbuffertouse);
/* Determine if the expected buffer address is empty */
Register = in_be32 (BaseAddress + XEL_TSR_OFFSET);
if (((Register & XEL_TSR_XMIT_BUSY_MASK) == 0)
&& ((in_be32 ((BaseAddress) + XEL_TSR_OFFSET)
reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
&& ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
#ifdef XILINX_EMACLITE_TX_PING_PONG
EmacLite.NextTxBufferToUse ^= XEL_BUFFER_OFFSET;
emaclite.nexttxbuffertouse ^= XEL_BUFFER_OFFSET;
#endif
#ifdef DEBUG
printf ("Send packet from 0x%x\n", BaseAddress);
printf ("Send packet from 0x%x\n", baseaddress);
#endif
/* Write the frame to the buffer */
XEmacLite_AlignedWrite (ptr, (u32 *) BaseAddress, len);
out_be32 (BaseAddress + XEL_TPLR_OFFSET,(len &
xemaclite_alignedwrite ((void *) ptr, baseaddress, len);
out_be32 (baseaddress + XEL_TPLR_OFFSET,(len &
(XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)));
Register = in_be32 (BaseAddress + XEL_TSR_OFFSET);
Register |= XEL_TSR_XMIT_BUSY_MASK;
if ((Register & XEL_TSR_XMIT_IE_MASK) != 0) {
Register |= XEL_TSR_XMIT_ACTIVE_MASK;
reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
reg |= XEL_TSR_XMIT_BUSY_MASK;
if ((reg & XEL_TSR_XMIT_IE_MASK) != 0) {
reg |= XEL_TSR_XMIT_ACTIVE_MASK;
}
out_be32 (BaseAddress + XEL_TSR_OFFSET, Register);
out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
return 1;
}
#ifdef XILINX_EMACLITE_TX_PING_PONG
/* Switch to second buffer */
BaseAddress ^= XEL_BUFFER_OFFSET;
baseaddress ^= XEL_BUFFER_OFFSET;
/* Determine if the expected buffer address is empty */
Register = in_be32 (BaseAddress + XEL_TSR_OFFSET);
if (((Register & XEL_TSR_XMIT_BUSY_MASK) == 0)
&& ((in_be32 ((BaseAddress) + XEL_TSR_OFFSET)
reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
&& ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
#ifdef DEBUG
printf ("Send packet from 0x%x\n", BaseAddress);
printf ("Send packet from 0x%x\n", baseaddress);
#endif
/* Write the frame to the buffer */
XEmacLite_AlignedWrite (ptr, (u32 *) BaseAddress, len);
out_be32 (BaseAddress + XEL_TPLR_OFFSET,(len &
xemaclite_alignedwrite ((void *) ptr, baseaddress, len);
out_be32 (baseaddress + XEL_TPLR_OFFSET,(len &
(XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)));
Register = in_be32 (BaseAddress + XEL_TSR_OFFSET);
Register |= XEL_TSR_XMIT_BUSY_MASK;
if ((Register & XEL_TSR_XMIT_IE_MASK) != 0) {
Register |= XEL_TSR_XMIT_ACTIVE_MASK;
reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
reg |= XEL_TSR_XMIT_BUSY_MASK;
if ((reg & XEL_TSR_XMIT_IE_MASK) != 0) {
reg |= XEL_TSR_XMIT_ACTIVE_MASK;
}
out_be32 (BaseAddress + XEL_TSR_OFFSET, Register);
out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
return 1;
}
#endif
@ -303,50 +301,50 @@ int eth_send (volatile void *ptr, int len) {
int eth_rx (void)
{
unsigned int Length;
unsigned int Register;
unsigned int BaseAddress;
unsigned int length;
unsigned int reg;
unsigned int baseaddress;
BaseAddress = EmacLite.BaseAddress + EmacLite.NextRxBufferToUse;
Register = in_be32 (BaseAddress + XEL_RSR_OFFSET);
baseaddress = emaclite.baseaddress + emaclite.nextrxbuffertouse;
reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
#ifdef DEBUG
printf ("Testing data at address 0x%x\n", BaseAddress);
printf ("Testing data at address 0x%x\n", baseaddress);
#endif
if ((Register & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
#ifdef XILINX_EMACLITE_RX_PING_PONG
EmacLite.NextRxBufferToUse ^= XEL_BUFFER_OFFSET;
emaclite.nextrxbuffertouse ^= XEL_BUFFER_OFFSET;
#endif
} else {
#ifndef XILINX_EMACLITE_RX_PING_PONG
#ifdef DEBUG
printf ("No data was available - address 0x%x\n", BaseAddress);
printf ("No data was available - address 0x%x\n", baseaddress);
#endif
return 0;
#else
BaseAddress ^= XEL_BUFFER_OFFSET;
Register = in_be32 (BaseAddress + XEL_RSR_OFFSET);
if ((Register & XEL_RSR_RECV_DONE_MASK) !=
baseaddress ^= XEL_BUFFER_OFFSET;
reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
if ((reg & XEL_RSR_RECV_DONE_MASK) !=
XEL_RSR_RECV_DONE_MASK) {
#ifdef DEBUG
printf ("No data was available - address 0x%x\n",
BaseAddress);
baseaddress);
#endif
return 0;
}
#endif
}
/* Get the length of the frame that arrived */
switch(((in_be32(BaseAddress + XEL_RXBUFF_OFFSET + 0xC)) &
switch(((in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC)) &
0xFFFF0000 ) >> 16) {
case 0x806:
Length = 42 + 20; /* FIXME size of ARP */
length = 42 + 20; /* FIXME size of ARP */
#ifdef DEBUG
puts ("ARP Packet\n");
#endif
break;
case 0x800:
Length = 14 + 14 +
(((in_be32(BaseAddress + XEL_RXBUFF_OFFSET + 0x10)) &
length = 14 + 14 +
(((in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0x10)) &
0xFFFF0000) >> 16); /* FIXME size of IP packet */
#ifdef DEBUG
puts("IP Packet\n");
@ -356,22 +354,22 @@ int eth_rx (void)
#ifdef DEBUG
puts("Other Packet\n");
#endif
Length = ENET_MAX_MTU;
length = ENET_MAX_MTU;
break;
}
XEmacLite_AlignedRead ((BaseAddress + XEL_RXBUFF_OFFSET),
etherrxbuff, Length);
xemaclite_alignedread ((u32 *) (baseaddress + XEL_RXBUFF_OFFSET),
etherrxbuff, length);
/* Acknowledge the frame */
Register = in_be32 (BaseAddress + XEL_RSR_OFFSET);
Register &= ~XEL_RSR_RECV_DONE_MASK;
out_be32 (BaseAddress + XEL_RSR_OFFSET, Register);
reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
reg &= ~XEL_RSR_RECV_DONE_MASK;
out_be32 (baseaddress + XEL_RSR_OFFSET, reg);
#ifdef DEBUG
printf ("Packet receive from 0x%x, length %dB\n", BaseAddress, Length);
printf ("Packet receive from 0x%x, length %dB\n", baseaddress, length);
#endif
NetReceive ((uchar *) etherrxbuff, Length);
NetReceive ((uchar *) etherrxbuff, length);
return 1;
}