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ddr: altera: Zero DM IN delay in scc_mgr_zero_group() 

This one last set of delay configuration registers was not properly
zeroed out originally, fix it and zero them out.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
utp
Marek Vasut 2016-04-04 21:16:18 +02:00
parent f3f777cdf0
commit 70ed80af46
1 changed files with 13 additions and 3 deletions
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16
drivers/ddr/altera/sequencer.c
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@ -303,15 +303,22 @@ static void scc_mgr_set_dqs_en_delay(u32 read_group, u32 delay)
scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
}
static void scc_mgr_set_dq_in_delay(u32 dq_in_group, u32 delay)
{
scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
}
static void scc_mgr_set_dqs_io_in_delay(u32 delay)
{
scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs,
delay);
}
static void scc_mgr_set_dq_in_delay(u32 dq_in_group, u32 delay)
static void scc_mgr_set_dm_in_delay(u32 dm, u32 delay)
{
scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET,
rwcfg->mem_dq_per_write_dqs + 1 + dm,
delay);
}
static void scc_mgr_set_dq_out1_delay(u32 dq_in_group, u32 delay)
@ -584,8 +591,11 @@ static void scc_mgr_zero_group(const u32 write_group, const int out_only)
writel(0xff, &sdr_scc_mgr->dq_ena);
/* Zero all DM config settings. */
for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
if (!out_only)
scc_mgr_set_dm_in_delay(i, 0);
scc_mgr_set_dm_out1_delay(i, 0);
}
/* Multicast to all DM enables. */
writel(0xff, &sdr_scc_mgr->dm_ena);