x86: broadwell: Add power-control support
Broadwell requires quite a bit of power-management setup. Add code to set this up correctly. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com> [squashed in http://patchwork.ozlabs.org/patch/598373/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>utp
Simon Glass
Bin Meng
parent
e7994858ec
commit
71a8f2080b
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@ -10,5 +10,6 @@ obj-y += lpc.o
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obj-y += northbridge.o
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obj-y += pch.o
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obj-y += pinctrl_broadwell.o
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obj-y += power_state.o
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obj-y += refcode.o
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obj-y += sata.o
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@ -0,0 +1,90 @@
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/*
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* From coreboot src/soc/intel/broadwell/romstage/power_state.c
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*
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* Copyright (C) 2016 Google, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/io.h>
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#include <asm/intel_regs.h>
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#include <asm/arch/iomap.h>
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#include <asm/arch/lpc.h>
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#include <asm/arch/pch.h>
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#include <asm/arch/pm.h>
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/* Return 0, 3, or 5 to indicate the previous sleep state. */
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static int prev_sleep_state(struct chipset_power_state *ps)
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{
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/* Default to S0. */
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int prev_sleep_state = SLEEP_STATE_S0;
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if (ps->pm1_sts & WAK_STS) {
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switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) {
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#if CONFIG_HAVE_ACPI_RESUME
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case SLP_TYP_S3:
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prev_sleep_state = SLEEP_STATE_S3;
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break;
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#endif
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case SLP_TYP_S5:
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prev_sleep_state = SLEEP_STATE_S5;
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break;
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}
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/* Clear SLP_TYP. */
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outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
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}
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if (ps->gen_pmcon3 & (PWR_FLR | SUS_PWR_FLR))
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prev_sleep_state = SLEEP_STATE_S5;
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return prev_sleep_state;
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}
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static void dump_power_state(struct chipset_power_state *ps)
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{
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debug("PM1_STS: %04x\n", ps->pm1_sts);
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debug("PM1_EN: %04x\n", ps->pm1_en);
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debug("PM1_CNT: %08x\n", ps->pm1_cnt);
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debug("TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts);
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debug("GPE0_STS: %08x %08x %08x %08x\n",
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ps->gpe0_sts[0], ps->gpe0_sts[1],
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ps->gpe0_sts[2], ps->gpe0_sts[3]);
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debug("GPE0_EN: %08x %08x %08x %08x\n",
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ps->gpe0_en[0], ps->gpe0_en[1],
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ps->gpe0_en[2], ps->gpe0_en[3]);
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debug("GEN_PMCON: %04x %04x %04x\n",
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ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3);
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debug("Previous Sleep State: S%d\n",
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ps->prev_sleep_state);
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}
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/* Fill power state structure from ACPI PM registers */
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void power_state_get(struct udevice *pch_dev, struct chipset_power_state *ps)
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{
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ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
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ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN);
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ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
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ps->tco1_sts = inw(ACPI_BASE_ADDRESS + TCO1_STS);
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ps->tco2_sts = inw(ACPI_BASE_ADDRESS + TCO2_STS);
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ps->gpe0_sts[0] = inl(ACPI_BASE_ADDRESS + GPE0_STS(0));
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ps->gpe0_sts[1] = inl(ACPI_BASE_ADDRESS + GPE0_STS(1));
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ps->gpe0_sts[2] = inl(ACPI_BASE_ADDRESS + GPE0_STS(2));
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ps->gpe0_sts[3] = inl(ACPI_BASE_ADDRESS + GPE0_STS(3));
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ps->gpe0_en[0] = inl(ACPI_BASE_ADDRESS + GPE0_EN(0));
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ps->gpe0_en[1] = inl(ACPI_BASE_ADDRESS + GPE0_EN(1));
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ps->gpe0_en[2] = inl(ACPI_BASE_ADDRESS + GPE0_EN(2));
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ps->gpe0_en[3] = inl(ACPI_BASE_ADDRESS + GPE0_EN(3));
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dm_pci_read_config16(pch_dev, GEN_PMCON_1, &ps->gen_pmcon1);
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dm_pci_read_config16(pch_dev, GEN_PMCON_2, &ps->gen_pmcon2);
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dm_pci_read_config16(pch_dev, GEN_PMCON_3, &ps->gen_pmcon3);
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ps->prev_sleep_state = prev_sleep_state(ps);
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dump_power_state(ps);
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}
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@ -0,0 +1,129 @@
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/*
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* From coreboot src/soc/intel/broadwell/include/soc/pm.h
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*
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* Copyright (C) 2016 Google, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef __ASM_ARCH_PM_H
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#define __ASM_ARCH_PM_H
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#define PM1_STS 0x00
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#define WAK_STS (1 << 15)
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#define PCIEXPWAK_STS (1 << 14)
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#define PRBTNOR_STS (1 << 11)
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#define RTC_STS (1 << 10)
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#define PWRBTN_STS (1 << 8)
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#define GBL_STS (1 << 5)
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#define BM_STS (1 << 4)
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#define TMROF_STS (1 << 0)
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#define PM1_EN 0x02
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#define PCIEXPWAK_DIS (1 << 14)
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#define RTC_EN (1 << 10)
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#define PWRBTN_EN (1 << 8)
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#define GBL_EN (1 << 5)
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#define TMROF_EN (1 << 0)
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#define PM1_CNT 0x04
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#define SLP_EN (1 << 13)
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#define SLP_TYP (7 << 10)
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#define SLP_TYP_SHIFT 10
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#define SLP_TYP_S0 0
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#define SLP_TYP_S1 1
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#define SLP_TYP_S3 5
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#define SLP_TYP_S4 6
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#define SLP_TYP_S5 7
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#define GBL_RLS (1 << 2)
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#define BM_RLD (1 << 1)
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#define SCI_EN (1 << 0)
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#define PM1_TMR 0x08
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#define SMI_EN 0x30
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#define XHCI_SMI_EN (1 << 31)
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#define ME_SMI_EN (1 << 30)
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#define GPIO_UNLOCK_SMI_EN (1 << 27)
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#define INTEL_USB2_EN (1 << 18)
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#define LEGACY_USB2_EN (1 << 17)
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#define PERIODIC_EN (1 << 14)
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#define TCO_EN (1 << 13)
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#define MCSMI_EN (1 << 11)
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#define BIOS_RLS (1 << 7)
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#define SWSMI_TMR_EN (1 << 6)
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#define APMC_EN (1 << 5)
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#define SLP_SMI_EN (1 << 4)
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#define LEGACY_USB_EN (1 << 3)
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#define BIOS_EN (1 << 2)
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#define EOS (1 << 1)
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#define GBL_SMI_EN (1 << 0)
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#define SMI_STS 0x34
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#define UPWRC 0x3c
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#define UPWRC_WS (1 << 8)
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#define UPWRC_WE (1 << 1)
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#define UPWRC_SMI (1 << 0)
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#define GPE_CNTL 0x42
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#define SWGPE_CTRL (1 << 1)
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#define DEVACT_STS 0x44
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#define PM2_CNT 0x50
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#define TCO1_CNT 0x60
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#define TCO_TMR_HLT (1 << 11)
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#define TCO1_STS 0x64
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#define DMISCI_STS (1 << 9)
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#define TCO2_STS 0x66
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#define TCO2_STS_SECOND_TO (1 << 1)
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#define GPE0_REG_MAX 4
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#define GPE0_REG_SIZE 32
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#define GPE0_STS(x) (0x80 + (x * 4))
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#define GPE_31_0 0 /* 0x80/0x90 = GPE[31:0] */
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#define GPE_63_32 1 /* 0x84/0x94 = GPE[63:32] */
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#define GPE_94_64 2 /* 0x88/0x98 = GPE[94:64] */
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#define GPE_STD 3 /* 0x8c/0x9c = Standard GPE */
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#define WADT_STS (1 << 18)
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#define GP27_STS (1 << 16)
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#define PME_B0_STS (1 << 13)
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#define ME_SCI_STS (1 << 12)
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#define PME_STS (1 << 11)
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#define BATLOW_STS (1 << 10)
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#define PCI_EXP_STS (1 << 9)
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#define SMB_WAK_STS (1 << 7)
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#define TCOSCI_STS (1 << 6)
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#define SWGPE_STS (1 << 2)
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#define HOT_PLUG_STS (1 << 1)
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#define GPE0_EN(x) (0x90 + (x * 4))
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#define WADT_en (1 << 18)
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#define GP27_EN (1 << 16)
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#define PME_B0_EN (1 << 13)
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#define ME_SCI_EN (1 << 12)
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#define PME_EN (1 << 11)
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#define BATLOW_EN (1 << 10)
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#define PCI_EXP_EN (1 << 9)
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#define TCOSCI_EN (1 << 6)
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#define SWGPE_EN (1 << 2)
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#define HOT_PLUG_EN (1 << 1)
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#define MAINBOARD_POWER_OFF 0
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#define MAINBOARD_POWER_ON 1
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#define MAINBOARD_POWER_KEEP 2
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#define SLEEP_STATE_S0 0
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#define SLEEP_STATE_S3 3
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#define SLEEP_STATE_S5 5
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struct chipset_power_state {
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uint16_t pm1_sts;
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uint16_t pm1_en;
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uint32_t pm1_cnt;
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uint16_t tco1_sts;
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uint16_t tco2_sts;
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uint32_t gpe0_sts[4];
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uint32_t gpe0_en[4];
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uint16_t gen_pmcon1;
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uint16_t gen_pmcon2;
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uint16_t gen_pmcon3;
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int prev_sleep_state;
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uint16_t hsio_version;
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uint16_t hsio_checksum;
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};
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void power_state_get(struct udevice *pch_dev, struct chipset_power_state *ps);
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#endif
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