85xx: Add setting of cache props in the device tree.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>utp
Kumar Gala
Andrew Fleming-AFLEMING
parent
4dbdb7681e
commit
730b2fcf6f
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@ -26,6 +26,7 @@
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#include <common.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <asm/processor.h>
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extern void ft_qe_setup(void *blob);
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#ifdef CONFIG_MP
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@ -77,6 +78,131 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
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}
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#endif
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#ifdef CONFIG_L2_CACHE
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/* return size in kilobytes */
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static inline u32 l2cache_size(void)
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{
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volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR;
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volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
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u32 ver = SVR_SOC_VER(get_svr());
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switch (l2siz_field) {
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case 0x0:
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break;
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case 0x1:
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if (ver == SVR_8540 || ver == SVR_8560 ||
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ver == SVR_8541 || ver == SVR_8541_E ||
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ver == SVR_8555 || ver == SVR_8555_E)
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return 128;
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else
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return 256;
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break;
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case 0x2:
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if (ver == SVR_8540 || ver == SVR_8560 ||
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ver == SVR_8541 || ver == SVR_8541_E ||
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ver == SVR_8555 || ver == SVR_8555_E)
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return 256;
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else
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return 512;
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break;
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case 0x3:
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return 1024;
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break;
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}
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return 0;
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}
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static inline void ft_fixup_l2cache(void *blob)
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{
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int len, off;
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u32 *ph;
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struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
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char compat_buf[38];
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const u32 line_size = 32;
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const u32 num_ways = 8;
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const u32 size = l2cache_size() * 1024;
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const u32 num_sets = size / (line_size * num_ways);
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off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
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if (off < 0) {
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debug("no cpu node fount\n");
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return;
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}
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ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
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if (ph == NULL) {
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debug("no next-level-cache property\n");
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return ;
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}
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off = fdt_node_offset_by_phandle(blob, *ph);
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if (off < 0) {
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printf("%s: %s\n", __func__, fdt_strerror(off));
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return ;
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}
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if (cpu) {
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len = sprintf(compat_buf, "fsl,mpc%s-l2-cache-controller",
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cpu->name);
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sprintf(&compat_buf[len + 1], "cache");
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}
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fdt_setprop(blob, off, "cache-unified", NULL, 0);
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fdt_setprop_cell(blob, off, "cache-block-size", line_size);
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fdt_setprop_cell(blob, off, "cache-line-size", line_size);
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fdt_setprop_cell(blob, off, "cache-size", size);
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fdt_setprop_cell(blob, off, "cache-sets", num_sets);
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fdt_setprop_cell(blob, off, "cache-level", 2);
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fdt_setprop(blob, off, "compatible", compat_buf, sizeof(compat_buf));
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}
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#else
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#define ft_fixup_l2cache(x)
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#endif
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static inline void ft_fixup_cache(void *blob)
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{
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int off;
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off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
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while (off != -FDT_ERR_NOTFOUND) {
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u32 l1cfg0 = mfspr(SPRN_L1CFG0);
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u32 l1cfg1 = mfspr(SPRN_L1CFG1);
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u32 isize, iline_size, inum_sets, inum_ways;
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u32 dsize, dline_size, dnum_sets, dnum_ways;
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/* d-side config */
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dsize = (l1cfg0 & 0x7ff) * 1024;
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dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1;
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dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32;
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dnum_sets = dsize / (dline_size * dnum_ways);
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fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size);
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fdt_setprop_cell(blob, off, "d-cache-line-size", dline_size);
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fdt_setprop_cell(blob, off, "d-cache-size", dsize);
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fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
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/* i-side config */
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isize = (l1cfg1 & 0x7ff) * 1024;
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inum_ways = ((l1cfg1 >> 11) & 0xff) + 1;
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iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32;
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inum_sets = isize / (iline_size * inum_ways);
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fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size);
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fdt_setprop_cell(blob, off, "i-cache-line-size", iline_size);
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fdt_setprop_cell(blob, off, "i-cache-size", isize);
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fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets);
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off = fdt_node_offset_by_prop_value(blob, off,
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"device_type", "cpu", 4);
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}
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ft_fixup_l2cache(blob);
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}
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void ft_cpu_setup(void *blob, bd_t *bd)
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{
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#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
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@ -114,4 +240,6 @@ void ft_cpu_setup(void *blob, bd_t *bd)
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#ifdef CONFIG_MP
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ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize);
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#endif
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ft_fixup_cache(blob);
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}
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