sh: Add support SH7710/SH7712
SH7710/SH7712 of SH3 CPU are supported. SH771X is called SH-Ether, and has the Ether controller in CPU. The driver of Ether is not included in this patch. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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@ -30,25 +30,20 @@
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#error "Default SCIF doesn't set....."
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#endif
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#if defined(CONFIG_SH3)
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/* There are SH7720's register */
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#define SCSMR (volatile unsigned short *)(SCIF_BASE + 0x0)
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#define SCBRR (volatile unsigned char *)(SCIF_BASE + 0x4)
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#define SCSCR (volatile unsigned short *)(SCIF_BASE + 0x8)
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#define SCFSR (volatile unsigned short *)(SCIF_BASE + 0x14) /* SCSSR */
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#define SCFCR (volatile unsigned short *)(SCIF_BASE + 0x18)
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#define SCFDR (volatile unsigned short *)(SCIF_BASE + 0x1C)
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#define SCFTDR (volatile unsigned char *)(SCIF_BASE + 0x20)
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#define SCFRDR (volatile unsigned char *)(SCIF_BASE + 0x24)
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/* Base register */
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#define SCSMR (vu_short *)(SCIF_BASE + 0x0)
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#define SCBRR (vu_char *)(SCIF_BASE + 0x4)
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#define SCSCR (vu_short *)(SCIF_BASE + 0x8)
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#define SCFCR (vu_short *)(SCIF_BASE + 0x18)
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#define SCFDR (vu_short *)(SCIF_BASE + 0x1C)
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#ifdef CONFIG_SH7720 /* SH7720 specific */
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#define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */
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#define SCFTDR (vu_char *)(SCIF_BASE + 0x20)
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#define SCFRDR (vu_char *)(SCIF_BASE + 0x24)
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#else
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#define SCSMR (vu_short *)(SCIF_BASE + 0x0)
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#define SCBRR (vu_char *)(SCIF_BASE + 0x4)
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#define SCSCR (vu_short *)(SCIF_BASE + 0x8)
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#define SCFTDR (vu_char *)(SCIF_BASE + 0xC)
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#define SCFSR (vu_short *)(SCIF_BASE + 0x10)
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#define SCFRDR (vu_char *)(SCIF_BASE + 0x14)
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#define SCFCR (vu_short *)(SCIF_BASE + 0x18)
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#define SCFDR (vu_short *)(SCIF_BASE + 0x1C)
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#endif
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#if defined(CONFIG_SH4A)
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@ -62,7 +57,11 @@
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#define SCLSR (vu_short *)(SCIF_BASE + 0x24)
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#define LSR_ORER 1
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#elif defined (CONFIG_SH3)
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#define SCLSR SCFSR /* SCSSR */
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#ifdef CONFIG_SH7720 /* SH7720 specific */
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# define SCLSR SCFSR /* SCSSR */
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#else
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# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
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#endif
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#define LSR_ORER 0x0200
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#endif
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@ -31,7 +31,9 @@
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#define CACHE_OC_NUM_ENTRIES 256
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#define CACHE_OC_ENTRY_SHIFT 4
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#if defined(CONFIG_CPU_SH7720)
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#if defined(CONFIG_CPU_SH7710)
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#include <asm/cpu_sh7710.h>
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#elif defined(CONFIG_CPU_SH7720)
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#include <asm/cpu_sh7720.h>
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#else
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#error "Unknown SH3 variant"
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64
include/asm-sh/cpu_sh7710.h
Normal file
64
include/asm-sh/cpu_sh7710.h
Normal file
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#ifndef _ASM_CPU_SH7710_H_
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#define _ASM_CPU_SH7710_H_
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#define CACHE_OC_NUM_WAYS 4
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#define CCR_CACHE_INIT 0x0000000D
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/* MMU and Cache control */
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#define MMUCR 0xFFFFFFE0
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#define CCR 0xFFFFFFEC
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/* PFC */
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#define PACR 0xA4050100
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#define PBCR 0xA4050102
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#define PCCR 0xA4050104
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#define PETCR 0xA4050106
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/* Port Data Registers */
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#define PADR 0xA4050120
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#define PBDR 0xA4050122
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#define PCDR 0xA4050124
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/* BSC */
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#define CMNCR 0xA4FD0000
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#define CS0BCR 0xA4FD0004
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#define CS2BCR 0xA4FD0008
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#define CS3BCR 0xA4FD000C
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#define CS4BCR 0xA4FD0010
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#define CS5ABCR 0xA4FD0014
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#define CS5BBCR 0xA4FD0018
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#define CS6ABCR 0xA4FD001C
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#define CS6BBCR 0xA4FD0020
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#define CS0WCR 0xA4FD0024
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#define CS2WCR 0xA4FD0028
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#define CS3WCR 0xA4FD002C
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#define CS4WCR 0xA4FD0030
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#define CS5AWCR 0xA4FD0034
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#define CS5BWCR 0xA4FD0038
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#define CS6AWCR 0xA4FD003C
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#define CS6BWCR 0xA4FD0040
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/* SDRAM controller */
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#define SDCR 0xA4FD0044
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#define RTCSR 0xA4FD0048
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#define RTCNT 0xA4FD004C
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#define RTCOR 0xA4FD0050
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/* SCIF */
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#define SCSMR_0 0xA4400000
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#define SCIF0_BASE SCSMR_0
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#define SCSMR_0 0xA4410000
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#define SCIF1_BASE SCSMR_1
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/* Timer */
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#define TSTR0 0xA412FE92
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#define TSTR TSTR0
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#define TCNT0 0xa412FE98
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#define TCR0 0xa412FE9C
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/* On chip oscillator circuits */
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#define FRQCR 0xA415FF80
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#define WTCNT 0xA415FF84
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#define WTCSR 0xA415FF86
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#endif /* _ASM_CPU_SH7710_H_ */
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