ARM: dts: uniphier: add PH1-LD20 SoC/board device tree sources
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>utp
Masahiro Yamada
parent
f6c65bc2fa
commit
7bdd155437
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@ -57,6 +57,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
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armada-xp-theadorable.dtb
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dtb-$(CONFIG_ARCH_UNIPHIER) += \
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uniphier-ph1-ld20-ref.dtb \
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uniphier-ph1-ld4-ref.dtb \
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uniphier-ph1-ld6b-ref.dtb \
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uniphier-ph1-pro4-ace.dtb \
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@ -0,0 +1,69 @@
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/*
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* Device Tree Source for UniPhier PH1-LD20 Reference Board
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*
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* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+ X11
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*/
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/dts-v1/;
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/include/ "uniphier-ph1-ld20.dtsi"
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/include/ "uniphier-support-card.dtsi"
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/ {
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model = "UniPhier PH1-LD20 Reference Board";
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compatible = "socionext,ph1-ld20-ref", "socionext,ph1-ld20";
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memory {
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device_type = "memory";
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reg = <0 0x80000000 0 0xc0000000>;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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aliases {
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serial0 = &serial0;
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serial1 = &serial1;
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serial2 = &serial2;
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serial3 = &serial3;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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};
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};
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ðsc {
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interrupts = <0 48 4>;
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};
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&serial0 {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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};
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/* for U-Boot only */
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/ {
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soc {
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u-boot,dm-pre-reloc;
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};
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};
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&serial0 {
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u-boot,dm-pre-reloc;
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};
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&pinctrl {
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u-boot,dm-pre-reloc;
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};
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&pinctrl_uart0 {
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u-boot,dm-pre-reloc;
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};
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@ -0,0 +1,241 @@
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/*
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* Device Tree Source for UniPhier PH1-LD20 SoC
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*
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* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+ X11
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*/
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/ {
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compatible = "socionext,ph1-ld20";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu2>;
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};
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core1 {
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cpu = <&cpu3>;
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};
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};
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};
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a72", "arm,armv8";
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reg = <0 0x000>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x80000100>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a72", "arm,armv8";
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reg = <0 0x001>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x80000100>;
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};
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cpu2: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0 0x100>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x80000100>;
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};
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cpu3: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0 0x101>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x80000100>;
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};
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};
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clocks {
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uart_clk: uart_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <58820000>;
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};
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i2c_clk: i2c_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 13 0xf01>,
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<1 14 0xf01>,
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<1 11 0xf01>,
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<1 10 0xf01>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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serial0: serial@54006800 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006800 0x40>;
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interrupts = <0 33 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart0>;
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clocks = <&uart_clk>;
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};
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serial1: serial@54006900 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006900 0x40>;
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interrupts = <0 35 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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clocks = <&uart_clk>;
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};
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serial2: serial@54006a00 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006a00 0x40>;
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interrupts = <0 37 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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clocks = <&uart_clk>;
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};
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serial3: serial@54006b00 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006b00 0x40>;
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interrupts = <0 177 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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clocks = <&uart_clk>;
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};
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i2c0: i2c@58780000 {
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compatible = "socionext,uniphier-fi2c";
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status = "disabled";
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reg = <0x58780000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 41 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c0>;
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clocks = <&i2c_clk>;
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clock-frequency = <100000>;
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};
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i2c1: i2c@58781000 {
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compatible = "socionext,uniphier-fi2c";
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status = "disabled";
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reg = <0x58781000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 42 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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clocks = <&i2c_clk>;
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clock-frequency = <100000>;
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};
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i2c2: i2c@58782000 {
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compatible = "socionext,uniphier-fi2c";
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reg = <0x58782000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 43 4>;
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clocks = <&i2c_clk>;
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clock-frequency = <400000>;
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};
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i2c3: i2c@58783000 {
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compatible = "socionext,uniphier-fi2c";
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status = "disabled";
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reg = <0x58783000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 44 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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clocks = <&i2c_clk>;
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clock-frequency = <100000>;
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};
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i2c4: i2c@58784000 {
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compatible = "socionext,uniphier-fi2c";
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status = "disabled";
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reg = <0x58784000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 45 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c4>;
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clocks = <&i2c_clk>;
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clock-frequency = <100000>;
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};
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i2c5: i2c@58785000 {
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compatible = "socionext,uniphier-fi2c";
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reg = <0x58785000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 25 4>;
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clocks = <&i2c_clk>;
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clock-frequency = <400000>;
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};
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system_bus: system-bus@58c00000 {
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compatible = "socionext,uniphier-system-bus";
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status = "disabled";
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reg = <0x58c00000 0x400>;
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#address-cells = <2>;
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#size-cells = <1>;
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};
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smpctrl@59800000 {
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compatible = "socionext,uniphier-smpctrl";
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reg = <0x59801000 0x400>;
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};
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pinctrl: pinctrl@5f801000 {
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compatible = "socionext,ph1-ld20-pinctrl", "syscon";
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reg = <0x5f801000 0xe00>;
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};
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gic: interrupt-controller@5fe00000 {
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compatible = "arm,gic-v3";
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reg = <0x5fe00000 0x10000>, /* GICD */
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<0x5fe80000 0x80000>; /* GICR */
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <1 9 4>;
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};
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};
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};
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/include/ "uniphier-pinctrl.dtsi"
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@ -37,6 +37,11 @@
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function = "i2c3";
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};
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pinctrl_i2c4: i2c4_grp {
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groups = "i2c4";
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function = "i2c4";
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};
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pinctrl_sd: sd_grp {
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groups = "sd";
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function = "sd";
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