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Merge with /home/mk/git/u-boot#generic_ohci

utp
Wolfgang Denk 2006-05-31 13:12:39 +02:00
parent 392c252efd ddf83a2fce
commit 81d72d7e2e
15 changed files with 438 additions and 50 deletions
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15
board/delta/delta.c
View File

@ -1,10 +1,6 @@
/*
* (C) Copyright 2002
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
* (C) Copyright 2006
* DENX Software Engineering
*
* See file CREDITS for list of people who contributed to this
* project.
@ -98,7 +94,6 @@ int board_late_init(void)
return 0;
}
/*
* Magic Key Handling, mainly copied from board/lwmon/lwmon.c
*/
@ -324,6 +319,12 @@ static void init_DA9030()
return;
}
val = 0x80;
if(i2c_write(addr, IRQ_MASK_B, 1, &val, 1)) {
printf("Error accessing DA9030 via i2c.\n");
return;
}
i2c_reg_write(addr, REG_CONTROL_1_97, 0xfd); /* disable LDO1, enable LDO6 */
i2c_reg_write(addr, LDO2_3, 0xd1); /* LDO2 =1,9V, LDO3=3,1V */
i2c_reg_write(addr, LDO4_5, 0xcc); /* LDO2 =1,9V, LDO3=3,1V */

2
cpu/arm920t/at91rm9200/Makefile
View File

@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(SOC).a
OBJS = bcm5221.o dm9161.o ether.o i2c.o interrupts.o \
lxt972.o serial.o usb_ohci.o
lxt972.o serial.o usb.o
SOBJS = lowlevel_init.o
all: .depend $(LIB)

53
cpu/arm920t/at91rm9200/usb.c 100644
View File

@ -0,0 +1,53 @@
/*
* (C) Copyright 2006
* DENX Software Engineering <mk@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#if defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT)
# ifdef CONFIG_AT91RM9200
#include <asm/arch/hardware.h>
int usb_cpu_init()
{
/* Enable USB host clock. */
*AT91C_PMC_SCER = AT91C_PMC_UHP; /* 48MHz clock enabled for UHP */
*AT91C_PMC_PCER = 1 << AT91C_ID_UHP; /* Peripheral Clock Enable Register */
return 0;
}
int usb_cpu_stop()
{
/* Initialization failed */
*AT91C_PMC_PCDR = 1 << AT91C_ID_UHP; /* Peripheral Clock Disable Register */
*AT91C_PMC_SCDR = AT91C_PMC_UHP; /* 48MHz clock disabled for UHP */
return 0;
}
int usb_cpu_init_fail()
{
usb_cpu_stop();
}
# endif /* CONFIG_AT91RM9200 */
#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */

2
cpu/arm920t/s3c24x0/Makefile
View File

@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(SOC).a
OBJS = i2c.o interrupts.o serial.o speed.o \
usb_ohci.o
usb.o
all: .depend $(LIB)

72
cpu/arm920t/s3c24x0/usb.c 100644
View File

@ -0,0 +1,72 @@
/*
* (C) Copyright 2006
* DENX Software Engineering <mk@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#if defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT)
# if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
#if defined(CONFIG_S3C2400)
# include <s3c2400.h>
#elif defined(CONFIG_S3C2410)
# include <s3c2410.h>
#endif
int usb_cpu_init()
{
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
/*
* Set the 48 MHz UPLL clocking. Values are taken from
* "PLL value selection guide", 6-23, s3c2400_UM.pdf.
*/
clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2);
gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */
/*
* Enable USB host clock.
*/
clk_power->CLKCON |= (1 << 4);
return 0;
}
int usb_cpu_stop()
{
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
/* may not want to do this */
clk_power->CLKCON &= ~(1 << 4);
return 0;
}
int usb_cpu_init_fail()
{
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
clk_power->CLKCON &= ~(1 << 4);
return 0;
}
# endif /* defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) */
#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */

2
cpu/pxa/Makefile
View File

@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(CPU).a
START = start.o
OBJS = serial.o interrupts.o cpu.o i2c.o pxafb.o mmc.o
OBJS = serial.o interrupts.o cpu.o i2c.o pxafb.o mmc.o usb.o
all: .depend $(START) $(LIB)

78
cpu/pxa/usb.c 100644
View File

@ -0,0 +1,78 @@
/*
* (C) Copyright 2006
* Markus Klotzbuecher, DENX Software Engineering <mk@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#if defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT)
# ifdef CONFIG_CPU_MONAHANS
#include <asm/arch/pxa-regs.h>
int usb_cpu_init()
{
/* Enable USB host clock. */
CKENA |= (CKENA_2_USBHOST | CKENA_20_UDC);
udelay(100);
/* Configure Port 2 for Host (USB Client Registers) */
UP2OCR = 0x3000c;
#if 0
GPIO2_2 = 0x801; /* USBHPEN - Alt. Fkt. 1 */
GPIO3_2 = 0x801; /* USBHPWR - Alt. Fkt. 1 */
#endif
UHCHR |= UHCHR_FHR;
wait_ms(11);
UHCHR &= ~UHCHR_FHR;
UHCHR |= UHCHR_FSBIR;
while (UHCHR & UHCHR_FSBIR)
udelay(1);
#if 0
UHCHR |= UHCHR_PCPL; /* USBHPEN is active low */
UHCHR |= UHCHR_PSPL; /* USBHPWR is active low */
#endif
UHCHR &= ~UHCHR_SSEP0;
UHCHR &= ~UHCHR_SSEP1;
UHCHR &= ~UHCHR_SSE;
return 0;
}
int usb_cpu_stop()
{
/* may not want to do this */
/* CKENA &= ~(CKENA_2_USBHOST | CKENA_20_UDC); */
return 0;
}
int usb_cpu_init_fail()
{
return 0;
}
# endif /* CONFIG_CPU_MONAHANS */
#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */

2
drivers/Makefile
View File

@ -46,7 +46,7 @@ OBJS = 3c589.o 5701rls.o ali512x.o \
sl811_usb.o sm501.o smc91111.o smiLynxEM.o \
status_led.o sym53c8xx.o \
ti_pci1410a.o tigon3.o tsec.o \
usbdcore.o usbdcore_ep0.o usbdcore_omap1510.o usbtty.o \
usb_ohci.o usbdcore.o usbdcore_ep0.o usbdcore_omap1510.o usbtty.o \
videomodes.o w83c553f.o \
ks8695eth.o

181
cpu/arm920t/at91rm9200/usb_ohci.c → drivers/usb_ohci.c
View File

@ -21,7 +21,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@ -45,13 +45,28 @@
#ifdef CONFIG_USB_OHCI
#include <asm/arch/hardware.h>
#if defined(CONFIG_S3C2400)
# include <s3c2400.h>
#elif defined(CONFIG_S3C2410)
# include <s3c2410.h>
#elif defined(CONFIG_ARM920T)
# include <asm/arch/hardware.h>
#elif defined(CONFIG_CPU_MONAHANS)
# include <asm/arch/pxa-regs.h>
#endif
#include <malloc.h>
#include <usb.h>
#include "usb_ohci.h"
#define OHCI_USE_NPS /* force NoPowerSwitching mode */
#undef S3C24X0_merge
#if defined(CONFIG_ARM920T) || \
defined(CONFIG_S3C2400) || \
defined(CONFIG_S3C2410)
# define OHCI_USE_NPS /* force NoPowerSwitching mode */
#endif
#undef OHCI_VERBOSE_DEBUG /* not always helpful */
/* For initializing controller (mask in an HCFS mode too) */
@ -95,6 +110,12 @@ int got_rhsc;
/* device which was disconnected */
struct usb_device *devgone;
#ifdef S3C24X0_merge
/* flag guarding URB transation */
int urb_finished = 0;
#endif
/*-------------------------------------------------------------------------*/
/* AMD-756 (D2 rev) reports corrupt register contents in some cases.
@ -399,6 +420,17 @@ int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
err("sohci_submit_job: EPIPE");
return -1;
}
#ifdef S3C24X0_merge
/* if we have an unfinished URB from previous transaction let's
* fail and scream as quickly as possible so as not to corrupt
* further communication */
if (!urb_finished) {
err("sohci_submit_job: URB NOT FINISHED");
return -1;
}
/* we're about to begin a new transaction here so mark the URB unfinished */
urb_finished = 0;
#endif
/* every endpoint has a ed, locate and fill it */
if (!(ed = ep_add_ed (dev, pipe))) {
@ -571,12 +603,14 @@ static int ep_unlink (ohci_t *ohci, ed_t *ed)
/*-------------------------------------------------------------------------*/
/* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
* but the USB stack is a little bit stateless so we do it at every transaction
* if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
* in all other cases the state is left unchanged
* the ed info fields are setted anyway even though most of them should not change */
/* add/reinit an endpoint; this should be done once at the
* usb_set_configuration command, but the USB stack is a little bit
* stateless so we do it at every transaction if the state of the ed
* is ED_NEW then a dummy td is added and the state is changed to
* ED_UNLINK in all other cases the state is left unchanged the ed
* info fields are setted anyway even though most of them should not
* change
*/
static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
{
td_t *td;
@ -660,7 +694,9 @@ static void td_fill (ohci_t *ohci, unsigned int info,
else
td->hwBE = 0;
td->hwNextTD = m32_swap (td_pt);
#ifndef S3C24X0_merge
td->hwPSW [0] = m16_swap (((__u32)data & 0x0FFF) | 0xE000);
#endif
/* append to queue */
td->ed->hwTailP = td->hwNextTD;
@ -827,7 +863,18 @@ static int dl_done_list (ohci_t *ohci, td_t *td_list)
dbg("ConditionCode %#x", cc);
stat = cc_to_error[cc];
}
#ifdef S3C24X0_merge
/* see if this done list makes for all TD's of current URB,
* and mark the URB finished if so */
if (++(lurb_priv->td_cnt) == lurb_priv->length) {
if ((ed->state & (ED_OPER | ED_UNLINK)))
urb_finished = 1;
else
dbg("dl_done_list: strange.., ED state %x, ed->state\n");
} else
dbg("dl_done_list: processing TD %x, len %x\n", lurb_priv->td_cnt,
lurb_priv->length);
#endif
if (ed->state != ED_NEW) {
edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
edTailP = m32_swap (ed->hwTailP);
@ -974,7 +1021,6 @@ int rh_check_port_status(ohci_t *controller)
#ifdef CONFIG_AT91C_PQFP_UHPBUG
ndp = (ndp == 2) ? 1:0;
#endif
for (i = 0; i < ndp; i++) {
temp = roothub_portstatus (controller, i);
/* check for a device disconnect */
@ -1170,7 +1216,7 @@ pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
}
len = min_t(unsigned int, leni,
min_t(unsigned int, data_buf [0], wLength));
min_t(unsigned int, data_buf [0], wLength));
OK (len);
}
@ -1258,18 +1304,38 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
stat = USB_ST_CRC_ERR;
break;
}
#ifdef S3C24X0_merge
/* NOTE: since we are not interrupt driven in U-Boot and always
* handle only one URB at a time, we cannot assume the
* transaction finished on the first successful return from
* hc_interrupt().. unless the flag for current URB is set,
* meaning that all TD's to/from device got actually
* transferred and processed. If the current URB is not
* finished we need to re-iterate this loop so as
* hc_interrupt() gets called again as there needs to be some
* more TD's to process still */
if ((stat >= 0) && (stat != 0xff) && (urb_finished)) {
#else
if (stat >= 0 && stat != 0xff) {
#endif
/* 0xff is returned for an SF-interrupt */
break;
}
if (--timeout) {
wait_ms(1);
} else {
err("CTL:TIMEOUT ");
#ifdef S3C24X0_merge
dbg("submit_common_msg: TO status %x\n", stat);
urb_finished = 1;
#endif
stat = USB_ST_CRC_ERR;
break;
}
}
#ifndef S3C24X0_merge
/* we got an Root Hub Status Change interrupt */
if (got_rhsc) {
#ifdef DEBUG
@ -1291,6 +1357,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
devgone = dev;
}
}
#endif /* S3C24X0_merge */
dev->status = stat;
dev->act_len = transfer_len;
@ -1460,24 +1527,40 @@ static int hc_start (ohci_t * ohci)
/* an interrupt happens */
static int
hc_interrupt (void)
static int hc_interrupt (void)
{
ohci_t *ohci = &gohci;
struct ohci_regs *regs = ohci->regs;
int ints;
int stat = -1;
#ifdef S3C24X0_merge
if ((ohci->hcca->done_head != 0) &&
!(m32_swap (ohci->hcca->done_head) & 0x01)) {
ints = OHCI_INTR_WDH;
} else if ((ints = readl (&regs->intrstatus)) == ~(u32)0) {
ohci->disabled++;
err ("%s device removed!", ohci->slot_name);
return -1;
} else if ((ints &= readl (&regs->intrenable)) == 0) {
dbg("hc_interrupt: returning..\n");
return 0xff;
}
#else
if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) {
ints = OHCI_INTR_WDH;
} else {
ints = readl (&regs->intrstatus);
}
#endif
/* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
if (ints & OHCI_INTR_RHSC) {
got_rhsc = 1;
#ifdef S3C24X0_merge
stat = 0xff;
#endif
}
if (ints & OHCI_INTR_UE) {
@ -1549,12 +1632,18 @@ static char ohci_inited = 0;
int usb_lowlevel_init(void)
{
/*
* Enable USB host clock.
*/
*AT91C_PMC_SCER = AT91C_PMC_UHP; /* 48MHz clock enabled for UHP */
*AT91C_PMC_PCER = 1 << AT91C_ID_UHP; /* Peripheral Clock Enable Register */
#ifdef CFG_USB_OHCI_CPU_INIT
/* cpu dependant init */
if(usb_cpu_init())
return -1;
#endif
#ifdef CFG_USB_OHCI_BOARD_INIT
/* board dependant init */
if(usb_board_init())
return -1;
#endif
memset (&gohci, 0, sizeof (ohci_t));
memset (&urb_priv, 0, sizeof (urb_priv_t));
@ -1582,29 +1671,42 @@ int usb_lowlevel_init(void)
gohci.disabled = 1;
gohci.sleeping = 0;
gohci.irq = -1;
gohci.regs = (struct ohci_regs *)AT91_USB_HOST_BASE;
gohci.regs = (struct ohci_regs *)CFG_USB_OHCI_REGS_BASE;
gohci.flags = 0;
gohci.slot_name = "at91rm9200";
gohci.slot_name = CFG_USB_OHCI_SLOT_NAME;
if (hc_reset (&gohci) < 0) {
hc_release_ohci (&gohci);
/* Initialization failed */
*AT91C_PMC_PCER = AT91C_ID_UHP;
*AT91C_PMC_SCDR = 1 << AT91C_PMC_UHP; /* 48MHz clock disabled for UHP */
err ("can't reset usb-%s", gohci.slot_name);
#ifdef CFG_USB_OHCI_BOARD_INIT
/* board dependant cleanup */
usb_board_init_fail();
#endif
#ifdef CFG_USB_OHCI_CPU_INIT
/* cpu dependant cleanup */
usb_cpu_init_fail();
#endif
return -1;
}
/* FIXME this is a second HC reset; why?? */
/* writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);
wait_ms (10);*/
/* writel(gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);
wait_ms(10); */
if (hc_start (&gohci) < 0) {
err ("can't start usb-%s", gohci.slot_name);
hc_release_ohci (&gohci);
/* Initialization failed */
*AT91C_PMC_PCER = AT91C_ID_UHP;
*AT91C_PMC_SCDR = 1 << AT91C_PMC_UHP; /* 48MHz clock disabled for UHP */
#ifdef CFG_USB_OHCI_BOARD_INIT
/* board dependant cleanup */
usb_board_stop();
#endif
#ifdef CFG_USB_OHCI_CPU_INIT
/* cpu dependant cleanup */
usb_cpu_stop();
#endif
return -1;
}
@ -1612,6 +1714,9 @@ int usb_lowlevel_init(void)
ohci_dump (&gohci, 1);
#else
wait_ms(1);
# ifdef S3C24X0_merge
urb_finished = 1;
# endif
#endif
ohci_inited = 1;
return 0;
@ -1626,9 +1731,19 @@ int usb_lowlevel_stop(void)
/* TODO release any interrupts, etc. */
/* call hc_release_ohci() here ? */
hc_reset (&gohci);
/* may not want to do this */
*AT91C_PMC_PCER = 1 << AT91C_ID_UHP;
*AT91C_PMC_SCDR = 1 << AT91C_PMC_UHP; /* 48MHz clock disabled for UHP */
#ifdef CFG_USB_OHCI_BOARD_INIT
/* board dependant cleanup */
if(usb_board_stop())
return -1;
#endif
#ifdef CFG_USB_OHCI_CPU_INIT
/* cpu dependant cleanup */
if(usb_cpu_stop())
return -1;
#endif
return 0;
}

15
cpu/arm920t/at91rm9200/usb_ohci.h → drivers/usb_ohci.h
View File

@ -7,6 +7,19 @@
* usb-ohci.h
*/
/* functions for doing board specific setup/cleanup */
#ifdef CFG_USB_BOARD_INIT
extern int usb_board_init(void);
extern int usb_board_stop(void);
extern int usb_cpu_init_fail(void);
#endif
#ifdef CFG_USB_CPU_INIT
extern int usb_cpu_init(void);
extern int usb_cpu_stop(void);
extern int usb_cpu_init_fail(void);
#endif
static int cc_to_error[16] = {
@ -138,7 +151,7 @@ struct ohci_hcca {
/*
* Maximum number of root hub ports.
*/
#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */
#define MAX_ROOT_PORTS 3 /* maximum OHCI root hub ports */
/*
* This is the structure of the OHCI controller's memory mapped I/O

23
include/asm-arm/arch-pxa/pxa-regs.h
View File

@ -592,9 +592,11 @@ typedef void (*ExcpHndlr) (void) ;
#define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */
#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */
/*
* USB Device Controller
*/
#ifndef CONFIG_CPU_MONAHANS
#define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */
#define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */
#define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */
@ -749,11 +751,30 @@ typedef void (*ExcpHndlr) (void) ;
#define USIR1_IR13 (1 << 5) /* Interrup request ep 13 */
#define USIR1_IR14 (1 << 6) /* Interrup request ep 14 */
#define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */
#endif /* ! CONFIG_CPU_MONAHANS */
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
/*
* USB Client Controller (incomplete)
*/
#define UDCCR __REG(0x40600000)
#define UDCICR0 __REG(0x40600004)
#define UDCCIR0 __REG(0x40600008)
#define UDCISR0 __REG(0x4060000c)
#define UDCSIR1 __REG(0x40600010)
#define UDCFNR __REG(0x40600014)
#define UDCOTGICR __REG(0x40600018)
#define UDCOTGISR __REG(0x4060001c)
#define UP2OCR __REG(0x40600020)
#define UP3OCR __REG(0x40600024)
#if defined(CONFIG_PXA27X)
/*
* USB Host Controller
*/
#define OHCI_REGS_BASE 0x4C000000 /* required for ohci driver */
#define UHCREV __REG(0x4C000000)
#define UHCHCON __REG(0x4C000004)
#define UHCCOMS __REG(0x4C000008)

15
include/configs/delta.h
View File

@ -94,12 +94,25 @@
# define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
| CFG_CMD_ENV \
| CFG_CMD_NAND \
| CFG_CMD_I2C) \
| CFG_CMD_I2C \
| CFG_CMD_USB \
| CFG_CMD_FAT) \
& ~(CFG_CMD_NET \
| CFG_CMD_FLASH \
| CFG_CMD_IMLS))
#endif
/* USB */
#define CONFIG_USB_OHCI 1
#define CONFIG_USB_STORAGE 1
#define CONFIG_DOS_PARTITION 1
#undef CFG_USB_OHCI_BOARD_INIT
#define CFG_USB_OHCI_CPU_INIT 1
#define CFG_USB_OHCI_REGS_BASE OHCI_REGS_BASE
#define CFG_USB_OHCI_SLOT_NAME "delta"
#define LITTLEENDIAN 1 /* used by usb_ohci.c */
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

11
include/configs/mp2usb.h
View File

@ -107,6 +107,11 @@
#define CONFIG_DOS_PARTITION 1
#define CONFIG_AT91C_PQFP_UHPBUG 1
#undef CFG_USB_OHCI_BOARD_INIT
#define CFG_USB_OHCI_CPU_INIT 1
#define CFG_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE
#define CFG_USB_OHCI_SLOT_NAME "at91rm9200"
#undef CONFIG_HARD_I2C
#ifdef CONFIG_HARD_I2C
@ -127,7 +132,7 @@
#define CONFIG_COMMANDS \
((CONFIG_CMD_DFL | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_DHCP | \
CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
CFG_CMD_NFS | \
@ -136,7 +141,7 @@
#else
#define CONFIG_COMMANDS \
((CONFIG_CMD_DFL | \
CFG_CMD_DHCP | \
CFG_CMD_DHCP | \
CFG_CMD_NFS | \
CFG_CMD_SNTP | \
CFG_CMD_USB | \
@ -156,7 +161,7 @@
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM 0x20000000
#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */
#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */
#define CFG_MEMTEST_START PHYS_SDRAM
#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144

5
include/configs/trab.h
View File

@ -84,6 +84,11 @@
#define CONFIG_USB_STORAGE 1
#define CONFIG_DOS_PARTITION 1
#undef CFG_USB_OHCI_BOARD_INIT
#define CFG_USB_OHCI_CPU_INIT 1
#define CFG_USB_OHCI_REGS_BASE S3C24X0_USB_HOST_BASE
#define CFG_USB_OHCI_SLOT_NAME "s3c2400"
/*
* Size of malloc() pool
*/

12
include/da9030.h
View File

@ -104,3 +104,15 @@
#define SYS_CONTROL_A_HWRES_ENABLE (1<<2)
#define SYS_CONTROL_A_WDOG_ACTION (1<<3)
#define SYS_CONTROL_A_WATCHDOG (1<<7)
#define MISC_CONTROLB_USB_INT_RISING (1<<2)
#define MISC_CONTROLB_SESSION_VALID_EN (1<<3)
#define USB_PUMP_USBVE (1<<0)
#define USB_PUMP_USBVEP (1<<1)
#define USB_PUMP_SRP_DETECT (1<<2)
#define USB_PUMP_SESSION_VALID (1<<3)
#define USB_PUMP_VBUS_VALID_4_0 (1<<4)
#define USB_PUMP_VBUS_VALID_4_4 (1<<5)
#define USB_PUMP_EN_USBVE (1<<6)
#define USB_PUMP_EN_USBVEP (1<<7)