Add STX GP3 SSA board to MAKEALL script; update CHANGELOG.
Signed-off-by: Wolfgang Denk <wd@denx.de>utp
Wolfgang Denk
parent
49db23d452
commit
885ec89b64
268
CHANGELOG
268
CHANGELOG
|
|
@ -1,3 +1,9 @@
|
|||
commit 5499645b3fe17a548af9dfc479ca6e2455f179a2
|
||||
Author: Wolfgang Denk <wd@denx.de>
|
||||
Date: Sat May 5 17:15:50 2007 +0200
|
||||
|
||||
Make "file" command happy with some config.mk files; update CHANGELOG
|
||||
|
||||
commit a79886590593ba1d667c840caa4940c61639f18f
|
||||
Author: Thomas Knobloch <knobloch@siemens.com>
|
||||
Date: Sat May 5 07:04:42 2007 +0200
|
||||
|
|
@ -53,6 +59,51 @@ Date: Fri Jan 5 09:15:34 2007 +0100
|
|||
|
||||
Signed-off-by Dan Malek, <dan@embeddedalley.com>
|
||||
|
||||
commit ffa621a0d12a1ccd81c936c567f8917a213787a8
|
||||
Author: Andy Fleming <afleming@freescale.com>
|
||||
Date: Sat Feb 24 01:08:13 2007 -0600
|
||||
|
||||
Cleaned up some 85xx PCI bugs
|
||||
|
||||
* Cleaned up the CDS PCI Config Tables and added NULL entries to
|
||||
the end
|
||||
* Fixed PCIe LAWBAR assignemt to use the cpu-relative address
|
||||
* Fixed 85xx PCI code to assign powar region sizes based on the
|
||||
config values (rather than hard-coding them)
|
||||
* Fixed the 8548 CDS PCI2 IO to once again have 0 as the base address
|
||||
|
||||
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
||||
|
||||
commit 6743105988fc44d5b0d30388c790607835aae7a6
|
||||
Author: Andy Fleming <afleming@freescale.com>
|
||||
Date: Mon Apr 23 02:54:25 2007 -0500
|
||||
|
||||
Add support for the 8568 MDS board
|
||||
|
||||
This included some changes to common files:
|
||||
* Add 8568 processor SVR to various places
|
||||
* Add support for setting the qe bus-frequency value in the dts
|
||||
* Add the 8568MDS target to the Makefile
|
||||
|
||||
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
||||
|
||||
commit af1c2b84bf27c8565baddc82d1abb93700d10e2e
|
||||
Author: David Updegraff <dave@cray.com>
|
||||
Date: Fri Apr 20 14:34:48 2007 -0500
|
||||
|
||||
Add support for treating unknown PHYs as generic PHYs.
|
||||
|
||||
When bringing up u-boot on new boards, PHY support sometimes gets
|
||||
neglected. Most PHYs don't really need any special support,
|
||||
though. By adding a generic entry that always matches if nothing
|
||||
else does, we can provide support for "unsupported" PHYs for the
|
||||
tsec.
|
||||
|
||||
The generic PHY driver supports most PHYs, including gigabit.
|
||||
|
||||
Signed-off-by: David Updegraff <dave@cray.com>
|
||||
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
||||
|
||||
commit a75af9bfd8fff0499efdbb90601cec5a2afef117
|
||||
Author: James Yang <James.Yang@freescale.com>
|
||||
Date: Wed Feb 7 15:28:04 2007 -0600
|
||||
|
|
@ -73,6 +124,223 @@ Date: Fri Mar 16 13:02:53 2007 -0500
|
|||
Signed-off-by: James Yang <James.Yang@freescale.com>
|
||||
Signed-off-by: Jon Loeliger <jdl@freescale.com>
|
||||
|
||||
commit 66ed6cca3f340f7a8a06d9272ae2ef8e96f0273d
|
||||
Author: Andy Fleming <afleming@freescale.com>
|
||||
Date: Mon Apr 23 02:37:47 2007 -0500
|
||||
|
||||
Reworked 85xx speed detection code
|
||||
|
||||
Changed the code to read the registers and calculate the clock
|
||||
rates, rather than using a "switch" statement.
|
||||
|
||||
Idea from Andrew Klossner <andrew@cesa.opbu.xerox.com>
|
||||
|
||||
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
||||
|
||||
commit 81f481ca708ed6a56bf9c410e3191dbad581c565
|
||||
Author: Andy Fleming <afleming@freescale.com>
|
||||
Date: Mon Apr 23 02:24:28 2007 -0500
|
||||
|
||||
Enable 8544 support
|
||||
|
||||
* Add support to the Makefile
|
||||
* Add 8544 configuration support to the tsec driver
|
||||
* Add 8544 SVR numbers to processor.h
|
||||
|
||||
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
|
||||
Signed-off-by: Jon Loeliger <jdl@freescale.com>
|
||||
|
||||
commit 0d8c3a2096eaff8d7de89d45e9af4d4b0d4868fe
|
||||
Author: Andy Fleming <afleming@freescale.com>
|
||||
Date: Fri Feb 23 17:12:25 2007 -0600
|
||||
|
||||
Support 1G size on 8548
|
||||
|
||||
e500v2 and newer cores support 1G page sizes.
|
||||
|
||||
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
|
||||
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
||||
|
||||
commit 45cef612cc601d2d1c890fbbd7cdc9609a189a46
|
||||
Author: Andy Fleming <afleming@freescale.com>
|
||||
Date: Fri Feb 23 17:11:16 2007 -0600
|
||||
|
||||
Changed BOOKE_PAGESZ_nGB to BOOKE_PAGESZ_nG
|
||||
|
||||
The other pagesz constants use one letter to specify order of
|
||||
magnitude. Also change the one reference to it in mpc8548cds/init.S
|
||||
|
||||
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
||||
|
||||
commit 1f9a318cea14272edd10d63739e2d326c90f430e
|
||||
Author: Andy Fleming <afleming@freescale.com>
|
||||
Date: Fri Feb 23 16:28:46 2007 -0600
|
||||
|
||||
Only set ddrioovcr for 8548 rev1.
|
||||
|
||||
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
|
||||
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
||||
|
||||
commit 9343dbf85bc03033f2102d8e8543567c2c1ad2d2
|
||||
Author: Andy Fleming <afleming@freescale.com>
|
||||
Date: Sat Feb 24 01:16:45 2007 -0600
|
||||
|
||||
Tweak DDR ECC error counter
|
||||
|
||||
Enable single-bit error counter when memory was cleared by ddr controller.
|
||||
|
||||
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
|
||||
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
||||
|
||||
commit 85e7c7a45e3dd9c7ce3e722352ba60f8df1a7a4b
|
||||
Author: Timur Tabi <timur@freescale.com>
|
||||
Date: Mon Feb 12 13:34:55 2007 -0600
|
||||
|
||||
85xx: write MAC address to mac-address and local-mac-address
|
||||
|
||||
Some device trees have a mac-address property, some have local-mac-address,
|
||||
and some have both. To support all of these device trees, ftp_cpu_setup()
|
||||
should write the MAC address to mac-address and local-mac-address, if they
|
||||
exist.
|
||||
|
||||
Signed-off-by: Timur Tabi <timur@freescale.com>
|
||||
|
||||
commit 03b81b48eec0ad249ec97a4ae16c36fa2e014ff4
|
||||
Author: Andy Fleming <afleming@freescale.com>
|
||||
Date: Mon Apr 23 01:44:44 2007 -0500
|
||||
|
||||
Some 85xx cpu cleanups
|
||||
|
||||
* Cleaned up the TSR[WIS] clearing
|
||||
* Cleaned up DMA initialization
|
||||
|
||||
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
|
||||
Signed-off-by: Jon Loeliger <jdl@freescale.com>
|
||||
Acked-by: Andy Fleming <afleming@freescale.com>
|
||||
|
||||
commit 151d5d992eab8c497b24c816c73dc1ad8bffb4eb
|
||||
Author: Andy Fleming <afleming@freescale.com>
|
||||
Date: Mon Apr 23 01:32:22 2007 -0500
|
||||
|
||||
Add cpu support for the 8544
|
||||
|
||||
Recognize new SVR values, and add a few register definitions
|
||||
|
||||
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
|
||||
Signed-off-by: Jon Loeliger <jdl@freescale.com>
|
||||
Acked-by: Andy Fleming <afleming@freescale.com>
|
||||
|
||||
commit 25d83d7f4ac65727182d8ddaf7ba42fa74cf65ae
|
||||
Author: Jon Loeliger <jdl@freescale.com>
|
||||
Date: Wed Apr 11 16:51:02 2007 -0500
|
||||
|
||||
Add MPC8544DS basic port board files.
|
||||
|
||||
Add board port under new board/freescale directory
|
||||
structure and reuse existing PIXIS FPGA support there.
|
||||
|
||||
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
|
||||
Signed-off-by: Jon Loeliger <jdl@freescale.com>
|
||||
|
||||
commit 0cde4b00fc7393b89f379d83a9d436dcb1334bfa
|
||||
Author: Jon Loeliger <jdl@freescale.com>
|
||||
Date: Wed Apr 11 16:50:57 2007 -0500
|
||||
|
||||
Add MPC8544DS main configuration file.
|
||||
|
||||
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
|
||||
Signed-off-by: Jon Loeliger <jdl@freescale.com>
|
||||
|
||||
commit 362dd83077ac04c0296bca3e824ec2fb3d44d9d6
|
||||
Author: Sergei Shtylyov <sshtylyov@ru.mvista.com>
|
||||
Date: Wed Dec 27 22:07:15 2006 +0300
|
||||
|
||||
Fix PCI I/O space mapping on Freescale MPC85x0ADS
|
||||
|
||||
The PCI I/O space mapping for Freescale MPC8540ADS board was broken by commit
|
||||
52c7a68b8d587ebcf5a6b051b58b3d3ffa377ddc which failed to update the #define's
|
||||
describing the local address window used for the PCI I/O space accesses -- fix
|
||||
this and carry over the necessary changes into the MPC8560ADS code since the
|
||||
PCI I/O space mapping was also broken for this board (by the earlier commit
|
||||
087454609e47295443af793a282cddcd91a5f49c). Add the comments clarifying how
|
||||
the PCI I/O space must be mapped to all the MPC85xx board config. headers.
|
||||
|
||||
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
|
||||
|
||||
board/mpc8540ads/init.S | 4 ++--
|
||||
board/mpc8560ads/init.S | 4 ++--
|
||||
include/configs/MPC8540ADS.h | 5 ++---
|
||||
include/configs/MPC8541CDS.h | 2 +-
|
||||
include/configs/MPC8548CDS.h | 2 +-
|
||||
include/configs/MPC8560ADS.h | 8 ++++----
|
||||
6 files changed, 12 insertions(+), 13 deletions(-)
|
||||
|
||||
commit 96629cbabdb727d4a5e62542deefc01d498db6dc
|
||||
Author: Zang Roy-r61911 <tie-fei.zang@freescale.com>
|
||||
Date: Tue Dec 5 16:42:30 2006 +0800
|
||||
|
||||
u-boot: Fix e500 v2 core reset bug
|
||||
|
||||
The following patch fixes the e500 v2 core reset bug.
|
||||
For e500 v2 core, a new reset control register is added to reset the
|
||||
processor.
|
||||
|
||||
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
|
||||
|
||||
commit 63247a5acd58032e6cf33f525bc3923b467bac88
|
||||
Author: Zang Roy-r61911 <tie-fei.zang@freescale.com>
|
||||
Date: Wed Dec 20 11:01:00 2006 +0800
|
||||
|
||||
u-boot: v2: Remove the fixed TLB and LAW entrynubmer
|
||||
|
||||
Remove the fixed TLB and LAW entry nubmer. Use actually TLB and LAW
|
||||
entry number to control the loop. This can reduce the potential risk
|
||||
for the 85xx processor increasing its TLB adn LAW entry number.
|
||||
|
||||
Signed-off-by: Swarthout Edward <swarthout@freescale.com>
|
||||
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
|
||||
|
||||
commit 0b1934ba12fd408fcc3b8bd9f4b04864c42a42bf
|
||||
Author: Zang Roy-r61911 <tie-fei.zang@freescale.com>
|
||||
Date: Mon Dec 18 17:01:04 2006 +0800
|
||||
|
||||
u-boot: Fix the 85xxcds tsec bug
|
||||
|
||||
Fix the 85xxcds tsec bug.
|
||||
When enable PCI, tsec.o should be added to u-boot.lds to make tsec work.
|
||||
|
||||
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
|
||||
|
||||
commit 7337b237ffc4aaf1b9467024fe472a880d852598
|
||||
Author: Zang Roy-r61911 <tie-fei.zang@freescale.com>
|
||||
Date: Fri Dec 15 14:43:31 2006 +0800
|
||||
|
||||
u-boot: Fix CPU2 errata on MPC8548CDS board
|
||||
|
||||
This patch apply workaround of CPU2 errata on MPC8548CDS board.
|
||||
|
||||
Signed-off-by:Ebony Zhu <ebony.zhu@freescale.com>
|
||||
|
||||
commit 39b18c4f3e0b6d0dc00f4e68bad2da3766c85f09
|
||||
Author: ebony.zhu@freescale.com <ebony.zhu@freescale.com>
|
||||
Date: Mon Dec 18 16:25:15 2006 +0800
|
||||
|
||||
u-boot: Disables MPC8548CDS 2T_TIMING for DDR by default
|
||||
|
||||
This patch disables MPC8548CDS 2T_TIMING for DDR by default.
|
||||
|
||||
Signed-off-by:Ebony Zhu <ebony.zhu@freescale.com>
|
||||
|
||||
commit 41fb7e0f1ec9b91bdae2565bab5f2e3ee15039c7
|
||||
Author: Zang Roy-r61911 <tie-fei.zang@freescale.com>
|
||||
Date: Thu Dec 14 14:14:55 2006 +0800
|
||||
|
||||
u-boot: Enable PCI function and add PEX & rapidio memory map on MPC8548CDS board
|
||||
|
||||
Enable PCI function and add PEX & rapidio memory map on MPC8548CDS
|
||||
board.
|
||||
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
|
||||
|
||||
commit 323bfa8f436dc3bc57187c9b1488bc3146ff1522
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Mon Apr 23 12:00:22 2007 +0200
|
||||
|
|
|
|||
3
MAKEALL
3
MAKEALL
|
|
@ -145,7 +145,8 @@ LIST_85xx=" \
|
|||
MPC8540ADS MPC8540EVAL MPC8541CDS MPC8544DS \
|
||||
MPC8548CDS MPC8555CDS MPC8560ADS PM854 \
|
||||
PM856 sbc8540 sbc8560 stxgp3 \
|
||||
TQM8540 TQM8541 TQM8555 TQM8560 \
|
||||
stxssa TQM8540 TQM8541 TQM8555 \
|
||||
TQM8560 \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
|
|
|
|||
Loading…
Reference in New Issue