ls2085a: esdhc: Add esdhc support for ls2085a
This patch adds esdhc support for ls2085a. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>utp
Yangbo Lu
York Sun
parent
32eda7cc94
commit
8b06460e55
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@ -13,6 +13,9 @@
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#include <fsl_debug_server.h>
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#include <fsl-mc/fsl_mc.h>
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#include <asm/arch/fsl_serdes.h>
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#ifdef CONFIG_FSL_ESDHC
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#include <fsl_esdhc.h>
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#endif
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#include "cpu.h"
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#include "mp.h"
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#include "speed.h"
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@ -412,6 +415,13 @@ int print_cpuinfo(void)
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}
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#endif
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#ifdef CONFIG_FSL_ESDHC
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int cpu_mmc_init(bd_t *bis)
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{
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return fsl_esdhc_mmc_init(bis);
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}
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#endif
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int cpu_eth_init(bd_t *bis)
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{
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int error = 0;
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@ -7,6 +7,9 @@
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#include <common.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#ifdef CONFIG_FSL_ESDHC
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#include <fsl_esdhc.h>
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#endif
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#include "mp.h"
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#ifdef CONFIG_MP
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@ -65,4 +68,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
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do_fixup_by_compat_u32(blob, "fsl,ns16550",
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"clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
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#endif
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#if defined(CONFIG_FSL_ESDHC)
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fdt_fixup_esdhc(blob, bd);
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#endif
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}
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@ -31,6 +31,7 @@
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#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
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#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
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#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
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#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
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#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
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@ -110,6 +111,7 @@
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#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
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#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
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#define CONFIG_SYS_FSL_ESDHC_LE
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/* IFC */
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#define CONFIG_SYS_FSL_IFC_LE
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#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
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@ -105,7 +105,8 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
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else if (cmd->resp_type & MMC_RSP_PRESENT)
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xfertyp |= XFERTYP_RSPTYP_48;
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#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || defined(CONFIG_LS102XA)
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#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || \
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defined(CONFIG_LS102XA) || defined(CONFIG_LS2085A)
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if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
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xfertyp |= XFERTYP_CMDTYP_ABORT;
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#endif
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@ -183,7 +184,9 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
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int timeout;
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struct fsl_esdhc_cfg *cfg = mmc->priv;
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struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
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#ifdef CONFIG_LS2085A
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dma_addr_t addr;
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#endif
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uint wml_value;
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wml_value = data->blocksize/4;
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@ -194,7 +197,15 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
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esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
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#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
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#ifdef CONFIG_LS2085A
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addr = virt_to_phys((void *)(data->dest));
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if (upper_32_bits(addr))
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printf("Error found for upper 32 bits\n");
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else
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esdhc_write32(®s->dsaddr, lower_32_bits(addr));
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#else
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esdhc_write32(®s->dsaddr, (u32)data->dest);
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#endif
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#endif
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} else {
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#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
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@ -212,7 +223,15 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
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esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
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wml_value << 16);
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#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
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#ifdef CONFIG_LS2085A
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addr = virt_to_phys((void *)(data->src));
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if (upper_32_bits(addr))
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printf("Error found for upper 32 bits\n");
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else
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esdhc_write32(®s->dsaddr, lower_32_bits(addr));
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#else
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esdhc_write32(®s->dsaddr, (u32)data->src);
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#endif
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#endif
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}
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@ -259,10 +278,23 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
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static void check_and_invalidate_dcache_range
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(struct mmc_cmd *cmd,
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struct mmc_data *data) {
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#ifdef CONFIG_LS2085A
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unsigned start = 0;
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#else
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unsigned start = (unsigned)data->dest ;
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#endif
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unsigned size = roundup(ARCH_DMA_MINALIGN,
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data->blocks*data->blocksize);
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unsigned end = start+size ;
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#ifdef CONFIG_LS2085A
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dma_addr_t addr;
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addr = virt_to_phys((void *)(data->dest));
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if (upper_32_bits(addr))
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printf("Error found for upper 32 bits\n");
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else
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start = lower_32_bits(addr);
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#endif
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invalidate_dcache_range(start, end);
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}
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#endif
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@ -155,6 +155,9 @@ unsigned long long get_qixis_addr(void);
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#define QIXIS_BASE get_qixis_addr()
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#define QIXIS_BASE_PHYS 0x20000000
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#define QIXIS_BASE_PHYS_EARLY 0xC000000
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#define QIXIS_STAT_PRES1 0xb
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#define QIXIS_SDID_MASK 0x07
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#define QIXIS_ESDHC_NO_ADAPTER 0x7
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#define CONFIG_SYS_NAND_BASE 0x530000000ULL
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#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
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@ -217,8 +220,6 @@ unsigned long long get_qixis_addr(void);
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#define CONFIG_CMD_BOOTD
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#define CONFIG_CMD_ECHO
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#define CONFIG_CMD_SOURCE
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#define CONFIG_CMD_FAT
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#define CONFIG_DOS_PARTITION
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
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@ -274,6 +274,14 @@ unsigned long get_board_ddr_clk(void);
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/* I2C bus multiplexer */
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#define I2C_MUX_CH_DEFAULT 0x8
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/*
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* MMC
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*/
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#ifdef CONFIG_MMC
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#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
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QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
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#endif
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/*
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* RTC configuration
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*/
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@ -304,7 +312,16 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_CMD_NET
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#endif
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/* MMC */
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#define CONFIG_MMC
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#ifdef CONFIG_MMC
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#define CONFIG_CMD_MMC
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#define CONFIG_FSL_ESDHC
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#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
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#define CONFIG_GENERIC_MMC
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#define CONFIG_CMD_FAT
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#define CONFIG_DOS_PARTITION
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#endif
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/* Initial environment variables */
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#undef CONFIG_EXTRA_ENV_SETTINGS
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@ -277,7 +277,16 @@ unsigned long get_board_sys_clk(void);
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#define CONFIG_CMD_NET
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#endif
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/* MMC */
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#define CONFIG_MMC
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#ifdef CONFIG_MMC
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#define CONFIG_CMD_MMC
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#define CONFIG_FSL_ESDHC
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#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
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#define CONFIG_GENERIC_MMC
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#define CONFIG_CMD_FAT
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#define CONFIG_DOS_PARTITION
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#endif
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/* Initial environment variables */
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#undef CONFIG_EXTRA_ENV_SETTINGS
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@ -158,7 +158,11 @@
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#define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */
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struct fsl_esdhc_cfg {
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#ifdef CONFIG_LS2085A
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u64 esdhc_base;
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#else
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u32 esdhc_base;
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#endif
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u32 sdhc_clk;
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u8 max_bus_width;
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struct mmc_config cfg;
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