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remarkable-uboot
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Merge branch 'master' of git://git.denx.de/u-boot-dm

utp
Tom Rini 2015-01-30 09:24:42 -05:00
parent 0f274f5376 85df958ce2
commit 8e3da9dd11
185 changed files with 4646 additions and 1619 deletions
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3
Kconfig
View File

@ -116,8 +116,9 @@ config FIT_VERBOSE
depends on FIT
config FIT_SIGNATURE
bool "Enabel signature verification of FIT uImages"
bool "Enable signature verification of FIT uImages"
depends on FIT
select RSA
help
This option enables signature verification of FIT uImages,
using a hash signed and verified using RSA.

7
Makefile
View File

@ -776,6 +776,13 @@ ifneq ($(CONFIG_SYS_GENERIC_BOARD),y)
@echo "See doc/README.generic-board for further information"
@echo "===================================================="
endif
ifeq ($(CONFIG_DM_I2C_COMPAT),y)
@echo "===================== WARNING ======================"
@echo "This board uses CONFIG_DM_I2C_COMPAT. Please remove"
@echo "(possibly in a subsequent patch in your series)"
@echo "before sending patches to the mailing list."
@echo "===================================================="
endif
PHONY += dtbs
dtbs dts/dt.dtb: checkdtc u-boot

7
README
View File

@ -3176,8 +3176,13 @@ CBFS (Coreboot Filesystem) support
This enables the RSA algorithm used for FIT image verification
in U-Boot. See doc/uImage.FIT/signature.txt for more information.
The Modular Exponentiation algorithm in RSA is implemented using
driver model. So CONFIG_DM needs to be enabled by default for this
library to function.
The signing part is build into mkimage regardless of this
option.
option. The software based modular exponentiation is built into
mkimage irrespective of this option.
- bootcount support:
CONFIG_BOOTCOUNT_LIMIT

27
arch/arm/cpu/armv7/exynos/pinmux.c
View File

@ -266,22 +266,33 @@ static void exynos5_sromc_config(int flags)
static void exynos5_i2c_config(int peripheral, int flags)
{
int func01, func23;
/* High-Speed I2C */
if (flags & PINMUX_FLAG_HS_MODE) {
func01 = 4;
func23 = 4;
} else {
func01 = 2;
func23 = 3;
}
switch (peripheral) {
case PERIPH_ID_I2C0:
gpio_cfg_pin(EXYNOS5_GPIO_B30, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5_GPIO_B31, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5_GPIO_B30, S5P_GPIO_FUNC(func01));
gpio_cfg_pin(EXYNOS5_GPIO_B31, S5P_GPIO_FUNC(func01));
break;
case PERIPH_ID_I2C1:
gpio_cfg_pin(EXYNOS5_GPIO_B32, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5_GPIO_B33, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5_GPIO_B32, S5P_GPIO_FUNC(func01));
gpio_cfg_pin(EXYNOS5_GPIO_B33, S5P_GPIO_FUNC(func01));
break;
case PERIPH_ID_I2C2:
gpio_cfg_pin(EXYNOS5_GPIO_A06, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_A07, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_A06, S5P_GPIO_FUNC(func23));
gpio_cfg_pin(EXYNOS5_GPIO_A07, S5P_GPIO_FUNC(func23));
break;
case PERIPH_ID_I2C3:
gpio_cfg_pin(EXYNOS5_GPIO_A12, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_A13, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_A12, S5P_GPIO_FUNC(func23));
gpio_cfg_pin(EXYNOS5_GPIO_A13, S5P_GPIO_FUNC(func23));
break;
case PERIPH_ID_I2C4:
gpio_cfg_pin(EXYNOS5_GPIO_A20, S5P_GPIO_FUNC(0x3));

2
arch/arm/cpu/tegra20-common/pmu.c
View File

@ -52,7 +52,7 @@ int pmu_set_nominal(void)
debug("%s: Cannot find DVC I2C bus\n", __func__);
return ret;
}
ret = i2c_get_chip(bus, PMI_I2C_ADDRESS, &dev);
ret = i2c_get_chip(bus, PMI_I2C_ADDRESS, 1, &dev);
if (ret) {
debug("%s: Cannot find DVC I2C chip\n", __func__);
return ret;

31
arch/arm/dts/exynos4.dtsi
View File

@ -51,56 +51,64 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
interrupts = <0 0 0>;
reg = <0x13860000 0x100>;
interrupts = <0 56 0>;
};
i2c@13870000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
interrupts = <1 1 0>;
reg = <0x13870000 0x100>;
interrupts = <1 57 0>;
};
i2c@13880000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
interrupts = <2 2 0>;
reg = <0x13880000 0x100>;
interrupts = <2 58 0>;
};
i2c@13890000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
interrupts = <3 3 0>;
reg = <0x13890000 0x100>;
interrupts = <3 59 0>;
};
i2c@138a0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
interrupts = <4 4 0>;
reg = <0x138a0000 0x100>;
interrupts = <4 60 0>;
};
i2c@138b0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
interrupts = <5 5 0>;
reg = <0x138b0000 0x100>;
interrupts = <5 61 0>;
};
i2c@138c0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
interrupts = <6 6 0>;
reg = <0x138c0000 0x100>;
interrupts = <6 62 0>;
};
i2c@138d0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
interrupts = <7 7 0>;
reg = <0x138d0000 0x100>;
interrupts = <7 63 0>;
};
sdhci@12510000 {
@ -143,11 +151,4 @@
interrupts = <0 131 0>;
};
gpio: gpio {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};

2
arch/arm/dts/exynos4210-origen.dts
View File

@ -36,7 +36,7 @@
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
cd-gpios = <&gpio 0xA2 0>;
cd-gpios = <&gpk2 2 0>;
};
sdhci@12540000 {

4
arch/arm/dts/exynos4210-trats.dts
View File

@ -101,7 +101,7 @@
sdhci@12510000 {
samsung,bus-width = <8>;
samsung,timing = <1 3 3>;
pwr-gpios = <&gpio 146 0>;
pwr-gpios = <&gpk0 2 0>;
};
sdhci@12520000 {
@ -111,7 +111,7 @@
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
cd-gpios = <&gpio 284 0>;
cd-gpios = <&gpx3 4 0>;
};
sdhci@12540000 {

12
arch/arm/dts/exynos4210-universal_c210.dts
View File

@ -24,7 +24,7 @@
sdhci@12510000 {
samsung,bus-width = <8>;
samsung,timing = <1 3 3>;
pwr-gpios = <&gpio 146 0>;
pwr-gpios = <&gpk0 2 0>;
};
sdhci@12520000 {
@ -34,7 +34,7 @@
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
cd-gpios = <&gpio 284 0>;
cd-gpios = <&gpx3 4 0>;
};
sdhci@12540000 {
@ -43,10 +43,10 @@
soft-spi {
compatible = "u-boot,soft-spi";
cs-gpio = <&gpio 235 0>; /* Y43 */
sclk-gpio = <&gpio 225 0>; /* Y31 */
mosi-gpio = <&gpio 227 0>; /* Y33 */
miso-gpio = <&gpio 224 0>; /* Y30 */
cs-gpio = <&gpy4 3 0>;
sclk-gpio = <&gpy3 1 0>;
mosi-gpio = <&gpy3 3 0>;
miso-gpio = <&gpy3 0 0>;
spi-delay-us = <1>;
#address-cells = <1>;
#size-cells = <0>;

9
arch/arm/dts/exynos4412-odroid.dts
View File

@ -16,6 +16,13 @@
aliases {
i2c0 = "/i2c@13860000";
i2c1 = "/i2c@13870000";
i2c2 = "/i2c@13880000";
i2c3 = "/i2c@13890000";
i2c4 = "/i2c@138a0000";
i2c5 = "/i2c@138b0000";
i2c6 = "/i2c@138c0000";
i2c7 = "/i2c@138d0000";
serial0 = "/serial@13800000";
console = "/serial@13810000";
mmc2 = "sdhci@12530000";
@ -51,7 +58,7 @@
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
cd-gpios = <&gpio 122 0>;
cd-gpios = <&gpk2 2 0>;
};
sdhci@12540000 {

6
arch/arm/dts/exynos4412-trats2.dts
View File

@ -416,7 +416,7 @@
sdhci@12510000 {
samsung,bus-width = <8>;
samsung,timing = <1 3 3>;
pwr-gpios = <&gpio 0x6a 0>;
pwr-gpios = <&gpk0 4 0>;
status = "disabled";
};
@ -427,7 +427,7 @@
sdhci@12530000 {
samsung,bus-width = <4>;
samsung,timing = <1 2 3>;
cd-gpios = <&gpio 0x7a 0>;
cd-gpios = <&gpk2 2 0>;
};
sdhci@12540000 {
@ -437,7 +437,7 @@
dwmmc@12550000 {
samsung,bus-width = <8>;
samsung,timing = <2 1 0>;
pwr-gpios = <&gpio 0x6a 0>;
pwr-gpios = <&gpk0 4 0>;
fifoth_val = <0x203f0040>;
bus_hz = <400000000>;
div = <0x3>;

4
arch/arm/dts/exynos5.dtsi
View File

@ -6,6 +6,7 @@
*/
#include "skeleton.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "samsung,exynos5";
@ -247,7 +248,4 @@
u-boot,dm-pre-reloc;
id = <3>;
};
gpio: gpio {
};
};

8
arch/arm/dts/exynos5250-arndale.dts
View File

@ -15,6 +15,14 @@
compatible = "samsung,arndale", "samsung,exynos5250";
aliases {
i2c0 = "/i2c@12c60000";
i2c1 = "/i2c@12c70000";
i2c2 = "/i2c@12c80000";
i2c3 = "/i2c@12c90000";
i2c4 = "/i2c@12ca0000";
i2c5 = "/i2c@12cb0000";
i2c6 = "/i2c@12cc0000";
i2c7 = "/i2c@12cd0000";
serial0 = "/serial@12C20000";
console = "/serial@12C20000";
};

2
arch/arm/dts/exynos5250-smdk5250.dts
View File

@ -146,6 +146,6 @@
};
ehci@12110000 {
samsung,vbus-gpio = <&gpio 0x316 0>; /* X26 */
samsung,vbus-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>;
};
};

11
arch/arm/dts/exynos5250-snow.dts
View File

@ -44,7 +44,8 @@
reg = <0x1e>;
compatible = "google,cros-ec";
i2c-max-frequency = <100000>;
ec-interrupt = <&gpio 182 1>;
u-boot,i2c-offset-len = <0>;
ec-interrupt = <&gpx1 6 GPIO_ACTIVE_LOW>;
};
power-regulator@48 {
@ -68,7 +69,7 @@
reg = <0>;
compatible = "google,cros-ec";
spi-max-frequency = <5000000>;
ec-interrupt = <&gpio 182 1>;
ec-interrupt = <&gpx1 6 GPIO_ACTIVE_LOW>;
optimise-flash-write;
status = "disabled";
};
@ -76,7 +77,7 @@
sound@3830000 {
samsung,codec-type = "max98095";
codec-enable-gpio = <&gpio 0xb7 0>;
codec-enable-gpio = <&gpx1 7 GPIO_ACTIVE_HIGH>;
};
sound@12d60000 {
@ -131,11 +132,11 @@
};
ehci@12110000 {
samsung,vbus-gpio = <&gpio 0xb1 0>; /* X11 */
samsung,vbus-gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>;
};
xhci@12000000 {
samsung,vbus-gpio = <&gpio 0xbf 0>; /* X27 */
samsung,vbus-gpio = <&gpx2 7 GPIO_ACTIVE_HIGH>;
};
tmu@10060000 {

8
arch/arm/dts/exynos5420-peach-pit.dts
View File

@ -17,7 +17,7 @@
"google,peach", "samsung,exynos5420", "samsung,exynos5";
config {
google,bad-wake-gpios = <&gpio 0x56 0>; /* gpx0-6 */
google,bad-wake-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
hwid = "PIT TEST A-A 7848";
lazy-init = <1>;
};
@ -108,7 +108,7 @@
spi-half-duplex;
spi-max-timeout-ms = <1100>;
spi-frame-header = <0xec>;
ec-interrupt = <&gpio 93 1>; /* GPX1_5 */
ec-interrupt = <&gpx1 5 GPIO_ACTIVE_LOW>;
/*
* This describes the flash memory within the EC. Note
@ -124,11 +124,11 @@
};
xhci@12000000 {
samsung,vbus-gpio = <&gpio 0x40 0>; /* H00 */
samsung,vbus-gpio = <&gph0 0 GPIO_ACTIVE_HIGH>;
};
xhci@12400000 {
samsung,vbus-gpio = <&gpio 0x41 0>; /* H01 */
samsung,vbus-gpio = <&gph0 1 GPIO_ACTIVE_HIGH>;
};
fimd@14400000 {

2
arch/arm/dts/exynos5422-odroidxu3.dts
View File

@ -32,7 +32,7 @@
};
ehci@12110000 {
samsung,vbus-gpio = <&gpio 0x66 0>; /* X26 */
samsung,vbus-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>;
};
serial@12C20000 {

10
arch/arm/dts/exynos5800-peach-pi.dts
View File

@ -17,7 +17,7 @@
"google,peach", "samsung,exynos5800", "samsung,exynos5";
config {
google,bad-wake-gpios = <&gpio 0x56 0>; /* gpx0-6 */
google,bad-wake-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
hwid = "PIT TEST A-A 7848";
lazy-init = <1>;
};
@ -32,7 +32,7 @@
mem-manuf = "samsung";
mem-type = "ddr3";
clock-frequency = <800000000>;
arm-frequency = <1700000000>;
arm-frequency = <900000000>;
};
tmu@10060000 {
@ -102,7 +102,7 @@
spi-half-duplex;
spi-max-timeout-ms = <1100>;
spi-frame-header = <0xec>;
ec-interrupt = <&gpio 93 1>; /* GPX1_5 */
ec-interrupt = <&gpx1 5 GPIO_ACTIVE_LOW>;
/*
* This describes the flash memory within the EC. Note
@ -118,11 +118,11 @@
};
xhci@12000000 {
samsung,vbus-gpio = <&gpio 0x40 0>; /* H00 */
samsung,vbus-gpio = <&gph0 0 GPIO_ACTIVE_HIGH>;
};
xhci@12400000 {
samsung,vbus-gpio = <&gpio 0x41 0>; /* H01 */
samsung,vbus-gpio = <&gph0 1 GPIO_ACTIVE_HIGH>;
};
fimd@14400000 {

5
arch/arm/dts/tegra114-dalmore.dts
View File

@ -57,7 +57,7 @@
};
sdhci@78000400 {
cd-gpios = <&gpio 170 1>; /* gpio PV2 */
cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
bus-width = <4>;
status = "okay";
};
@ -68,8 +68,7 @@
};
usb@7d008000 {
/* SPDIF_IN: USB_VBUS_EN1 */
nvidia,vbus-gpio = <&gpio 86 0>;
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
status = "okay";
};
};

9
arch/arm/dts/tegra124-jetson-tk1.dts
View File

@ -303,8 +303,9 @@
sdhci@700b0400 {
status = "okay";
cd-gpios = <&gpio 170 1>; /* gpio PV2 */
power-gpios = <&gpio 136 0>; /* gpio PR0 */
cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@ -316,12 +317,12 @@
usb@7d000000 {
status = "okay";
dr_mode = "otg";
nvidia,vbus-gpio = <&gpio 108 0>; /* gpio PN4, USB_VBUS_EN0 */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
};
usb@7d008000 {
status = "okay";
nvidia,vbus-gpio = <&gpio 109 0>; /* gpio PN5, USB_VBUS_EN1 */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
};
regulators {

9
arch/arm/dts/tegra124-venice2.dts
View File

@ -72,8 +72,9 @@
sdhci@700b0400 {
status = "okay";
cd-gpios = <&gpio 170 0>; /* gpio PV2 */
power-gpios = <&gpio 136 0>; /* gpio PR0 */
cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
bus-width = <4>;
};
@ -85,11 +86,11 @@
usb@7d000000 {
status = "okay";
dr_mode = "otg";
nvidia,vbus-gpio = <&gpio 108 0>; /* gpio PN4, USB_VBUS_EN0 */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
};
usb@7d008000 {
status = "okay";
nvidia,vbus-gpio = <&gpio 109 0>; /* gpio PN5, USB_VBUS_EN1 */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
};
};

10
arch/arm/dts/tegra20-colibri_t20_iris.dts
View File

@ -22,16 +22,16 @@
};
usb@c5004000 {
nvidia,phy-reset-gpio = <&gpio 169 0>; /* PV1 */
nvidia,vbus-gpio = <&gpio 217 0>; /* PBB1 */
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
};
usb@c5008000 {
nvidia,vbus-gpio = <&gpio 178 1>; /* PW2 low-active */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
};
nand-controller@70008000 {
nvidia,wp-gpios = <&gpio 144 0>; /* PS0 */
nvidia,wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
nvidia,width = <8>;
nvidia,timing = <15 100 25 80 25 10 15 10 100>;
@ -43,7 +43,7 @@
sdhci@c8000600 {
status = "okay";
cd-gpios = <&gpio 23 1>; /* gpio PC7 */
cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
bus-width = <4>;
};
};

28
arch/arm/dts/tegra20-harmony.dts
View File

@ -37,7 +37,7 @@
};
nand-controller@70008000 {
nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */
nvidia,wp-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
nvidia,width = <8>;
nvidia,timing = <26 100 20 80 20 10 12 10 70>;
nand@0 {
@ -67,22 +67,22 @@
};
usb@c5004000 {
nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 0>;
};
sdhci@c8000200 {
status = "okay";
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
power-gpios = <&gpio 155 0>; /* gpio PT3 */
cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
sdhci@c8000600 {
status = "okay";
cd-gpios = <&gpio 58 1>; /* gpio PH2 */
wp-gpios = <&gpio 59 0>; /* gpio PH3 */
power-gpios = <&gpio 70 0>; /* gpio PI6 */
cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
bus-width = <8>;
};
@ -100,10 +100,14 @@
vsyncx-active-high;
nvidia,bits-per-pixel = <16>;
nvidia,pwm = <&pwm 0 0>;
nvidia,backlight-enable-gpios = <&gpio 13 0>; /* PB5 */
nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */
nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
nvidia,panel-vdd-gpios = <&gpio 22 0>; /* PC6 */
nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(B, 5)
GPIO_ACTIVE_HIGH>;
nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2)
GPIO_ACTIVE_HIGH>;
nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
GPIO_ACTIVE_HIGH>;
nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(C, 6)
GPIO_ACTIVE_HIGH>;
nvidia,panel-timings = <0 0 200 0 0>;
};
};

9
arch/arm/dts/tegra20-medcom-wide.dts
View File

@ -73,9 +73,12 @@
nvidia,bits-per-pixel = <16>;
nvidia,pwm = <&pwm 0 500000>;
nvidia,backlight-enable-gpios = <&gpio 13 0>; /* PB5 */
nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */
nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(B, 5)
GPIO_ACTIVE_HIGH>;
nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2)
GPIO_ACTIVE_HIGH>;
nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
GPIO_ACTIVE_HIGH>;
nvidia,panel-timings = <0 0 0 0>;
};
};

18
arch/arm/dts/tegra20-paz00.dts
View File

@ -61,9 +61,9 @@
sdhci@c8000000 {
status = "okay";
cd-gpios = <&gpio 173 1>; /* gpio PV5 */
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
power-gpios = <&gpio 169 0>; /* gpio PV1 */
cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@ -86,10 +86,14 @@
hsync-active-high;
nvidia,bits-per-pixel = <16>;
nvidia,pwm = <&pwm 0 0>;
nvidia,backlight-enable-gpios = <&gpio 164 0>; /* PU4 */
nvidia,lvds-shutdown-gpios = <&gpio 102 0>; /* PM6 */
nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
nvidia,panel-vdd-gpios = <&gpio 4 0>; /* PA4 */
nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(U, 4)
GPIO_ACTIVE_HIGH>;
nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(M, 6)
GPIO_ACTIVE_HIGH>;
nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
GPIO_ACTIVE_HIGH>;
nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(A, 4)
GPIO_ACTIVE_HIGH>;
nvidia,panel-timings = <400 4 203 17 15>;
};
};

22
arch/arm/dts/tegra20-seaboard.dts
View File

@ -65,7 +65,7 @@
};
nand-controller@70008000 {
nvidia,wp-gpios = <&gpio 59 0>; /* PH3 */
nvidia,wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
nvidia,width = <8>;
nvidia,timing = <26 100 20 80 20 10 12 10 70>;
nand@0 {
@ -151,7 +151,7 @@
};
usb@c5000000 {
nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
dr_mode = "otg";
};
@ -161,9 +161,9 @@
sdhci@c8000400 {
status = "okay";
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
power-gpios = <&gpio 70 0>; /* gpio PI6 */
cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@ -186,10 +186,14 @@
hsync-active-high;
nvidia,bits-per-pixel = <16>;
nvidia,pwm = <&pwm 2 0>;
nvidia,backlight-enable-gpios = <&gpio 28 0>; /* PD4 */
nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */
nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
nvidia,panel-vdd-gpios = <&gpio 22 0>; /* PC6 */
nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(D, 4)
GPIO_ACTIVE_HIGH>;
nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2)
GPIO_ACTIVE_HIGH>;
nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
GPIO_ACTIVE_HIGH>;
nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(C, 6)
GPIO_ACTIVE_HIGH>;
nvidia,panel-timings = <400 4 203 17 15>;
};
};

9
arch/arm/dts/tegra20-tamonten.dtsi
View File

@ -14,7 +14,8 @@
pll-supply = <&hdmi_pll_reg>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
GPIO_ACTIVE_HIGH>;
};
};
@ -280,7 +281,7 @@
};
nand-controller@70008000 {
nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */
nvidia,wp-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
nvidia,width = <8>;
nvidia,timing = <26 100 20 80 20 10 12 10 70>;
@ -476,8 +477,8 @@
};
sdhci@c8000600 {
cd-gpios = <&gpio 58 1>; /* gpio PH2 */
wp-gpios = <&gpio 59 0>; /* gpio PH3 */
cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
status = "okay";
};

9
arch/arm/dts/tegra20-tec.dts
View File

@ -73,9 +73,12 @@
nvidia,bits-per-pixel = <16>;
nvidia,pwm = <&pwm 0 500000>;
nvidia,backlight-enable-gpios = <&gpio 13 0>; /* PB5 */
nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */
nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(B, 5)
GPIO_ACTIVE_HIGH>;
nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2)
GPIO_ACTIVE_HIGH>;
nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
GPIO_ACTIVE_HIGH>;
nvidia,panel-timings = <0 0 0 0>;
};
};

8
arch/arm/dts/tegra20-trimslice.dts
View File

@ -62,7 +62,7 @@
};
usb@c5000000 {
nvidia,vbus-gpio = <&gpio 170 0>; /* PV2 */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
};
usb@c5004000 {
@ -76,8 +76,8 @@
sdhci@c8000600 {
status = "okay";
cd-gpios = <&gpio 121 1>; /* gpio PP1 */
wp-gpios = <&gpio 122 0>; /* gpio PP2 */
cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@ -111,7 +111,7 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio TEGRA_GPIO(V, 2) 0>;
gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
regulator-always-on;
regulator-boot-on;
};

18
arch/arm/dts/tegra20-ventana.dts
View File

@ -61,9 +61,9 @@
sdhci@c8000400 {
status = "okay";
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
power-gpios = <&gpio 70 0>; /* gpio PI6 */
cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@ -86,10 +86,14 @@
vsync-active-high;
nvidia,bits-per-pixel = <16>;
nvidia,pwm = <&pwm 2 0>;
nvidia,backlight-enable-gpios = <&gpio 28 0>; /* PD4 */
nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */
nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
nvidia,panel-vdd-gpios = <&gpio 22 0>; /* PC6 */
nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(D, 4)
GPIO_ACTIVE_HIGH>;
nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2)
GPIO_ACTIVE_HIGH>;
nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0)
GPIO_ACTIVE_HIGH>;
nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(C, 6)
GPIO_ACTIVE_HIGH>;
nvidia,panel-timings = <0 0 200 0 0>;
};
};

2
arch/arm/dts/tegra20-whistler.dts
View File

@ -66,7 +66,7 @@
sdhci@c8000400 {
status = "okay";
wp-gpios = <&gpio 173 0>; /* gpio PV5 */
wp-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
bus-width = <8>;
};

10
arch/arm/dts/tegra30-apalis.dts
View File

@ -243,13 +243,13 @@
sdhci@78000000 {
status = "okay";
bus-width = <4>;
cd-gpios = <&gpio 229 1>; /* PCC5, SD1_CD# */
cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>;
};
sdhci@78000400 {
status = "okay";
bus-width = <8>;
cd-gpios = <&gpio 171 1>; /* PV3, MMC1_CD# */
cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
};
sdhci@78000600 {
@ -262,20 +262,20 @@
usb@7d000000 {
status = "okay";
dr_mode = "peripheral";
nvidia,vbus-gpio = <&gpio 157 0>; /* PT5, USBO1_EN */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
};
/* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */
usb@7d004000 {
status = "okay";
nvidia,vbus-gpio = <&gpio 233 0>; /* PDD1, USBH_EN */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
phy_type = "utmi";
};
/* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */
usb@7d008000 {
status = "okay";
nvidia,vbus-gpio = <&gpio 233 0>; /* PDD1, USBH_EN */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
};
regulators {

10
arch/arm/dts/tegra30-beaver.dts
View File

@ -196,9 +196,9 @@
sdhci@78000000 {
status = "okay";
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
wp-gpios = <&gpio 155 0>; /* gpio PT3 */
power-gpios = <&gpio 31 0>; /* gpio PD7 */
cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@ -210,11 +210,11 @@
usb@7d000000 {
status = "okay";
dr_mode = "otg";
nvidia,vbus-gpio = <&gpio 238 0>; /* gpio DD6, PEX_L1_CLKREQ */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>;
};
usb@7d008000 {
nvidia,vbus-gpio = <&gpio 236 0>; /* PDD4 */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
status = "okay";
};

8
arch/arm/dts/tegra30-cardhu.dts
View File

@ -185,9 +185,9 @@
sdhci@78000000 {
status = "okay";
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
wp-gpios = <&gpio 155 0>; /* gpio PT3 */
power-gpios = <&gpio 31 0>; /* gpio PD7 */
cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};
@ -197,7 +197,7 @@
};
usb@7d008000 {
nvidia,vbus-gpio = <&gpio 236 0>; /* PDD4 */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
status = "okay";
};

6
arch/arm/dts/tegra30-colibri.dts
View File

@ -64,7 +64,7 @@
sdhci@78000200 {
status = "okay";
bus-width = <4>;
cd-gpios = <&gpio 23 1>; /* PC7, MMCD */
cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
};
sdhci@78000600 {
@ -83,12 +83,12 @@
usb@7d004000 {
status = "okay";
phy_type = "utmi";
nvidia,vbus-gpio = <&gpio 234 0>; /* PDD2, VBUS_LAN */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
};
/* EHCI instance 2: USB3_DP/N -> USBH_P/N */
usb@7d008000 {
status = "okay";
nvidia,vbus-gpio = <&gpio 178 1>; /* PW2, USBH_PEN */
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
};
};

4
arch/arm/dts/tegra30-tamonten.dtsi
View File

@ -55,8 +55,8 @@
/* SD slot on the base board */
sdhci@78000400 {
cd-gpios = <&gpio 69 1>; /* gpio PI5 */
wp-gpios = <&gpio 67 0>; /* gpio PI3 */
cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>;
bus-width = <4>;
};

3
arch/arm/include/asm/arch-exynos/pinmux.h
View File

@ -23,6 +23,9 @@ enum {
/* Flags for SROM controller */
PINMUX_FLAG_BANK = 3 << 0, /* bank number (0-3) */
PINMUX_FLAG_16BIT = 1 << 2, /* 16-bit width */
/* Flags for I2C */
PINMUX_FLAG_HS_MODE = 1 << 1, /* I2C High Speed Mode */
};
/**

0
arch/arm/include/asm/arch-pantheon/gpio.h 100644
View File

7
arch/arm/include/asm/arch-tegra/tegra_mmc.h
View File

@ -10,6 +10,7 @@
#define __TEGRA_MMC_H_
#include <fdtdec.h>
#include <asm/gpio.h>
/* for mmc_config definition */
#include <mmc.h>
@ -134,9 +135,9 @@ struct mmc_host {
int enabled; /* 1 to enable, 0 to disable */
int width; /* Bus Width, 1, 4 or 8 */
enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */
struct fdt_gpio_state cd_gpio; /* Change Detect GPIO */
struct fdt_gpio_state pwr_gpio; /* Power GPIO */
struct fdt_gpio_state wp_gpio; /* Write Protect GPIO */
struct gpio_desc cd_gpio; /* Change Detect GPIO */
struct gpio_desc pwr_gpio; /* Power GPIO */
struct gpio_desc wp_gpio; /* Write Protect GPIO */
unsigned int version; /* SDHCI spec. version */
unsigned int clock; /* Current clock (MHz) */
struct mmc_config cfg; /* mmc configuration */

9
arch/arm/include/asm/arch-tegra20/display.h
View File

@ -10,6 +10,7 @@
#include <asm/arch/dc.h>
#include <fdtdec.h>
#include <asm/gpio.h>
/* This holds information about a window which can be displayed */
struct disp_ctl_win {
@ -72,10 +73,10 @@ struct fdt_panel_config {
int pwm_channel; /* PWM channel to use for backlight */
enum lcd_cache_t cache_type;
struct fdt_gpio_state backlight_en; /* GPIO for backlight enable */
struct fdt_gpio_state lvds_shutdown; /* GPIO for lvds shutdown */
struct fdt_gpio_state backlight_vdd; /* GPIO for backlight vdd */
struct fdt_gpio_state panel_vdd; /* GPIO for panel vdd */
struct gpio_desc backlight_en; /* GPIO for backlight enable */
struct gpio_desc lvds_shutdown; /* GPIO for lvds shutdown */
struct gpio_desc backlight_vdd; /* GPIO for backlight vdd */
struct gpio_desc panel_vdd; /* GPIO for panel vdd */
/*
* Panel required timings
* Timing 1: delay between panel_vdd-rise and data-rise

15
arch/arm/include/asm/arch-zynq/gpio.h
View File

@ -7,19 +7,4 @@
#ifndef _ZYNQ_GPIO_H
#define _ZYNQ_GPIO_H
inline int gpio_get_value(unsigned gpio)
{
return 0;
}
inline int gpio_set_value(unsigned gpio, int val)
{
return 0;
}
inline int gpio_request(unsigned gpio, const char *label)
{
return 0;
}
#endif /* _ZYNQ_GPIO_H */

3
arch/blackfin/cpu/cpu.c
View File

@ -24,6 +24,7 @@
#include "cpu.h"
#include "initcode.h"
#include "exports.h"
ulong bfin_poweron_retx;
DECLARE_GLOBAL_DATA_PTR;
@ -121,7 +122,7 @@ static void display_global_data(void)
printf(" |-ram_size: %lx\n", gd->ram_size);
printf(" |-env_addr: %lx\n", gd->env_addr);
printf(" |-env_valid: %lx\n", gd->env_valid);
printf(" |-jt(%p): %p\n", gd->jt, *(gd->jt));
printf(" |-jt(%p): %p\n", gd->jt, gd->jt->get_version);
printf(" \\-bd: %p\n", gd->bd);
printf(" |-bi_boot_params: %lx\n", bd->bi_boot_params);
printf(" |-bi_memstart: %lx\n", bd->bi_memstart);

11
arch/sandbox/dts/sandbox.dts
View File

@ -19,6 +19,7 @@
colour = "cyan";
sides = <3>;
character = <83>;
light-gpios = <&gpio_a 2>, <&gpio_b 6 0>;
};
square {
compatible = "demo-shape";
@ -126,7 +127,7 @@
0x070b0067 0x070c0069>;
};
gpio_a: gpios {
gpio_a: gpios@0 {
gpio-controller;
compatible = "sandbox,gpio";
#gpio-cells = <1>;
@ -134,6 +135,14 @@
num-gpios = <20>;
};
gpio_b: gpios@1 {
gpio-controller;
compatible = "sandbox,gpio";
#gpio-cells = <2>;
gpio-bank-name = "b";
num-gpios = <10>;
};
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;

2
board/BuS/eb_cpux9k2/cpux9k2.c
View File

@ -98,7 +98,7 @@ int misc_init_r(void)
puts("Error: invalid MAC at EEPROM\n");
}
}
gd->jt[XF_do_reset] = (void *) do_reset;
gd->jt->do_reset = do_reset;
#ifdef CONFIG_STATUS_LED
status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING);

4
board/avionic-design/common/tamonten-ng.c
View File

@ -55,12 +55,12 @@ void pmu_write(uchar reg, uchar data)
struct udevice *dev;
int ret;
ret = i2c_get_chip_for_busnum(4, PMU_I2C_ADDRESS, &dev);
ret = i2c_get_chip_for_busnum(4, PMU_I2C_ADDRESS, 1, &dev);
if (ret) {
debug("%s: Cannot find PMIC I2C chip\n", __func__);
return;
}
i2c_write(dev, reg, &data, 1);
dm_i2c_write(dev, reg, &data, 1);
}
/*

12
board/nvidia/cardhu/cardhu.c
View File

@ -46,7 +46,7 @@ void board_sdmmc_voltage_init(void)
int ret;
int i;
ret = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, &dev);
ret = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, 1, &dev);
if (ret) {
debug("%s: Cannot find PMIC I2C chip\n", __func__);
return;
@ -57,7 +57,7 @@ void board_sdmmc_voltage_init(void)
reg = 0x32;
for (i = 0; i < MAX_I2C_RETRY; ++i) {
if (i2c_write(dev, reg, data_buffer, 1))
if (dm_i2c_write(dev, reg, data_buffer, 1))
udelay(100);
}
@ -66,7 +66,7 @@ void board_sdmmc_voltage_init(void)
reg = 0x67;
for (i = 0; i < MAX_I2C_RETRY; ++i) {
if (i2c_write(dev, reg, data_buffer, 1))
if (dm_i2c_write(dev, reg, data_buffer, 1))
udelay(100);
}
}
@ -94,7 +94,7 @@ int tegra_pcie_board_init(void)
u8 addr, data[1];
int err;
err = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, &dev);
err = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, 1, &dev);
if (err) {
debug("failed to find PMU bus\n");
return err;
@ -104,7 +104,7 @@ int tegra_pcie_board_init(void)
data[0] = 0x15;
addr = 0x30;
err = i2c_write(dev, addr, data, 1);
err = dm_i2c_write(dev, addr, data, 1);
if (err) {
debug("failed to set VDD supply\n");
return err;
@ -121,7 +121,7 @@ int tegra_pcie_board_init(void)
data[0] = 0x15;
addr = 0x31;
err = i2c_write(dev, addr, data, 1);
err = dm_i2c_write(dev, addr, data, 1);
if (err) {
debug("failed to set AVDD supply\n");
return err;

10
board/nvidia/dalmore/dalmore.c
View File

@ -55,7 +55,7 @@ void board_sdmmc_voltage_init(void)
uchar reg, data_buffer[1];
int ret;
ret = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, &dev);
ret = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, 1, &dev);
if (ret) {
debug("%s: Cannot find PMIC I2C chip\n", __func__);
return;
@ -65,7 +65,7 @@ void board_sdmmc_voltage_init(void)
data_buffer[0] = 0x31;
reg = 0x61;
ret = i2c_write(dev, reg, data_buffer, 1);
ret = dm_i2c_write(dev, reg, data_buffer, 1);
if (ret)
printf("%s: PMU i2c_write %02X<-%02X returned %d\n",
__func__, reg, data_buffer[0], ret);
@ -74,7 +74,7 @@ void board_sdmmc_voltage_init(void)
data_buffer[0] = 0x01;
reg = 0x60;
ret = i2c_write(dev, reg, data_buffer, 1);
ret = dm_i2c_write(dev, reg, data_buffer, 1);
if (ret)
printf("%s: PMU i2c_write %02X<-%02X returned %d\n",
__func__, reg, data_buffer[0], ret);
@ -83,12 +83,12 @@ void board_sdmmc_voltage_init(void)
data_buffer[0] = 0x03;
reg = 0x14;
ret = i2c_get_chip_for_busnum(0, BAT_I2C_ADDRESS, &dev);
ret = i2c_get_chip_for_busnum(0, BAT_I2C_ADDRESS, 1, &dev);
if (ret) {
debug("%s: Cannot find charger I2C chip\n", __func__);
return;
}
ret = i2c_write(dev, reg, data_buffer, 1);
ret = dm_i2c_write(dev, reg, data_buffer, 1);
if (ret)
printf("%s: BAT i2c_write %02X<-%02X returned %d\n",
__func__, reg, data_buffer[0], ret);

14
board/nvidia/whistler/whistler.c
View File

@ -27,21 +27,21 @@ void pin_mux_mmc(void)
int ret;
/* Turn on MAX8907B LDO12 to 2.8V for J40 power */
ret = i2c_get_chip_for_busnum(0, 0x3c, &dev);
ret = i2c_get_chip_for_busnum(0, 0x3c, 1, &dev);
if (ret) {
printf("%s: Cannot find MAX8907B I2C chip\n", __func__);
return;
}
val = 0x29;
ret = i2c_write(dev, 0x46, &val, 1);
ret = dm_i2c_write(dev, 0x46, &val, 1);
if (ret)
printf("i2c_write 0 0x3c 0x46 failed: %d\n", ret);
val = 0x00;
ret = i2c_write(dev, 0x45, &val, 1);
ret = dm_i2c_write(dev, 0x45, &val, 1);
if (ret)
printf("i2c_write 0 0x3c 0x45 failed: %d\n", ret);
val = 0x1f;
ret = i2c_write(dev, 0x44, &val, 1);
ret = dm_i2c_write(dev, 0x44, &val, 1);
if (ret)
printf("i2c_write 0 0x3c 0x44 failed: %d\n", ret);
@ -64,17 +64,17 @@ void pin_mux_usb(void)
*/
/* Turn on TAC6416's GPIO 0+1 for USB1/3's VBUS */
ret = i2c_get_chip_for_busnum(0, 0x20, &dev);
ret = i2c_get_chip_for_busnum(0, 0x20, 1, &dev);
if (ret) {
printf("%s: Cannot find TAC6416 I2C chip\n", __func__);
return;
}
val = 0x03;
ret = i2c_write(dev, 2, &val, 1);
ret = dm_i2c_write(dev, 2, &val, 1);
if (ret)
printf("i2c_write 0 0x20 2 failed: %d\n", ret);
val = 0xfc;
ret = i2c_write(dev, 6, &val, 1);
ret = dm_i2c_write(dev, 6, &val, 1);
if (ret)
printf("i2c_write 0 0x20 6 failed: %d\n", ret);
}

14
board/samsung/odroid/odroid.c
View File

@ -415,15 +415,6 @@ static int pmic_init_max77686(void)
return 0;
}
#ifdef CONFIG_SYS_I2C_INIT_BOARD
static void board_init_i2c(void)
{
/* I2C_0 */
if (exynos_pinmux_config(PERIPH_ID_I2C0, PINMUX_FLAG_NONE))
debug("I2C%d not configured\n", (I2C_0));
}
#endif
int exynos_early_init_f(void)
{
board_clock_init();
@ -444,10 +435,7 @@ int exynos_init(void)
int exynos_power_init(void)
{
#ifdef CONFIG_SYS_I2C_INIT_BOARD
board_init_i2c();
#endif
pmic_init(I2C_0);
pmic_init(0);
pmic_init_max77686();
return 0;

8
board/toradex/apalis_t30/apalis_t30.c
View File

@ -42,7 +42,7 @@ int tegra_pcie_board_init(void)
u8 addr, data[1];
int err;
err = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, &dev);
err = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, 1, &dev);
if (err) {
debug("%s: Cannot find PMIC I2C chip\n", __func__);
return err;
@ -51,7 +51,7 @@ int tegra_pcie_board_init(void)
data[0] = 0x27;
addr = 0x25;
err = i2c_write(dev, addr, data, 1);
err = dm_i2c_write(dev, addr, data, 1);
if (err) {
debug("failed to set VDD supply\n");
return err;
@ -61,7 +61,7 @@ int tegra_pcie_board_init(void)
data[0] = 0x0D;
addr = 0x24;
err = i2c_write(dev, addr, data, 1);
err = dm_i2c_write(dev, addr, data, 1);
if (err) {
debug("failed to enable VDD supply\n");
return err;
@ -71,7 +71,7 @@ int tegra_pcie_board_init(void)
data[0] = 0x0D;
addr = 0x35;
err = i2c_write(dev, addr, data, 1);
err = dm_i2c_write(dev, addr, data, 1);
if (err) {
debug("failed to set AVDD supply\n");
return err;

2
common/Makefile
View File

@ -27,6 +27,8 @@ endif
# boards
obj-$(CONFIG_SYS_GENERIC_BOARD) += board_f.o
obj-$(CONFIG_SYS_GENERIC_BOARD) += board_r.o
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
obj-$(CONFIG_DISPLAY_BOARDINFO_LATE) += board_info.o
# core command
obj-y += cmd_boot.o

2
common/board_f.c
View File

@ -894,7 +894,7 @@ static init_fnc_t init_sequence_f[] = {
prt_mpc5xxx_clks,
#endif /* CONFIG_MPC5xxx */
#if defined(CONFIG_DISPLAY_BOARDINFO)
checkboard, /* display board info */
show_board_info,
#endif
INIT_FUNC_WATCHDOG_INIT
#if defined(CONFIG_MISC_INIT_F)

35
common/board_info.c 100644
View File

@ -0,0 +1,35 @@
/*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <libfdt.h>
#include <linux/compiler.h>
int __weak checkboard(void)
{
printf("Board: Unknown\n");
return 0;
}
/*
* If the root node of the DTB has a "model" property, show it.
* If CONFIG_OF_CONTROL is disabled or the "model" property is missing,
* fall back to checkboard().
*/
int show_board_info(void)
{
#ifdef CONFIG_OF_CONTROL
DECLARE_GLOBAL_DATA_PTR;
const char *model;
model = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
if (model) {
printf("Model: %s\n", model);
return 0;
}
#endif
return checkboard();
}

18
common/board_r.c
View File

@ -476,22 +476,6 @@ static int initr_api(void)
}
#endif
#ifdef CONFIG_DISPLAY_BOARDINFO_LATE
static int show_model_r(void)
{
/* Put this here so it appears on the LCD, now it is ready */
# ifdef CONFIG_OF_CONTROL
const char *model;
model = (char *)fdt_getprop(gd->fdt_blob, 0, "model", NULL);
printf("Model: %s\n", model ? model : "<unknown>");
# else
checkboard();
# endif
return 0;
}
#endif
/* enable exceptions */
#ifdef CONFIG_ARM
static int initr_enable_interrupts(void)
@ -801,7 +785,7 @@ init_fnc_t init_sequence_r[] = {
#endif
console_init_r, /* fully init console as a device */
#ifdef CONFIG_DISPLAY_BOARDINFO_LATE
show_model_r,
show_board_info,
#endif
#ifdef CONFIG_ARCH_MISC_INIT
arch_misc_init, /* miscellaneous arch-dependent init */

29
common/cmd_demo.c
View File

@ -39,6 +39,26 @@ static int do_demo_status(cmd_tbl_t *cmdtp, int flag, int argc,
return 0;
}
static int do_demo_light(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
int light;
int ret;
if (argc) {
light = simple_strtoul(argv[0], NULL, 16);
ret = demo_set_light(demo_dev, light);
} else {
ret = demo_get_light(demo_dev);
if (ret >= 0) {
printf("Light: %x\n", ret);
ret = 0;
}
}
return ret;
}
int do_demo_list(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
struct udevice *dev;
@ -61,6 +81,7 @@ int do_demo_list(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
static cmd_tbl_t demo_commands[] = {
U_BOOT_CMD_MKENT(list, 0, 1, do_demo_list, "", ""),
U_BOOT_CMD_MKENT(hello, 2, 1, do_demo_hello, "", ""),
U_BOOT_CMD_MKENT(light, 2, 1, do_demo_light, "", ""),
U_BOOT_CMD_MKENT(status, 1, 1, do_demo_status, "", ""),
};
@ -86,6 +107,10 @@ static int do_demo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
return cmd_process_error(cmdtp, ret);
argc--;
argv++;
} else {
demo_dev = NULL;
if (demo_cmd->cmd != do_demo_list)
return CMD_RET_USAGE;
}
ret = demo_cmd->cmd(demo_cmd, flag, argc, argv);
@ -98,5 +123,7 @@ U_BOOT_CMD(
"Driver model (dm) demo operations",
"list List available demo devices\n"
"demo hello <num> [<char>] Say hello\n"
"demo status <num> Get demo device status"
"demo light [<num>] Set or get the lights\n"
"demo status <num> Get demo device status\n"
"demo list List available demo devices"
);

52
common/cmd_i2c.c
View File

@ -83,12 +83,12 @@ DECLARE_GLOBAL_DATA_PTR;
/* Display values from last command.
* Memory modify remembered values are different from display memory.
*/
static uchar i2c_dp_last_chip;
static uint i2c_dp_last_chip;
static uint i2c_dp_last_addr;
static uint i2c_dp_last_alen;
static uint i2c_dp_last_length = 0x10;
static uchar i2c_mm_last_chip;
static uint i2c_mm_last_chip;
static uint i2c_mm_last_addr;
static uint i2c_mm_last_alen;
@ -133,7 +133,7 @@ static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
#ifdef CONFIG_DM_I2C
static struct udevice *i2c_cur_bus;
static int i2c_set_bus_num(unsigned int busnum)
static int cmd_i2c_set_bus_num(unsigned int busnum)
{
struct udevice *bus;
int ret;
@ -168,7 +168,7 @@ static int i2c_get_cur_bus_chip(uint chip_addr, struct udevice **devp)
if (ret)
return ret;
return i2c_get_chip(bus, chip_addr, devp);
return i2c_get_chip(bus, chip_addr, 1, devp);
}
#endif
@ -282,7 +282,7 @@ static int i2c_report_err(int ret, enum i2c_err_op op)
*/
static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
u_char chip;
uint chip;
uint devaddr, length;
int alen;
u_char *memaddr;
@ -323,7 +323,7 @@ static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv
if (!ret && alen != -1)
ret = i2c_set_chip_offset_len(dev, alen);
if (!ret)
ret = i2c_read(dev, devaddr, memaddr, length);
ret = dm_i2c_read(dev, devaddr, memaddr, length);
#else
ret = i2c_read(chip, devaddr, alen, memaddr, length);
#endif
@ -335,7 +335,7 @@ static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv
static int do_i2c_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
u_char chip;
uint chip;
uint devaddr, length;
int alen;
u_char *memaddr;
@ -381,7 +381,7 @@ static int do_i2c_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[
while (length-- > 0) {
#ifdef CONFIG_DM_I2C
ret = i2c_write(dev, devaddr++, memaddr++, 1);
ret = dm_i2c_write(dev, devaddr++, memaddr++, 1);
#else
ret = i2c_write(chip, devaddr++, alen, memaddr++, 1);
#endif
@ -444,7 +444,7 @@ static int do_i2c_flags(cmd_tbl_t *cmdtp, int flag, int argc,
*/
static int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
u_char chip;
uint chip;
uint addr, length;
int alen;
int j, nbytes, linebytes;
@ -513,7 +513,7 @@ static int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]
linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
#ifdef CONFIG_DM_I2C
ret = i2c_read(dev, addr, linebuf, linebytes);
ret = dm_i2c_read(dev, addr, linebuf, linebytes);
#else
ret = i2c_read(chip, addr, alen, linebuf, linebytes);
#endif
@ -563,7 +563,7 @@ static int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]
*/
static int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
uchar chip;
uint chip;
ulong addr;
int alen;
uchar byte;
@ -611,7 +611,7 @@ static int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]
while (count-- > 0) {
#ifdef CONFIG_DM_I2C
ret = i2c_write(dev, addr++, &byte, 1);
ret = dm_i2c_write(dev, addr++, &byte, 1);
#else
ret = i2c_write(chip, addr++, alen, &byte, 1);
#endif
@ -649,7 +649,7 @@ static int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]
*/
static int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
uchar chip;
uint chip;
ulong addr;
int alen;
int count;
@ -698,7 +698,7 @@ static int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]
err = 0;
while (count-- > 0) {
#ifdef CONFIG_DM_I2C
ret = i2c_read(dev, addr, &byte, 1);
ret = dm_i2c_read(dev, addr, &byte, 1);
#else
ret = i2c_read(chip, addr, alen, &byte, 1);
#endif
@ -734,7 +734,7 @@ static int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]
static int
mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const argv[])
{
uchar chip;
uint chip;
ulong addr;
int alen;
ulong data;
@ -793,7 +793,7 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const arg
do {
printf("%08lx:", addr);
#ifdef CONFIG_DM_I2C
ret = i2c_read(dev, addr, (uchar *)&data, size);
ret = dm_i2c_read(dev, addr, (uchar *)&data, size);
#else
ret = i2c_read(chip, addr, alen, (uchar *)&data, size);
#endif
@ -841,8 +841,8 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const arg
*/
bootretry_reset_cmd_timeout();
#ifdef CONFIG_DM_I2C
ret = i2c_write(dev, addr, (uchar *)&data,
size);
ret = dm_i2c_write(dev, addr, (uchar *)&data,
size);
#else
ret = i2c_write(chip, addr, alen,
(uchar *)&data, size);
@ -917,7 +917,7 @@ static int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv
continue;
#endif
#ifdef CONFIG_DM_I2C
ret = i2c_probe(bus, j, 0, &dev);
ret = dm_i2c_probe(bus, j, 0, &dev);
#else
ret = i2c_probe(j);
#endif
@ -957,7 +957,7 @@ static int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv
*/
static int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
u_char chip;
uint chip;
int alen;
uint addr;
uint length;
@ -1010,7 +1010,7 @@ static int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]
*/
while (1) {
#ifdef CONFIG_DM_I2C
ret = i2c_read(dev, addr, bytes, length);
ret = dm_i2c_read(dev, addr, bytes, length);
#else
ret = i2c_read(chip, addr, alen, bytes, length);
#endif
@ -1085,7 +1085,7 @@ static int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
enum { unknown, EDO, SDRAM, DDR2 } type;
u_char chip;
uint chip;
u_char data[128];
u_char cksum;
int j;
@ -1563,7 +1563,7 @@ static int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
#if defined(CONFIG_I2C_EDID)
int do_edid(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
u_char chip;
uint chip;
struct edid1_info edid;
int ret;
#ifdef CONFIG_DM_I2C
@ -1579,7 +1579,7 @@ int do_edid(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
#ifdef CONFIG_DM_I2C
ret = i2c_get_cur_bus_chip(chip, &dev);
if (!ret)
ret = i2c_read(dev, 0, (uchar *)&edid, sizeof(edid));
ret = dm_i2c_read(dev, 0, (uchar *)&edid, sizeof(edid));
#else
ret = i2c_read(chip, 0, 1, (uchar *)&edid, sizeof(edid));
#endif
@ -1696,7 +1696,11 @@ static int do_i2c_bus_num(cmd_tbl_t *cmdtp, int flag, int argc,
}
#endif
printf("Setting bus to %d\n", bus_no);
#ifdef CONFIG_DM_I2C
ret = cmd_i2c_set_bus_num(bus_no);
#else
ret = i2c_set_bus_num(bus_no);
#endif
if (ret)
printf("Failure changing bus number (%d)\n", ret);
}

2
common/cmd_load.c
View File

@ -222,7 +222,7 @@ static int read_record(char *buf, ulong len)
}
/* Check for the console hangup (if any different from serial) */
if (gd->jt[XF_getc] != getc) {
if (gd->jt->getc != getc) {
if (ctrlc()) {
return (-1);
}

20
common/console.c
View File

@ -125,13 +125,13 @@ static int console_setfile(int file, struct stdio_dev * dev)
*/
switch (file) {
case stdin:
gd->jt[XF_getc] = getc;
gd->jt[XF_tstc] = tstc;
gd->jt->getc = getc;
gd->jt->tstc = tstc;
break;
case stdout:
gd->jt[XF_putc] = putc;
gd->jt[XF_puts] = puts;
gd->jt[XF_printf] = printf;
gd->jt->putc = putc;
gd->jt->puts = puts;
gd->jt->printf = printf;
break;
}
break;
@ -758,11 +758,11 @@ int console_init_r(void)
#endif
/* set default handlers at first */
gd->jt[XF_getc] = serial_getc;
gd->jt[XF_tstc] = serial_tstc;
gd->jt[XF_putc] = serial_putc;
gd->jt[XF_puts] = serial_puts;
gd->jt[XF_printf] = serial_printf;
gd->jt->getc = serial_getc;
gd->jt->tstc = serial_tstc;
gd->jt->putc = serial_putc;
gd->jt->puts = serial_puts;
gd->jt->printf = serial_printf;
/* stdin stdout and stderr are in environment */
/* scan for it */

28
common/exports.c
View File

@ -1,6 +1,7 @@
#include <common.h>
#include <exports.h>
#include <spi.h>
#include <i2c.h>
DECLARE_GLOBAL_DATA_PTR;
@ -13,33 +14,10 @@ unsigned long get_version(void)
return XF_VERSION;
}
/* Reuse _exports.h with a little trickery to avoid bitrot */
#define EXPORT_FUNC(sym) gd->jt[XF_##sym] = (void *)sym;
#if !defined(CONFIG_X86) && !defined(CONFIG_PPC)
# define install_hdlr dummy
# define free_hdlr dummy
#else /* kludge for non-standard function naming */
# define install_hdlr irq_install_handler
# define free_hdlr irq_free_handler
#endif
#ifndef CONFIG_CMD_I2C
# define i2c_write dummy
# define i2c_read dummy
#endif
#if !defined(CONFIG_CMD_SPI) || defined(CONFIG_DM_SPI)
# define spi_init dummy
# define spi_setup_slave dummy
# define spi_free_slave dummy
#endif
#ifndef CONFIG_CMD_SPI
# define spi_claim_bus dummy
# define spi_release_bus dummy
# define spi_xfer dummy
#endif
#define EXPORT_FUNC(f, a, x, ...) gd->jt->x = f;
void jumptable_init(void)
{
gd->jt = malloc(XF_MAX * sizeof(void *));
gd->jt = malloc(sizeof(struct jt_funcs));
#include <_exports.h>
}

80
common/hash.c
View File

@ -10,17 +10,26 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef USE_HOSTCC
#include <common.h>
#include <command.h>
#include <malloc.h>
#include <hw_sha.h>
#include <hash.h>
#include <u-boot/sha1.h>
#include <u-boot/sha256.h>
#include <asm/io.h>
#include <asm/errno.h>
#else
#include "mkimage.h"
#include <time.h>
#include <image.h>
#endif /* !USE_HOSTCC*/
#ifdef CONFIG_CMD_SHA1SUM
#include <hash.h>
#include <u-boot/crc.h>
#include <u-boot/sha1.h>
#include <u-boot/sha256.h>
#include <u-boot/md5.h>
#ifdef CONFIG_SHA1
static int hash_init_sha1(struct hash_algo *algo, void **ctxp)
{
sha1_context *ctx = malloc(sizeof(sha1_context));
@ -125,12 +134,7 @@ static struct hash_algo hash_algo[] = {
CHUNKSZ_SHA256,
},
#endif
/*
* This is CONFIG_CMD_SHA1SUM instead of CONFIG_SHA1 since otherwise
* it bloats the code for boards which use SHA1 but not the 'hash'
* or 'sha1sum' commands.
*/
#ifdef CONFIG_CMD_SHA1SUM
#ifdef CONFIG_SHA1
{
"sha1",
SHA1_SUM_LEN,
@ -140,7 +144,6 @@ static struct hash_algo hash_algo[] = {
hash_update_sha1,
hash_finish_sha1,
},
#define MULTI_HASH
#endif
#ifdef CONFIG_SHA256
{
@ -152,7 +155,6 @@ static struct hash_algo hash_algo[] = {
hash_update_sha256,
hash_finish_sha256,
},
#define MULTI_HASH
#endif
{
"crc32",
@ -165,6 +167,10 @@ static struct hash_algo hash_algo[] = {
},
};
#if defined(CONFIG_SHA256) || defined(CONFIG_CMD_SHA1SUM)
#define MULTI_HASH
#endif
#if defined(CONFIG_HASH_VERIFY) || defined(CONFIG_CMD_HASH)
#define MULTI_HASH
#endif
@ -176,6 +182,40 @@ static struct hash_algo hash_algo[] = {
#define multi_hash() 0
#endif
int hash_lookup_algo(const char *algo_name, struct hash_algo **algop)
{
int i;
for (i = 0; i < ARRAY_SIZE(hash_algo); i++) {
if (!strcmp(algo_name, hash_algo[i].name)) {
*algop = &hash_algo[i];
return 0;
}
}
debug("Unknown hash algorithm '%s'\n", algo_name);
return -EPROTONOSUPPORT;
}
int hash_progressive_lookup_algo(const char *algo_name,
struct hash_algo **algop)
{
int i;
for (i = 0; i < ARRAY_SIZE(hash_algo); i++) {
if (!strcmp(algo_name, hash_algo[i].name)) {
if (hash_algo[i].hash_init) {
*algop = &hash_algo[i];
return 0;
}
}
}
debug("Unknown hash algorithm '%s'\n", algo_name);
return -EPROTONOSUPPORT;
}
#ifndef USE_HOSTCC
/**
* store_result: Store the resulting sum to an address or variable
*
@ -296,21 +336,6 @@ static int parse_verify_sum(struct hash_algo *algo, char *verify_str,
return 0;
}
int hash_lookup_algo(const char *algo_name, struct hash_algo **algop)
{
int i;
for (i = 0; i < ARRAY_SIZE(hash_algo); i++) {
if (!strcmp(algo_name, hash_algo[i].name)) {
*algop = &hash_algo[i];
return 0;
}
}
debug("Unknown hash algorithm '%s'\n", algo_name);
return -EPROTONOSUPPORT;
}
void hash_show(struct hash_algo *algo, ulong addr, ulong len, uint8_t *output)
{
int i;
@ -424,3 +449,4 @@ int hash_command(const char *algo_name, int flags, cmd_tbl_t *cmdtp, int flag,
return 0;
}
#endif

6
common/image-sig.c
View File

@ -38,7 +38,7 @@ struct checksum_algo checksum_algos[] = {
#if IMAGE_ENABLE_SIGN
EVP_sha1,
#endif
sha1_calculate,
hash_calculate,
padding_sha1_rsa2048,
},
{
@ -48,7 +48,7 @@ struct checksum_algo checksum_algos[] = {
#if IMAGE_ENABLE_SIGN
EVP_sha256,
#endif
sha256_calculate,
hash_calculate,
padding_sha256_rsa2048,
},
{
@ -58,7 +58,7 @@ struct checksum_algo checksum_algos[] = {
#if IMAGE_ENABLE_SIGN
EVP_sha256,
#endif
sha256_calculate,
hash_calculate,
padding_sha256_rsa4096,
}

4
configs/am335x_boneblack_vboot_defconfig
View File

@ -4,3 +4,7 @@ CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT,ENABLE_VBOOT"
+S:CONFIG_TARGET_AM335X_EVM=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-boneblack"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_DM=y

3
configs/ids8313_defconfig
View File

@ -1,4 +1,7 @@
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFFF00000"
CONFIG_PPC=y
CONFIG_MPC83xx=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_TARGET_IDS8313=y
CONFIG_DM=y

2
configs/ph1_ld4_defconfig
View File

@ -18,6 +18,7 @@ CONFIG_CMD_LOADB=y
CONFIG_CMD_LOADS=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_ECHO=y
CONFIG_CMD_ITEST=y
@ -34,6 +35,7 @@ CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_DM_SERIAL=y
CONFIG_UNIPHIER_SERIAL=y
CONFIG_DM_I2C=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

2
configs/ph1_pro4_defconfig
View File

@ -18,6 +18,7 @@ CONFIG_CMD_LOADB=y
CONFIG_CMD_LOADS=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_ECHO=y
CONFIG_CMD_ITEST=y
@ -34,6 +35,7 @@ CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_DM_SERIAL=y
CONFIG_UNIPHIER_SERIAL=y
CONFIG_DM_I2C=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

2
configs/ph1_sld8_defconfig
View File

@ -18,6 +18,7 @@ CONFIG_CMD_LOADB=y
CONFIG_CMD_LOADS=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_NAND=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_ECHO=y
CONFIG_CMD_ITEST=y
@ -34,6 +35,7 @@ CONFIG_SYS_NAND_DENALI_64BIT=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_DM_SERIAL=y
CONFIG_UNIPHIER_SERIAL=y
CONFIG_DM_I2C=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

4
configs/sandbox_defconfig
View File

@ -1,3 +1,7 @@
CONFIG_OF_CONTROL=y
CONFIG_OF_HOSTFILE=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_DM=y
CONFIG_DEFAULT_DEVICE_TREE="sandbox"

4
configs/zynq_microzed_defconfig
View File

@ -3,4 +3,8 @@ CONFIG_SPL=y
+S:CONFIG_ZYNQ=y
+S:CONFIG_TARGET_ZYNQ_MICROZED=y
CONFIG_OF_CONTROL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_DM=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-microzed"

4
configs/zynq_zc70x_defconfig
View File

@ -4,3 +4,7 @@ CONFIG_SPL=y
+S:CONFIG_TARGET_ZYNQ_ZC70X=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_DM=y

4
configs/zynq_zc770_xm010_defconfig
View File

@ -5,3 +5,7 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010"
+S:CONFIG_TARGET_ZYNQ_ZC770=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_DM=y

4
configs/zynq_zc770_xm012_defconfig
View File

@ -5,3 +5,7 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012"
+S:CONFIG_TARGET_ZYNQ_ZC770=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm012"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_DM=y

4
configs/zynq_zc770_xm013_defconfig
View File

@ -5,3 +5,7 @@ CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013"
+S:CONFIG_TARGET_ZYNQ_ZC770=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm013"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_DM=y

4
configs/zynq_zed_defconfig
View File

@ -4,3 +4,7 @@ CONFIG_SPL=y
+S:CONFIG_TARGET_ZYNQ_ZED=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zed"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_DM=y

4
configs/zynq_zybo_defconfig
View File

@ -4,3 +4,7 @@ CONFIG_SPL=y
+S:CONFIG_TARGET_ZYNQ_ZYBO=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zybo"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_DM=y

41
doc/README.standalone
View File

@ -5,18 +5,18 @@ Design Notes on Exporting U-Boot Functions to Standalone Applications:
table is allocated and initialized in the jumptable_init() routine
(common/exports.c). Other routines may also modify the jump table,
however. The jump table can be accessed as the 'jt' field of the
'global_data' structure. The slot numbers for the jump table are
'global_data' structure. The struct members for the jump table are
defined in the <include/exports.h> header. E.g., to substitute the
malloc() and free() functions that will be available to standalone
applications, one should do the following:
DECLARE_GLOBAL_DATA_PTR;
gd->jt[XF_malloc] = my_malloc;
gd->jt[XF_free] = my_free;
gd->jt->malloc = my_malloc;
gd->jt->free = my_free;
Note that the pointers to the functions all have 'void *' type and
thus the compiler cannot perform type checks on these assignments.
Note that the pointers to the functions are real function pointers
so the compiler can perform type checks on these assignments.
2. The pointer to the jump table is passed to the application in a
machine-dependent way. PowerPC, ARM, MIPS, Blackfin and Nios II
@ -65,27 +65,46 @@ Design Notes on Exporting U-Boot Functions to Standalone Applications:
=> tftp 0x40000 hello_world.bin
=> go 0x40004
5. To export some additional function foobar(), the following steps
5. To export some additional function long foobar(int i,char c), the following steps
should be undertaken:
- Append the following line at the end of the include/_exports.h
file:
EXPORT_FUNC(foobar)
EXPORT_FUNC(foobar, long, foobar, int, char)
Parameters to EXPORT_FUNC:
- the first parameter is the function that is exported (default implementation)
- the second parameter is the return value type
- the third parameter is the name of the member in struct jt_funcs
this is also the name that the standalone application will used.
the rest of the parameters are the function arguments
- Add the prototype for this function to the include/exports.h
file:
void foobar(void);
long foobar(int i, char c);
- Add the initialization of the jump table slot wherever
appropriate (most likely, to the jumptable_init() function):
Initialization with the default implementation is done in jumptable_init()
gd->jt[XF_foobar] = foobar;
You can override the default implementation using:
gd->jt->foobar = another_foobar;
The signature of another_foobar must then match the declaration of foobar.
- Increase the XF_VERSION value by one in the include/exports.h
file
- If you want to export a function which depends on a CONFIG_XXX
use 2 lines like this:
#ifdef CONFIG_FOOBAR
EXPORT_FUNC(foobar, long, foobar, int, char)
#else
EXPORT_FUNC(dummy, void, foobar, void)
#endif
6. The code for exporting the U-Boot functions to applications is
mostly machine-independent. The only places written in assembly
language are stub functions that perform the jump through the jump

41
doc/device-tree-bindings/gpio/gpio-samsung.txt 100644
View File

@ -0,0 +1,41 @@
Samsung Exynos4 GPIO Controller
Required properties:
- compatible: Compatible property value should be "samsung,exynos4-gpio>".
- reg: Physical base address of the controller and length of memory mapped
region.
- #gpio-cells: Should be 4. The syntax of the gpio specifier used by client nodes
should be the following with values derived from the SoC user manual.
<[phandle of the gpio controller node]
[pin number within the gpio controller]
[mux function]
[flags and pull up/down]
[drive strength]>
Values for gpio specifier:
- Pin number: is a value between 0 to 7.
- Flags and Pull Up/Down: 0 - Pull Up/Down Disabled.
1 - Pull Down Enabled.
3 - Pull Up Enabled.
Bit 16 (0x00010000) - Input is active low.
- Drive Strength: 0 - 1x,
1 - 3x,
2 - 2x,
3 - 4x
- gpio-controller: Specifies that the node is a gpio controller.
- #address-cells: should be 1.
- #size-cells: should be 1.
Example:
gpa0: gpio-controller@11400000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "samsung,exynos4-gpio";
reg = <0x11400000 0x20>;
#gpio-cells = <4>;
gpio-controller;
};

211
doc/device-tree-bindings/gpio/gpio.txt 100644
View File

@ -0,0 +1,211 @@
Specifying GPIO information for devices
============================================
1) gpios property
-----------------
Nodes that makes use of GPIOs should specify them using one or more
properties, each containing a 'gpio-list':
gpio-list ::= <single-gpio> [gpio-list]
single-gpio ::= <gpio-phandle> <gpio-specifier>
gpio-phandle : phandle to gpio controller node
gpio-specifier : Array of #gpio-cells specifying specific gpio
(controller specific)
GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
of this GPIO for the device. While a non-existent <name> is considered valid
for compatibility reasons (resolving to the "gpios" property), it is not allowed
for new bindings.
GPIO properties can contain one or more GPIO phandles, but only in exceptional
cases should they contain more than one. If your device uses several GPIOs with
distinct functions, reference each of them under its own property, giving it a
meaningful name. The only case where an array of GPIOs is accepted is when
several GPIOs serve the same function (e.g. a parallel data line).
The exact purpose of each gpios property must be documented in the device tree
binding of the device.
The following example could be used to describe GPIO pins used as device enable
and bit-banged data signals:
gpio1: gpio1 {
gpio-controller
#gpio-cells = <2>;
};
gpio2: gpio2 {
gpio-controller
#gpio-cells = <1>;
};
[...]
enable-gpios = <&gpio2 2>;
data-gpios = <&gpio1 12 0>,
<&gpio1 13 0>,
<&gpio1 14 0>,
<&gpio1 15 0>;
Note that gpio-specifier length is controller dependent. In the
above example, &gpio1 uses 2 cells to specify a gpio, while &gpio2
only uses one.
gpio-specifier may encode: bank, pin position inside the bank,
whether pin is open-drain and whether pin is logically inverted.
Exact meaning of each specifier cell is controller specific, and must
be documented in the device tree binding for the device. Use the macros
defined in include/dt-bindings/gpio/gpio.h whenever possible:
Example of a node using GPIOs:
node {
enable-gpios = <&qe_pio_e 18 GPIO_ACTIVE_HIGH>;
};
GPIO_ACTIVE_HIGH is 0, so in this example gpio-specifier is "18 0" and encodes
GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller.
1.1) GPIO specifier best practices
----------------------------------
A gpio-specifier should contain a flag indicating the GPIO polarity; active-
high or active-low. If it does, the follow best practices should be followed:
The gpio-specifier's polarity flag should represent the physical level at the
GPIO controller that achieves (or represents, for inputs) a logically asserted
value at the device. The exact definition of logically asserted should be
defined by the binding for the device. If the board inverts the signal between
the GPIO controller and the device, then the gpio-specifier will represent the
opposite physical level than the signal at the device's pin.
When the device's signal polarity is configurable, the binding for the
device must either:
a) Define a single static polarity for the signal, with the expectation that
any software using that binding would statically program the device to use
that signal polarity.
The static choice of polarity may be either:
a1) (Preferred) Dictated by a binding-specific DT property.
or:
a2) Defined statically by the DT binding itself.
In particular, the polarity cannot be derived from the gpio-specifier, since
that would prevent the DT from separately representing the two orthogonal
concepts of configurable signal polarity in the device, and possible board-
level signal inversion.
or:
b) Pick a single option for device signal polarity, and document this choice
in the binding. The gpio-specifier should represent the polarity of the signal
(at the GPIO controller) assuming that the device is configured for this
particular signal polarity choice. If software chooses to program the device
to generate or receive a signal of the opposite polarity, software will be
responsible for correctly interpreting (inverting) the GPIO signal at the GPIO
controller.
2) gpio-controller nodes
------------------------
Every GPIO controller node must contain both an empty "gpio-controller"
property, and a #gpio-cells integer property, which indicates the number of
cells in a gpio-specifier.
Example of two SOC GPIO banks defined as gpio-controller nodes:
qe_pio_a: gpio-controller@1400 {
compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank";
reg = <0x1400 0x18>;
gpio-controller;
#gpio-cells = <2>;
};
qe_pio_e: gpio-controller@1460 {
compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
reg = <0x1460 0x18>;
gpio-controller;
#gpio-cells = <2>;
};
2.1) gpio- and pin-controller interaction
-----------------------------------------
Some or all of the GPIOs provided by a GPIO controller may be routed to pins
on the package via a pin controller. This allows muxing those pins between
GPIO and other functions.
It is useful to represent which GPIOs correspond to which pins on which pin
controllers. The gpio-ranges property described below represents this, and
contains information structures as follows:
gpio-range-list ::= <single-gpio-range> [gpio-range-list]
single-gpio-range ::= <numeric-gpio-range> | <named-gpio-range>
numeric-gpio-range ::=
<pinctrl-phandle> <gpio-base> <pinctrl-base> <count>
named-gpio-range ::= <pinctrl-phandle> <gpio-base> '<0 0>'
gpio-phandle : phandle to pin controller node.
gpio-base : Base GPIO ID in the GPIO controller
pinctrl-base : Base pinctrl pin ID in the pin controller
count : The number of GPIOs/pins in this range
The "pin controller node" mentioned above must conform to the bindings
described in ../pinctrl/pinctrl-bindings.txt.
In case named gpio ranges are used (ranges with both <pinctrl-base> and
<count> set to 0), the property gpio-ranges-group-names contains one string
for every single-gpio-range in gpio-ranges:
gpiorange-names-list ::= <gpiorange-name> [gpiorange-names-list]
gpiorange-name : Name of the pingroup associated to the GPIO range in
the respective pin controller.
Elements of gpiorange-names-list corresponding to numeric ranges contain
the empty string. Elements of gpiorange-names-list corresponding to named
ranges contain the name of a pin group defined in the respective pin
controller. The number of pins/GPIOs in the range is the number of pins in
that pin group.
Previous versions of this binding required all pin controller nodes that
were referenced by any gpio-ranges property to contain a property named
#gpio-range-cells with value <3>. This requirement is now deprecated.
However, that property may still exist in older device trees for
compatibility reasons, and would still be required even in new device
trees that need to be compatible with older software.
Example 1:
qe_pio_e: gpio-controller@1460 {
#gpio-cells = <2>;
compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
reg = <0x1460 0x18>;
gpio-controller;
gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>;
};
Here, a single GPIO controller has GPIOs 0..9 routed to pin controller
pinctrl1's pins 20..29, and GPIOs 10..19 routed to pin controller pinctrl2's
pins 50..59.
Example 2:
gpio_pio_i: gpio-controller@14B0 {
#gpio-cells = <2>;
compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
reg = <0x1480 0x18>;
gpio-controller;
gpio-ranges = <&pinctrl1 0 20 10>,
<&pinctrl2 10 0 0>,
<&pinctrl1 15 0 10>,
<&pinctrl2 25 0 0>;
gpio-ranges-group-names = "",
"foo",
"",
"bar";
};
Here, three GPIO ranges are defined wrt. two pin controllers. pinctrl1 GPIO
ranges are defined using pin numbers whereas the GPIO ranges wrt. pinctrl2
are named "foo" and "bar".

40
doc/device-tree-bindings/gpio/nvidia,tegra20-gpio.txt 100644
View File

@ -0,0 +1,40 @@
NVIDIA Tegra GPIO controller
Required properties:
- compatible : "nvidia,tegra<chip>-gpio"
- reg : Physical base address and length of the controller's registers.
- interrupts : The interrupt outputs from the controller. For Tegra20,
there should be 7 interrupts specified, and for Tegra30, there should
be 8 interrupts specified.
- #gpio-cells : Should be two. The first cell is the pin number and the
second cell is used to specify optional parameters:
- bit 0 specifies polarity (0 for normal, 1 for inverted)
- gpio-controller : Marks the device node as a GPIO controller.
- #interrupt-cells : Should be 2.
The first cell is the GPIO number.
The second cell is used to specify flags:
bits[3:0] trigger type and level flags:
1 = low-to-high edge triggered.
2 = high-to-low edge triggered.
4 = active high level-sensitive.
8 = active low level-sensitive.
Valid combinations are 1, 2, 3, 4, 8.
- interrupt-controller : Marks the device node as an interrupt controller.
Example:
gpio: gpio@6000d000 {
compatible = "nvidia,tegra20-gpio";
reg = < 0x6000d000 0x1000 >;
interrupts = < 0 32 0x04
0 33 0x04
0 34 0x04
0 35 0x04
0 55 0x04
0 87 0x04
0 89 0x04 >;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
};

28
doc/device-tree-bindings/i2c/i2c.txt 100644
View File

@ -0,0 +1,28 @@
U-Boot I2C
----------
U-Boot's I2C model has the concept of an offset within a chip (I2C target
device). The offset can be up to 4 bytes long, but is normally 1 byte,
meaning that offsets from 0 to 255 are supported by the chip. This often
corresponds to register numbers.
Apart from the controller-specific I2C bindings, U-Boot supports a special
property which allows the chip offset length to be selected.
Optional properties:
- u-boot,i2c-offset-len - length of chip offset in bytes. If omitted the
default value of 1 is used.
Example
-------
i2c4: i2c@12ca0000 {
cros-ec@1e {
reg = <0x1e>;
compatible = "google,cros-ec";
i2c-max-frequency = <100000>;
u-boot,i2c-offset-len = <0>;
ec-interrupt = <&gpx1 6 GPIO_ACTIVE_LOW>;
};
};

91
doc/driver-model/README.txt
View File

@ -363,6 +363,10 @@ can leave out platdata_auto_alloc_size. In this case you can use malloc
in your ofdata_to_platdata (or probe) method to allocate the required memory,
and you should free it in the remove method.
The driver model tree is intended to mirror that of the device tree. The
root driver is at device tree offset 0 (the root node, '/'), and its
children are the children of the root node.
Declaring Uclasses
------------------
@ -384,12 +388,12 @@ Device Sequence Numbers
U-Boot numbers devices from 0 in many situations, such as in the command
line for I2C and SPI buses, and the device names for serial ports (serial0,
serial1, ...). Driver model supports this numbering and permits devices
to be locating by their 'sequence'. This numbering unique identifies a
to be locating by their 'sequence'. This numbering uniquely identifies a
device in its uclass, so no two devices within a particular uclass can have
the same sequence number.
Sequence numbers start from 0 but gaps are permitted. For example, a board
may have I2C buses 0, 1, 4, 5 but no 2 or 3. The choice of how devices are
may have I2C buses 1, 4, 5 but no 0, 2 or 3. The choice of how devices are
numbered is up to a particular board, and may be set by the SoC in some
cases. While it might be tempting to automatically renumber the devices
where there are gaps in the sequence, this can lead to confusion and is
@ -399,7 +403,7 @@ Each device can request a sequence number. If none is required then the
device will be automatically allocated the next available sequence number.
To specify the sequence number in the device tree an alias is typically
used.
used. Make sure that the uclass has the DM_UC_FLAG_SEQ_ALIAS flag set.
aliases {
serial2 = "/serial@22230000";
@ -409,43 +413,18 @@ This indicates that in the uclass called "serial", the named node
("/serial@22230000") will be given sequence number 2. Any command or driver
which requests serial device 2 will obtain this device.
Some devices represent buses where the devices on the bus are numbered or
addressed. For example, SPI typically numbers its slaves from 0, and I2C
uses a 7-bit address. In these cases the 'reg' property of the subnode is
used, for example:
More commonly you can use node references, which expand to the full path:
{
aliases {
spi2 = "/spi@22300000";
};
aliases {
serial2 = &serial_2;
};
...
serial_2: serial@22230000 {
...
};
spi@22300000 {
#address-cells = <1>;
#size-cells = <1>;
spi-flash@0 {
reg = <0>;
...
}
eeprom@1 {
reg = <1>;
};
};
In this case we have a SPI bus with two slaves at 0 and 1. The SPI bus
itself is numbered 2. So we might access the SPI flash with:
sf probe 2:0
and the eeprom with
sspi 2:1 32 ef
These commands simply need to look up the 2nd device in the SPI uclass to
find the right SPI bus. Then, they look at the children of that bus for the
right sequence number (0 or 1 in this case).
Typically the alias method is used for top-level nodes and the 'reg' method
is used only for buses.
The alias resolves to the same string in this case, but this version is
easier to read.
Device sequence numbers are resolved when a device is probed. Before then
the sequence number is only a request which may or may not be honoured,
@ -462,11 +441,18 @@ access to other devices. Example of buses include SPI and I2C. Typically
the bus provides some sort of transport or translation that makes it
possible to talk to the devices on the bus.
Driver model provides a few useful features to help with implementing
buses. Firstly, a bus can request that its children store some 'parent
data' which can be used to keep track of child state. Secondly, the bus can
define methods which are called when a child is probed or removed. This is
similar to the methods the uclass driver provides.
Driver model provides some useful features to help with implementing buses.
Firstly, a bus can request that its children store some 'parent data' which
can be used to keep track of child state. Secondly, the bus can define
methods which are called when a child is probed or removed. This is similar
to the methods the uclass driver provides. Thirdly, per-child platform data
can be provided to specify things like the child's address on the bus. This
persists across child probe()/remove() cycles.
For consistency and ease of implementation, the bus uclass can specify the
per-child platform data, so that it can be the same for all children of buses
in that uclass. There are also uclass methods which can be called when
children are bound and probed.
Here an explanation of how a bus fits with a uclass may be useful. Consider
a USB bus with several devices attached to it, each from a different (made
@ -481,15 +467,23 @@ Each of the devices is connected to a different address on the USB bus.
The bus device wants to store this address and some other information such
as the bus speed for each device.
To achieve this, the bus device can use dev->parent_priv in each of its
three children. This can be auto-allocated if the bus driver has a non-zero
value for per_child_auto_alloc_size. If not, then the bus device can
allocate the space itself before the child device is probed.
To achieve this, the bus device can use dev->parent_platdata in each of its
three children. This can be auto-allocated if the bus driver (or bus uclass)
has a non-zero value for per_child_platdata_auto_alloc_size. If not, then
the bus device or uclass can allocate the space itself before the child
device is probed.
Also the bus driver can define the child_pre_probe() and child_post_remove()
methods to allow it to do some processing before the child is activated or
after it is deactivated.
Similarly the bus uclass can define the child_post_bind() method to obtain
the per-child platform data from the device tree and set it up for the child.
The bus uclass can also provide a child_pre_probe() method. Very often it is
the bus uclass that controls these features, since it avoids each driver
having to do the same processing. Of course the driver can still tweak and
override these activities.
Note that the information that controls this behaviour is in the bus's
driver, not the child's. In fact it is possible that child has no knowledge
that it is connected to a bus. The same child device may even be used on two
@ -516,7 +510,8 @@ bus device, regardless of its own views on the matter.
The uclass for the device can also contain data private to that uclass.
But note that each device on the bus may be a memeber of a different
uclass, and this data has nothing to do with the child data for each child
on the bus.
on the bus. It is the bus' uclass that controls the child with respect to
the bus.
Driver Lifecycle

40
doc/driver-model/spi-howto.txt
View File

@ -3,7 +3,8 @@ How to port a SPI driver to driver model
Here is a rough step-by-step guide. It is based around converting the
exynos SPI driver to driver model (DM) and the example code is based
around U-Boot v2014.10-rc2 (commit be9f643).
around U-Boot v2014.10-rc2 (commit be9f643). This has been updated for
v2015.04.
It is quite long since it includes actual code examples.
@ -262,8 +263,8 @@ U_BOOT_DEVICE(board_spi0) = {
.platdata = &platdata_spi0,
};
You will unfortunately need to put the struct into a header file in this
case so that your board file can use it.
You will unfortunately need to put the struct definition into a header file
in this case so that your board file can use it.
9. Add the device private data
@ -592,3 +593,36 @@ board.
You can use 'tools/patman/patman' to prepare, check and send patches for
your work. See the README for details.
20. A little note about SPI uclass features:
The SPI uclass keeps some information about each device 'dev' on the bus:
struct dm_spi_slave_platdata - this is device_get_parent_platdata(dev)
This is where the chip select number is stored, along with
the default bus speed and mode. It is automatically read
from the device tree in spi_child_post_bind(). It must not
be changed at run-time after being set up because platform
data is supposed to be immutable at run-time.
struct spi_slave - this is device_get_parentdata(dev)
Already mentioned above. It holds run-time information about
the device.
There are also some SPI uclass methods that get called behind the scenes:
spi_post_bind() - called when a new bus is bound
This scans the device tree for devices on the bus, and binds
each one. This in turn causes spi_child_post_bind() to be
called for each, which reads the device tree information
into the parent (per-child) platform data.
spi_child_post_bind() - called when a new child is bound
As mentioned above this reads the device tree information
into the per-child platform data
spi_child_pre_probe() - called before a new child is probed
This sets up the mode and speed in struct spi_slave by
copying it from the parent's platform data for this child.
It also sets the 'dev' pointer, needed to permit passing
'struct spi_slave' around the place without needing a
separate 'struct udevice' pointer.
The above housekeeping makes it easier to write your SPI driver.

16
drivers/core/device-remove.c
View File

@ -88,6 +88,14 @@ int device_unbind(struct udevice *dev)
if (ret)
return ret;
if (dev->flags & DM_FLAG_ALLOC_PDATA) {
free(dev->platdata);
dev->platdata = NULL;
}
if (dev->flags & DM_FLAG_ALLOC_PARENT_PDATA) {
free(dev->parent_platdata);
dev->parent_platdata = NULL;
}
ret = uclass_unbind_device(dev);
if (ret)
return ret;
@ -111,10 +119,6 @@ void device_free(struct udevice *dev)
free(dev->priv);
dev->priv = NULL;
}
if (dev->flags & DM_FLAG_ALLOC_PDATA) {
free(dev->platdata);
dev->platdata = NULL;
}
size = dev->uclass->uc_drv->per_device_auto_alloc_size;
if (size) {
free(dev->uclass_priv);
@ -122,6 +126,10 @@ void device_free(struct udevice *dev)
}
if (dev->parent) {
size = dev->parent->driver->per_child_auto_alloc_size;
if (!size) {
size = dev->parent->uclass->uc_drv->
per_child_auto_alloc_size;
}
if (size) {
free(dev->parent_priv);
dev->parent_priv = NULL;

123
drivers/core/device.c
View File

@ -53,27 +53,47 @@ int device_bind(struct udevice *parent, struct driver *drv, const char *name,
dev->driver = drv;
dev->uclass = uc;
/*
* For some devices, such as a SPI or I2C bus, the 'reg' property
* is a reasonable indicator of the sequence number. But if there is
* an alias, we use that in preference. In any case, this is just
* a 'requested' sequence, and will be resolved (and ->seq updated)
* when the device is probed.
*/
dev->seq = -1;
#ifdef CONFIG_OF_CONTROL
dev->req_seq = fdtdec_get_int(gd->fdt_blob, of_offset, "reg", -1);
if (!IS_ERR_VALUE(dev->req_seq))
dev->req_seq &= INT_MAX;
if (uc->uc_drv->name && of_offset != -1) {
fdtdec_get_alias_seq(gd->fdt_blob, uc->uc_drv->name, of_offset,
&dev->req_seq);
}
#else
dev->req_seq = -1;
#ifdef CONFIG_OF_CONTROL
/*
* Some devices, such as a SPI bus, I2C bus and serial ports are
* numbered using aliases.
*
* This is just a 'requested' sequence, and will be
* resolved (and ->seq updated) when the device is probed.
*/
if (uc->uc_drv->flags & DM_UC_FLAG_SEQ_ALIAS) {
if (uc->uc_drv->name && of_offset != -1) {
fdtdec_get_alias_seq(gd->fdt_blob, uc->uc_drv->name,
of_offset, &dev->req_seq);
}
}
#endif
if (!dev->platdata && drv->platdata_auto_alloc_size)
if (!dev->platdata && drv->platdata_auto_alloc_size) {
dev->flags |= DM_FLAG_ALLOC_PDATA;
dev->platdata = calloc(1, drv->platdata_auto_alloc_size);
if (!dev->platdata) {
ret = -ENOMEM;
goto fail_alloc1;
}
}
if (parent) {
int size = parent->driver->per_child_platdata_auto_alloc_size;
if (!size) {
size = parent->uclass->uc_drv->
per_child_platdata_auto_alloc_size;
}
if (size) {
dev->flags |= DM_FLAG_ALLOC_PARENT_PDATA;
dev->parent_platdata = calloc(1, size);
if (!dev->parent_platdata) {
ret = -ENOMEM;
goto fail_alloc2;
}
}
}
/* put dev into parent's successor list */
if (parent)
@ -81,28 +101,51 @@ int device_bind(struct udevice *parent, struct driver *drv, const char *name,
ret = uclass_bind_device(dev);
if (ret)
goto fail_bind;
goto fail_uclass_bind;
/* if we fail to bind we remove device from successors and free it */
if (drv->bind) {
ret = drv->bind(dev);
if (ret) {
if (uclass_unbind_device(dev)) {
dm_warn("Failed to unbind dev '%s' on error path\n",
dev->name);
}
if (ret)
goto fail_bind;
}
}
if (parent && parent->driver->child_post_bind) {
ret = parent->driver->child_post_bind(dev);
if (ret)
goto fail_child_post_bind;
}
if (parent)
dm_dbg("Bound device %s to %s\n", dev->name, parent->name);
*devp = dev;
return 0;
fail_child_post_bind:
if (drv->unbind && drv->unbind(dev)) {
dm_warn("unbind() method failed on dev '%s' on error path\n",
dev->name);
}
fail_bind:
if (uclass_unbind_device(dev)) {
dm_warn("Failed to unbind dev '%s' on error path\n",
dev->name);
}
fail_uclass_bind:
list_del(&dev->sibling_node);
if (dev->flags & DM_FLAG_ALLOC_PARENT_PDATA) {
free(dev->parent_platdata);
dev->parent_platdata = NULL;
}
fail_alloc2:
if (dev->flags & DM_FLAG_ALLOC_PDATA) {
free(dev->platdata);
dev->platdata = NULL;
}
fail_alloc1:
free(dev);
return ret;
}
@ -137,7 +180,7 @@ int device_probe_child(struct udevice *dev, void *parent_priv)
drv = dev->driver;
assert(drv);
/* Allocate private data and platdata if requested */
/* Allocate private data if requested */
if (drv->priv_auto_alloc_size) {
dev->priv = calloc(1, drv->priv_auto_alloc_size);
if (!dev->priv) {
@ -146,13 +189,6 @@ int device_probe_child(struct udevice *dev, void *parent_priv)
}
}
/* Allocate private data if requested */
if (dev->flags & DM_FLAG_ALLOC_PDATA) {
dev->platdata = calloc(1, drv->platdata_auto_alloc_size);
if (!dev->platdata) {
ret = -ENOMEM;
goto fail;
}
}
size = dev->uclass->uc_drv->per_device_auto_alloc_size;
if (size) {
dev->uclass_priv = calloc(1, size);
@ -165,6 +201,10 @@ int device_probe_child(struct udevice *dev, void *parent_priv)
/* Ensure all parents are probed */
if (dev->parent) {
size = dev->parent->driver->per_child_auto_alloc_size;
if (!size) {
size = dev->parent->uclass->uc_drv->
per_child_auto_alloc_size;
}
if (size) {
dev->parent_priv = calloc(1, size);
if (!dev->parent_priv) {
@ -187,6 +227,10 @@ int device_probe_child(struct udevice *dev, void *parent_priv)
}
dev->seq = seq;
ret = uclass_pre_probe_child(dev);
if (ret)
goto fail;
if (dev->parent && dev->parent->driver->child_pre_probe) {
ret = dev->parent->driver->child_pre_probe(dev);
if (ret)
@ -241,6 +285,16 @@ void *dev_get_platdata(struct udevice *dev)
return dev->platdata;
}
void *dev_get_parent_platdata(struct udevice *dev)
{
if (!dev) {
dm_warn("%s: null device", __func__);
return NULL;
}
return dev->parent_platdata;
}
void *dev_get_priv(struct udevice *dev)
{
if (!dev) {
@ -390,3 +444,8 @@ ulong dev_get_of_data(struct udevice *dev)
{
return dev->of_id->data;
}
enum uclass_id device_get_uclass_id(struct udevice *dev)
{
return dev->uclass->uc_drv->id;
}

8
drivers/core/root.c
View File

@ -9,6 +9,7 @@
#include <common.h>
#include <errno.h>
#include <fdtdec.h>
#include <malloc.h>
#include <libfdt.h>
#include <dm/device.h>
@ -49,6 +50,9 @@ int dm_init(void)
ret = device_bind_by_name(NULL, false, &root_info, &DM_ROOT_NON_CONST);
if (ret)
return ret;
#ifdef CONFIG_OF_CONTROL
DM_ROOT_NON_CONST->of_offset = 0;
#endif
ret = device_probe(DM_ROOT_NON_CONST);
if (ret)
return ret;
@ -89,6 +93,10 @@ int dm_scan_fdt_node(struct udevice *parent, const void *blob, int offset,
if (pre_reloc_only &&
!fdt_getprop(blob, offset, "u-boot,dm-pre-reloc", NULL))
continue;
if (!fdtdec_get_is_enabled(blob, offset)) {
dm_dbg(" - ignoring disabled device\n");
continue;
}
err = lists_bind_fdt(parent, blob, offset, NULL);
if (err && !ret)
ret = err;

34
drivers/core/uclass.c
View File

@ -319,18 +319,29 @@ int uclass_bind_device(struct udevice *dev)
int ret;
uc = dev->uclass;
list_add_tail(&dev->uclass_node, &uc->dev_head);
if (dev->parent) {
struct uclass_driver *uc_drv = dev->parent->uclass->uc_drv;
if (uc_drv->child_post_bind) {
ret = uc_drv->child_post_bind(dev);
if (ret)
goto err;
}
}
if (uc->uc_drv->post_bind) {
ret = uc->uc_drv->post_bind(dev);
if (ret) {
list_del(&dev->uclass_node);
return ret;
}
if (ret)
goto err;
}
return 0;
err:
/* There is no need to undo the parent's post_bind call */
list_del(&dev->uclass_node);
return ret;
}
int uclass_unbind_device(struct udevice *dev)
@ -380,6 +391,19 @@ int uclass_resolve_seq(struct udevice *dev)
return seq;
}
int uclass_pre_probe_child(struct udevice *dev)
{
struct uclass_driver *uc_drv;
if (!dev->parent)
return 0;
uc_drv = dev->parent->uclass->uc_drv;
if (uc_drv->child_pre_probe)
return uc_drv->child_pre_probe(dev);
return 0;
}
int uclass_post_probe_device(struct udevice *dev)
{
struct uclass_driver *uc_drv = dev->uclass->uc_drv;

1
drivers/crypto/Kconfig
View File

@ -0,0 +1 @@
source drivers/crypto/fsl/Kconfig

1
drivers/crypto/Makefile
View File

@ -6,4 +6,5 @@
#
obj-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.o
obj-y += rsa_mod_exp/
obj-y += fsl/

6
drivers/crypto/fsl/Kconfig 100644
View File

@ -0,0 +1,6 @@
config FSL_CAAM
bool "Freescale Crypto Driver Support"
help
Enables the Freescale's Cryptographic Accelerator and Assurance
Module (CAAM), also known as the SEC version 4 (SEC4). The driver uses
Job Ring as interface to communicate with CAAM.

1
drivers/crypto/fsl/Makefile
View File

@ -9,3 +9,4 @@
obj-y += sec.o
obj-$(CONFIG_FSL_CAAM) += jr.o fsl_hash.o jobdesc.o error.o
obj-$(CONFIG_CMD_BLOB) += fsl_blob.o
obj-$(CONFIG_RSA_FREESCALE_EXP) += fsl_rsa.o

60
drivers/crypto/fsl/fsl_rsa.c 100644
View File

@ -0,0 +1,60 @@
/*
* (C) Copyright 2014 Freescale Semiconductor, Inc.
* Author: Ruchika Gupta <ruchika.gupta@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <common.h>
#include <dm.h>
#include <asm/types.h>
#include <malloc.h>
#include "jobdesc.h"
#include "desc.h"
#include "jr.h"
#include "rsa_caam.h"
#include <u-boot/rsa-mod-exp.h>
int fsl_mod_exp(struct udevice *dev, const uint8_t *sig, uint32_t sig_len,
struct key_prop *prop, uint8_t *out)
{
uint32_t keylen;
struct pk_in_params pkin;
uint32_t desc[MAX_CAAM_DESCSIZE];
int ret;
/* Length in bytes */
keylen = prop->num_bits / 8;
pkin.a = sig;
pkin.a_siz = sig_len;
pkin.n = prop->modulus;
pkin.n_siz = keylen;
pkin.e = prop->public_exponent;
pkin.e_siz = prop->exp_len;
inline_cnstr_jobdesc_pkha_rsaexp(desc, &pkin, out, sig_len);
ret = run_descriptor_jr(desc);
if (ret) {
debug("%s: RSA failed to verify: %d\n", __func__, ret);
return -EFAULT;
}
return 0;
}
static const struct mod_exp_ops fsl_mod_exp_ops = {
.mod_exp = fsl_mod_exp,
};
U_BOOT_DRIVER(fsl_rsa_mod_exp) = {
.name = "fsl_rsa_mod_exp",
.id = UCLASS_MOD_EXP,
.ops = &fsl_mod_exp_ops,
};
U_BOOT_DEVICE(fsl_rsa) = {
.name = "fsl_rsa_mod_exp",
};

28
drivers/crypto/fsl/jobdesc.c
View File

@ -11,6 +11,7 @@
#include <common.h>
#include "desc_constr.h"
#include "jobdesc.h"
#include "rsa_caam.h"
#define KEY_BLOB_SIZE 32
#define MAC_SIZE 16
@ -123,3 +124,30 @@ void inline_cnstr_jobdesc_rng_instantiation(uint32_t *desc)
append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
OP_ALG_RNG4_SK);
}
/* Change key size to bytes form bits in calling function*/
void inline_cnstr_jobdesc_pkha_rsaexp(uint32_t *desc,
struct pk_in_params *pkin, uint8_t *out,
uint32_t out_siz)
{
dma_addr_t dma_addr_e, dma_addr_a, dma_addr_n, dma_addr_out;
dma_addr_e = virt_to_phys((void *)pkin->e);
dma_addr_a = virt_to_phys((void *)pkin->a);
dma_addr_n = virt_to_phys((void *)pkin->n);
dma_addr_out = virt_to_phys((void *)out);
init_job_desc(desc, 0);
append_key(desc, dma_addr_e, pkin->e_siz, KEY_DEST_PKHA_E | CLASS_1);
append_fifo_load(desc, dma_addr_a,
pkin->a_siz, LDST_CLASS_1_CCB | FIFOLD_TYPE_PK_A);
append_fifo_load(desc, dma_addr_n,
pkin->n_siz, LDST_CLASS_1_CCB | FIFOLD_TYPE_PK_N);
append_operation(desc, OP_TYPE_PK | OP_ALG_PK | OP_ALG_PKMODE_MOD_EXPO);
append_fifo_store(desc, dma_addr_out, out_siz,
LDST_CLASS_1_CCB | FIFOST_TYPE_PKHA_B);
}

5
drivers/crypto/fsl/jobdesc.h
View File

@ -10,6 +10,7 @@
#include <common.h>
#include <asm/io.h>
#include "rsa_caam.h"
#define KEY_IDNFR_SZ_BYTES 16
@ -26,4 +27,8 @@ void inline_cnstr_jobdesc_blob_decap(uint32_t *desc, uint8_t *key_idnfr,
uint32_t out_sz);
void inline_cnstr_jobdesc_rng_instantiation(uint32_t *desc);
void inline_cnstr_jobdesc_pkha_rsaexp(uint32_t *desc,
struct pk_in_params *pkin, uint8_t *out,
uint32_t out_siz);
#endif

28
drivers/crypto/fsl/rsa_caam.h 100644
View File

@ -0,0 +1,28 @@
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __RSA_CAAM_H
#define __RSA_CAAM_H
#include <common.h>
/**
* struct pk_in_params - holder for input to PKHA block in CAAM
* These parameters are required to perform Modular Exponentiation
* using PKHA Block in CAAM
*/
struct pk_in_params {
const uint8_t *e; /* public exponent as byte array */
uint32_t e_siz; /* size of e[] in number of bytes */
const uint8_t *n; /* modulus as byte array */
uint32_t n_siz; /* size of n[] in number of bytes */
const uint8_t *a; /* Signature as byte array */
uint32_t a_siz; /* size of a[] in number of bytes */
uint8_t *b; /* Result exp. modulus in number of bytes */
uint32_t b_siz; /* size of b[] in number of bytes */
};
#endif

5
drivers/crypto/rsa_mod_exp/Kconfig 100644
View File

@ -0,0 +1,5 @@
config DM_MOD_EXP
bool "Enable Driver Model for RSA Modular Exponentiation"
depends on DM
help
If you want to use driver model for RSA Modular Exponentiation, say Y.

7
drivers/crypto/rsa_mod_exp/Makefile 100644
View File

@ -0,0 +1,7 @@
#
# (C) Copyright 2014 Freescale Semiconductor, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_RSA) += mod_exp_uclass.o mod_exp_sw.o

39
drivers/crypto/rsa_mod_exp/mod_exp_sw.c 100644
View File

@ -0,0 +1,39 @@
/*
* (C) Copyright 2014 Freescale Semiconductor, Inc.
* Author: Ruchika Gupta <ruchika.gupta@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <common.h>
#include <dm.h>
#include <u-boot/rsa-mod-exp.h>
int mod_exp_sw(struct udevice *dev, const uint8_t *sig, uint32_t sig_len,
struct key_prop *prop, uint8_t *out)
{
int ret = 0;
ret = rsa_mod_exp_sw(sig, sig_len, prop, out);
if (ret) {
debug("%s: RSA failed to verify: %d\n", __func__, ret);
return ret;
}
return 0;
}
static const struct mod_exp_ops mod_exp_ops_sw = {
.mod_exp = mod_exp_sw,
};
U_BOOT_DRIVER(mod_exp_sw) = {
.name = "mod_exp_sw",
.id = UCLASS_MOD_EXP,
.ops = &mod_exp_ops_sw,
};
U_BOOT_DEVICE(mod_exp_sw) = {
.name = "mod_exp_sw",
};

31
drivers/crypto/rsa_mod_exp/mod_exp_uclass.c 100644
View File

@ -0,0 +1,31 @@
/*
* (C) Copyright 2014 Freescale Semiconductor, Inc
* Author: Ruchika Gupta <ruchika.gupta@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <u-boot/rsa-mod-exp.h>
#include <errno.h>
#include <fdtdec.h>
#include <malloc.h>
#include <asm/io.h>
#include <linux/list.h>
int rsa_mod_exp(struct udevice *dev, const uint8_t *sig, uint32_t sig_len,
struct key_prop *node, uint8_t *out)
{
const struct mod_exp_ops *ops = device_get_ops(dev);
if (!ops->mod_exp)
return -ENOSYS;
return ops->mod_exp(dev, sig, sig_len, node, out);
}
UCLASS_DRIVER(mod_exp) = {
.id = UCLASS_MOD_EXP,
.name = "rsa_mod_exp",
};

71
drivers/demo/demo-shape.c
View File

@ -11,6 +11,7 @@
#include <malloc.h>
#include <dm-demo.h>
#include <asm/io.h>
#include <asm/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
@ -20,6 +21,8 @@ DECLARE_GLOBAL_DATA_PTR;
struct shape_data {
int num_chars; /* Number of non-space characters output so far */
struct gpio_desc gpio_desc[8];
int gpio_count;
};
/* Crazy little function to draw shapes on the console */
@ -89,9 +92,52 @@ static int shape_status(struct udevice *dev, int *status)
return 0;
}
static int set_light(struct udevice *dev, int light)
{
struct shape_data *priv = dev_get_priv(dev);
struct gpio_desc *desc;
int ret;
int i;
desc = priv->gpio_desc;
for (i = 0; i < priv->gpio_count; i++, desc++) {
uint mask = 1 << i;
ret = dm_gpio_set_value(desc, light & mask);
if (ret < 0)
return ret;
}
return 0;
}
static int get_light(struct udevice *dev)
{
struct shape_data *priv = dev_get_priv(dev);
struct gpio_desc *desc;
uint value = 0;
int ret;
int i;
desc = priv->gpio_desc;
for (i = 0; i < priv->gpio_count; i++, desc++) {
uint mask = 1 << i;
ret = dm_gpio_get_value(desc);
if (ret < 0)
return ret;
if (ret)
value |= mask;
}
return value;
}
static const struct demo_ops shape_ops = {
.hello = shape_hello,
.status = shape_status,
.get_light = get_light,
.set_light = set_light,
};
static int shape_ofdata_to_platdata(struct udevice *dev)
@ -111,6 +157,29 @@ static int shape_ofdata_to_platdata(struct udevice *dev)
return 0;
}
static int dm_shape_probe(struct udevice *dev)
{
struct shape_data *priv = dev_get_priv(dev);
int ret;
ret = gpio_request_list_by_name(dev, "light-gpios", priv->gpio_desc,
ARRAY_SIZE(priv->gpio_desc),
GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
if (ret < 0)
return ret;
priv->gpio_count = ret;
debug("%s: %d GPIOs\n", __func__, priv->gpio_count);
return 0;
}
static int dm_shape_remove(struct udevice *dev)
{
struct shape_data *priv = dev_get_priv(dev);
return gpio_free_list(dev, priv->gpio_desc, priv->gpio_count);
}
static const struct udevice_id demo_shape_id[] = {
{ "demo-shape", 0 },
{ },
@ -122,6 +191,8 @@ U_BOOT_DRIVER(demo_shape_drv) = {
.id = UCLASS_DEMO,
.ofdata_to_platdata = shape_ofdata_to_platdata,
.ops = &shape_ops,
.probe = dm_shape_probe,
.remove = dm_shape_remove,
.priv_auto_alloc_size = sizeof(struct shape_data),
.platdata_auto_alloc_size = sizeof(struct dm_demo_pdata),
};

20
drivers/demo/demo-uclass.c
View File

@ -43,6 +43,26 @@ int demo_status(struct udevice *dev, int *status)
return ops->status(dev, status);
}
int demo_get_light(struct udevice *dev)
{
const struct demo_ops *ops = device_get_ops(dev);
if (!ops->get_light)
return -ENOSYS;
return ops->get_light(dev);
}
int demo_set_light(struct udevice *dev, int light)
{
const struct demo_ops *ops = device_get_ops(dev);
if (!ops->set_light)
return -ENOSYS;
return ops->set_light(dev, light);
}
int demo_parse_dt(struct udevice *dev)
{
struct dm_demo_pdata *pdata = dev_get_platdata(dev);

396
drivers/gpio/gpio-uclass.c
View File

@ -7,20 +7,25 @@
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
#include <malloc.h>
#include <asm/gpio.h>
#include <linux/ctype.h>
DECLARE_GLOBAL_DATA_PTR;
/**
* gpio_to_device() - Convert global GPIO number to device, number
* gpio: The numeric representation of the GPIO
*
* Convert the GPIO number to an entry in the list of GPIOs
* or GPIO blocks registered with the GPIO controller. Returns
* entry on success, NULL on error.
*
* @gpio: The numeric representation of the GPIO
* @desc: Returns description (desc->flags will always be 0)
* @return 0 if found, -ENOENT if not found
*/
static int gpio_to_device(unsigned int gpio, struct udevice **devp,
unsigned int *offset)
static int gpio_to_device(unsigned int gpio, struct gpio_desc *desc)
{
struct gpio_dev_priv *uc_priv;
struct udevice *dev;
@ -32,14 +37,15 @@ static int gpio_to_device(unsigned int gpio, struct udevice **devp,
uc_priv = dev->uclass_priv;
if (gpio >= uc_priv->gpio_base &&
gpio < uc_priv->gpio_base + uc_priv->gpio_count) {
*devp = dev;
*offset = gpio - uc_priv->gpio_base;
desc->dev = dev;
desc->offset = gpio - uc_priv->gpio_base;
desc->flags = 0;
return 0;
}
}
/* No such GPIO */
return ret ? ret : -EINVAL;
return ret ? ret : -ENOENT;
}
int gpio_lookup_name(const char *name, struct udevice **devp,
@ -88,6 +94,57 @@ int gpio_lookup_name(const char *name, struct udevice **devp,
return 0;
}
static int gpio_find_and_xlate(struct gpio_desc *desc,
struct fdtdec_phandle_args *args)
{
struct dm_gpio_ops *ops = gpio_get_ops(desc->dev);
/* Use the first argument as the offset by default */
if (args->args_count > 0)
desc->offset = args->args[0];
else
desc->offset = -1;
desc->flags = 0;
return ops->xlate ? ops->xlate(desc->dev, desc, args) : 0;
}
static int dm_gpio_request(struct gpio_desc *desc, const char *label)
{
struct udevice *dev = desc->dev;
struct gpio_dev_priv *uc_priv;
char *str;
int ret;
uc_priv = dev->uclass_priv;
if (uc_priv->name[desc->offset])
return -EBUSY;
str = strdup(label);
if (!str)
return -ENOMEM;
if (gpio_get_ops(dev)->request) {
ret = gpio_get_ops(dev)->request(dev, desc->offset, label);
if (ret) {
free(str);
return ret;
}
}
uc_priv->name[desc->offset] = str;
return 0;
}
static int dm_gpio_requestf(struct gpio_desc *desc, const char *fmt, ...)
{
va_list args;
char buf[40];
va_start(args, fmt);
vscnprintf(buf, sizeof(buf), fmt, args);
va_end(args);
return dm_gpio_request(desc, buf);
}
/**
* gpio_request() - [COMPAT] Request GPIO
* gpio: GPIO number
@ -102,32 +159,14 @@ int gpio_lookup_name(const char *name, struct udevice **devp,
*/
int gpio_request(unsigned gpio, const char *label)
{
struct gpio_dev_priv *uc_priv;
unsigned int offset;
struct udevice *dev;
char *str;
struct gpio_desc desc;
int ret;
ret = gpio_to_device(gpio, &dev, &offset);
ret = gpio_to_device(gpio, &desc);
if (ret)
return ret;
uc_priv = dev->uclass_priv;
if (uc_priv->name[offset])
return -EBUSY;
str = strdup(label);
if (!str)
return -ENOMEM;
if (gpio_get_ops(dev)->request) {
ret = gpio_get_ops(dev)->request(dev, offset, label);
if (ret) {
free(str);
return ret;
}
}
uc_priv->name[offset] = str;
return 0;
return dm_gpio_request(&desc, label);
}
/**
@ -151,25 +190,11 @@ int gpio_requestf(unsigned gpio, const char *fmt, ...)
return gpio_request(gpio, buf);
}
/**
* gpio_free() - [COMPAT] Relinquish GPIO
* gpio: GPIO number
*
* This function implements the API that's compatible with current
* GPIO API used in U-Boot. The request is forwarded to particular
* GPIO driver. Returns 0 on success, negative value on error.
*/
int gpio_free(unsigned gpio)
int _dm_gpio_free(struct udevice *dev, uint offset)
{
struct gpio_dev_priv *uc_priv;
unsigned int offset;
struct udevice *dev;
int ret;
ret = gpio_to_device(gpio, &dev, &offset);
if (ret)
return ret;
uc_priv = dev->uclass_priv;
if (!uc_priv->name[offset])
return -ENXIO;
@ -185,15 +210,35 @@ int gpio_free(unsigned gpio)
return 0;
}
static int check_reserved(struct udevice *dev, unsigned offset,
const char *func)
/**
* gpio_free() - [COMPAT] Relinquish GPIO
* gpio: GPIO number
*
* This function implements the API that's compatible with current
* GPIO API used in U-Boot. The request is forwarded to particular
* GPIO driver. Returns 0 on success, negative value on error.
*/
int gpio_free(unsigned gpio)
{
struct gpio_dev_priv *uc_priv = dev->uclass_priv;
struct gpio_desc desc;
int ret;
if (!uc_priv->name[offset]) {
ret = gpio_to_device(gpio, &desc);
if (ret)
return ret;
return _dm_gpio_free(desc.dev, desc.offset);
}
static int check_reserved(struct gpio_desc *desc, const char *func)
{
struct gpio_dev_priv *uc_priv = desc->dev->uclass_priv;
if (!uc_priv->name[desc->offset]) {
printf("%s: %s: error: gpio %s%d not reserved\n",
dev->name, func,
uc_priv->bank_name ? uc_priv->bank_name : "", offset);
desc->dev->name, func,
uc_priv->bank_name ? uc_priv->bank_name : "",
desc->offset);
return -EBUSY;
}
@ -210,16 +255,17 @@ static int check_reserved(struct udevice *dev, unsigned offset,
*/
int gpio_direction_input(unsigned gpio)
{
unsigned int offset;
struct udevice *dev;
struct gpio_desc desc;
int ret;
ret = gpio_to_device(gpio, &dev, &offset);
ret = gpio_to_device(gpio, &desc);
if (ret)
return ret;
ret = check_reserved(&desc, "dir_input");
if (ret)
return ret;
ret = check_reserved(dev, offset, "dir_input");
return ret ? ret : gpio_get_ops(dev)->direction_input(dev, offset);
return gpio_get_ops(desc.dev)->direction_input(desc.dev, desc.offset);
}
/**
@ -233,17 +279,81 @@ int gpio_direction_input(unsigned gpio)
*/
int gpio_direction_output(unsigned gpio, int value)
{
unsigned int offset;
struct udevice *dev;
struct gpio_desc desc;
int ret;
ret = gpio_to_device(gpio, &dev, &offset);
ret = gpio_to_device(gpio, &desc);
if (ret)
return ret;
ret = check_reserved(&desc, "dir_output");
if (ret)
return ret;
ret = check_reserved(dev, offset, "dir_output");
return ret ? ret :
gpio_get_ops(dev)->direction_output(dev, offset, value);
return gpio_get_ops(desc.dev)->direction_output(desc.dev,
desc.offset, value);
}
int dm_gpio_get_value(struct gpio_desc *desc)
{
int value;
int ret;
ret = check_reserved(desc, "get_value");
if (ret)
return ret;
value = gpio_get_ops(desc->dev)->get_value(desc->dev, desc->offset);
return desc->flags & GPIOD_ACTIVE_LOW ? !value : value;
}
int dm_gpio_set_value(struct gpio_desc *desc, int value)
{
int ret;
ret = check_reserved(desc, "set_value");
if (ret)
return ret;
if (desc->flags & GPIOD_ACTIVE_LOW)
value = !value;
gpio_get_ops(desc->dev)->set_value(desc->dev, desc->offset, value);
return 0;
}
int dm_gpio_set_dir_flags(struct gpio_desc *desc, ulong flags)
{
struct udevice *dev = desc->dev;
struct dm_gpio_ops *ops = gpio_get_ops(dev);
int ret;
ret = check_reserved(desc, "set_dir");
if (ret)
return ret;
if (flags & GPIOD_IS_OUT) {
int value = flags & GPIOD_IS_OUT_ACTIVE ? 1 : 0;
if (flags & GPIOD_ACTIVE_LOW)
value = !value;
ret = ops->direction_output(dev, desc->offset, value);
} else if (flags & GPIOD_IS_IN) {
ret = ops->direction_input(dev, desc->offset);
}
if (ret)
return ret;
/*
* Update desc->flags here, so that GPIO_ACTIVE_LOW is honoured in
* futures
*/
desc->flags = flags;
return 0;
}
int dm_gpio_set_dir(struct gpio_desc *desc)
{
return dm_gpio_set_dir_flags(desc, desc->flags);
}
/**
@ -257,16 +367,14 @@ int gpio_direction_output(unsigned gpio, int value)
*/
int gpio_get_value(unsigned gpio)
{
unsigned int offset;
struct udevice *dev;
int ret;
ret = gpio_to_device(gpio, &dev, &offset);
struct gpio_desc desc;
ret = gpio_to_device(gpio, &desc);
if (ret)
return ret;
ret = check_reserved(dev, offset, "get_value");
return ret ? ret : gpio_get_ops(dev)->get_value(dev, offset);
return dm_gpio_get_value(&desc);
}
/**
@ -280,16 +388,13 @@ int gpio_get_value(unsigned gpio)
*/
int gpio_set_value(unsigned gpio, int value)
{
unsigned int offset;
struct udevice *dev;
struct gpio_desc desc;
int ret;
ret = gpio_to_device(gpio, &dev, &offset);
ret = gpio_to_device(gpio, &desc);
if (ret)
return ret;
ret = check_reserved(dev, offset, "set_value");
return ret ? ret : gpio_get_ops(dev)->set_value(dev, offset, value);
return dm_gpio_set_value(&desc, value);
}
const char *gpio_get_bank_info(struct udevice *dev, int *bit_count)
@ -409,6 +514,155 @@ unsigned gpio_get_values_as_int(const int *gpio_num_array)
return vector;
}
static int _gpio_request_by_name_nodev(const void *blob, int node,
const char *list_name, int index,
struct gpio_desc *desc, int flags,
bool add_index)
{
struct fdtdec_phandle_args args;
int ret;
desc->dev = NULL;
desc->offset = 0;
ret = fdtdec_parse_phandle_with_args(blob, node, list_name,
"#gpio-cells", 0, index, &args);
if (ret) {
debug("%s: fdtdec_parse_phandle_with_args failed\n", __func__);
goto err;
}
ret = uclass_get_device_by_of_offset(UCLASS_GPIO, args.node,
&desc->dev);
if (ret) {
debug("%s: uclass_get_device_by_of_offset failed\n", __func__);
goto err;
}
ret = gpio_find_and_xlate(desc, &args);
if (ret) {
debug("%s: gpio_find_and_xlate failed\n", __func__);
goto err;
}
ret = dm_gpio_requestf(desc, add_index ? "%s.%s%d" : "%s.%s",
fdt_get_name(blob, node, NULL),
list_name, index);
if (ret) {
debug("%s: dm_gpio_requestf failed\n", __func__);
goto err;
}
ret = dm_gpio_set_dir_flags(desc, flags | desc->flags);
if (ret) {
debug("%s: dm_gpio_set_dir failed\n", __func__);
goto err;
}
return 0;
err:
debug("%s: Node '%s', property '%s', failed to request GPIO index %d: %d\n",
__func__, fdt_get_name(blob, node, NULL), list_name, index, ret);
return ret;
}
int gpio_request_by_name_nodev(const void *blob, int node,
const char *list_name, int index,
struct gpio_desc *desc, int flags)
{
return _gpio_request_by_name_nodev(blob, node, list_name, index, desc,
flags, index > 0);
}
int gpio_request_by_name(struct udevice *dev, const char *list_name, int index,
struct gpio_desc *desc, int flags)
{
/*
* This isn't ideal since we don't use dev->name in the debug()
* calls in gpio_request_by_name(), but we can do this until
* gpio_request_by_name_nodev() can be dropped.
*/
return gpio_request_by_name_nodev(gd->fdt_blob, dev->of_offset,
list_name, index, desc, flags);
}
int gpio_request_list_by_name_nodev(const void *blob, int node,
const char *list_name,
struct gpio_desc *desc, int max_count,
int flags)
{
int count;
int ret;
for (count = 0; ; count++) {
if (count >= max_count) {
ret = -ENOSPC;
goto err;
}
ret = _gpio_request_by_name_nodev(blob, node, list_name, count,
&desc[count], flags, true);
if (ret == -ENOENT)
break;
else if (ret)
goto err;
}
/* We ran out of GPIOs in the list */
return count;
err:
gpio_free_list_nodev(desc, count - 1);
return ret;
}
int gpio_request_list_by_name(struct udevice *dev, const char *list_name,
struct gpio_desc *desc, int max_count,
int flags)
{
/*
* This isn't ideal since we don't use dev->name in the debug()
* calls in gpio_request_by_name(), but we can do this until
* gpio_request_list_by_name_nodev() can be dropped.
*/
return gpio_request_list_by_name_nodev(gd->fdt_blob, dev->of_offset,
list_name, desc, max_count,
flags);
}
int gpio_get_list_count(struct udevice *dev, const char *list_name)
{
int ret;
ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset,
list_name, "#gpio-cells", 0, -1,
NULL);
if (ret) {
debug("%s: Node '%s', property '%s', GPIO count failed: %d\n",
__func__, dev->name, list_name, ret);
}
return ret;
}
int dm_gpio_free(struct udevice *dev, struct gpio_desc *desc)
{
/* For now, we don't do any checking of dev */
return _dm_gpio_free(desc->dev, desc->offset);
}
int gpio_free_list(struct udevice *dev, struct gpio_desc *desc, int count)
{
int i;
/* For now, we don't do any checking of dev */
for (i = 0; i < count; i++)
dm_gpio_free(dev, &desc[i]);
return 0;
}
int gpio_free_list_nodev(struct gpio_desc *desc, int count)
{
return gpio_free_list(NULL, desc, count);
}
/* We need to renumber the GPIOs when any driver is probed/removed */
static int gpio_renumber(struct udevice *removed_dev)
{

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