net: sh_eth: add support for SH7757's ETHER
SH7757 has ETHER and GETHER. This patch supports EHTER only. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>utp
Yoshihiro Shimoda
Nobuhiro Iwamatsu
parent
cc1dd33f27
commit
903de461e4
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@ -277,6 +277,7 @@ int sh_eth_recv(struct eth_device *dev)
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static int sh_eth_reset(struct sh_eth_dev *eth)
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{
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int port = eth->port;
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#if defined(CONFIG_CPU_SH7763)
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int ret = 0, i;
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/* Start e-dmac transmitter and receiver */
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@ -296,6 +297,13 @@ static int sh_eth_reset(struct sh_eth_dev *eth)
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}
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return ret;
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#else
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outl(inl(EDMR(port)) | EDMR_SRST, EDMR(port));
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udelay(3000);
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outl(inl(EDMR(port)) & ~EDMR_SRST, EDMR(port));
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return 0;
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#endif
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}
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static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
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@ -339,9 +347,11 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
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/* Point the controller to the tx descriptor list. Must use physical
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addresses */
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outl(ADDR_TO_PHY(port_info->tx_desc_base), TDLAR(port));
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#if defined(CONFIG_CPU_SH7763)
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outl(ADDR_TO_PHY(port_info->tx_desc_base), TDFAR(port));
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outl(ADDR_TO_PHY(cur_tx_desc), TDFXR(port));
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outl(0x01, TDFFR(port));/* Last discriptor bit */
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#endif
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err:
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return ret;
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@ -405,9 +415,11 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
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/* Point the controller to the rx descriptor list */
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outl(ADDR_TO_PHY(port_info->rx_desc_base), RDLAR(port));
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#if defined(CONFIG_CPU_SH7763)
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outl(ADDR_TO_PHY(port_info->rx_desc_base), RDFAR(port));
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outl(ADDR_TO_PHY(cur_rx_desc), RDFXR(port));
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outl(RDFFR_RDLF, RDFFR(port));
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#endif
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return ret;
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@ -532,11 +544,18 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
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outl(0, TFTR(port));
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outl((FIFO_SIZE_T | FIFO_SIZE_R), FDR(port));
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outl(RMCR_RST, RMCR(port));
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#ifndef CONFIG_CPU_SH7757
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outl(0, RPADIR(port));
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#endif
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outl((FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR(port));
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/* Configure e-mac registers */
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#if defined(CONFIG_CPU_SH7757)
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outl(ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP |
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ECSIPR_MPDIP | ECSIPR_ICDIP, ECSIPR(port));
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#else
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outl(0, ECSIPR(port));
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#endif
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/* Set Mac address */
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val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 |
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@ -547,11 +566,16 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
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outl(val, MALR(port));
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outl(RFLR_RFL_MIN, RFLR(port));
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#ifndef CONFIG_CPU_SH7757
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outl(0, PIPR(port));
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#endif
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outl(APR_AP, APR(port));
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outl(MPR_MP, MPR(port));
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#ifdef CONFIG_CPU_SH7757
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outl(TPAUSER_UNLIMITED, TPAUSER(port));
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#else
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outl(TPAUSER_TPAUSE, TPAUSER(port));
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#endif
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/* Configure phy */
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ret = sh_eth_phy_config(eth);
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if (ret) {
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@ -562,6 +586,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
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phy_status = sh_eth_mii_read_phy_reg(port, port_info->phy_addr, 1);
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/* Set the transfer speed */
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#ifdef CONFIG_CPU_SH7763
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if (phy_status & (PHY_S_100X_F|PHY_S_100X_H)) {
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printf(SHETHER_NAME ": 100Base/");
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outl(GECMR_100B, GECMR(port));
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@ -569,6 +594,16 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
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printf(SHETHER_NAME ": 10Base/");
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outl(GECMR_10B, GECMR(port));
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}
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#endif
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#if defined(CONFIG_CPU_SH7757)
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if (phy_status & (PHY_S_100X_F|PHY_S_100X_H)) {
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printf("100Base/");
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outl(1, RTRATE(port));
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} else {
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printf("10Base/");
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outl(0, RTRATE(port));
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}
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#endif
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/* Check if full duplex mode is supported by the phy */
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if (phy_status & (PHY_S_100X_F|PHY_S_10T_F)) {
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@ -1,5 +1,5 @@
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/*
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* sh_eth.h - Driver for Renesas SH7763's gigabit ethernet controler.
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* sh_eth.h - Driver for Renesas SuperH ethernet controler.
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*
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* Copyright (C) 2008 Renesas Solutions Corp.
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* Copyright (c) 2008 Nobuhiro Iwamatsu
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@ -30,7 +30,11 @@
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#define ADDR_TO_P2(addr) ((((int)(addr) & ~0xe0000000) | 0xa0000000))
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/* The ethernet controller needs to use physical addresses */
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#if defined(CONFIG_SH_32BIT)
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#define ADDR_TO_PHY(addr) ((((int)(addr) & ~0xe0000000) | 0x40000000))
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#else
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#define ADDR_TO_PHY(addr) ((int)(addr) & ~0xe0000000)
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#endif
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/* Number of supported ports */
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#define MAX_PORT_NUM 2
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@ -93,6 +97,7 @@ struct sh_eth_dev {
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};
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/* Register Address */
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#ifdef CONFIG_CPU_SH7763
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#define BASE_IO_ADDR 0xfee00000
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#define EDSR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0000)
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@ -130,6 +135,34 @@ struct sh_eth_dev {
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#define MALR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05c8)
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#define MAHR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05c0)
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#elif defined(CONFIG_CPU_SH7757)
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#define BASE_IO_ADDR 0xfef00000
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#define TDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0018)
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#define RDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0020)
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#define EDMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0000)
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#define EDTRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0008)
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#define EDRRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0010)
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#define EESR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0028)
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#define EESIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0030)
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#define TRSCER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0038)
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#define TFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0048)
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#define FDR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0050)
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#define RMCR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0058)
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#define FCFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0070)
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#define ECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0100)
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#define RFLR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0108)
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#define ECSIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0118)
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#define PIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0120)
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#define APR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0154)
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#define MPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0158)
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#define TPAUSER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0164)
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#define MAHR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01c0)
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#define MALR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01c8)
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#define RTRATE(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01fc)
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#endif
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/*
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* Register's bits
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* Copy from Linux driver source code
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@ -149,6 +182,10 @@ enum DMAC_M_BIT {
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EDMR_SRST = 0x03,
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EMDR_DESC_R = 0x30, /* Descriptor reserve size */
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EDMR_EL = 0x40, /* Litte endian */
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#elif defined CONFIG_CPU_SH7757
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EDMR_SRST = 0x01,
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EMDR_DESC_R = 0x30, /* Descriptor reserve size */
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EDMR_EL = 0x40, /* Litte endian */
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#else /* CONFIG_CPU_SH7763 */
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EDMR_SRST = 0x01,
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#endif
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@ -287,7 +324,7 @@ enum FCFTR_BIT {
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/* Transfer descriptor bit */
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enum TD_STS_BIT {
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#ifdef CONFIG_CPU_SH7763
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#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7757)
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TD_TACT = 0x80000000,
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#else
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TD_TACT = 0x7fffffff,
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@ -317,8 +354,10 @@ enum FELIC_MODE_BIT {
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#ifdef CONFIG_CPU_SH7763
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#define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \
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ECMR_TXF | ECMR_MCT)
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#elif CONFIG_CPU_SH7757
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#define ECMR_CHG_DM (ECMR_ZPF)
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#else
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#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR ECMR_RXF | ECMR_TXF | ECMR_MCT)
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#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
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#endif
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/* ECSR */
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@ -355,12 +394,20 @@ enum ECSIPR_STATUS_MASK_BIT {
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/* APR */
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enum APR_BIT {
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#ifdef CONFIG_CPU_SH7757
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APR_AP = 0x00000001,
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#else
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APR_AP = 0x00000004,
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#endif
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};
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/* MPR */
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enum MPR_BIT {
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#ifdef CONFIG_CPU_SH7757
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MPR_MP = 0x00000001,
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#else
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MPR_MP = 0x00000006,
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#endif
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};
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/* TRSCER */
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