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sunxi: Fix 2nd usb controller on sun4i/sun7i no longer working 

The 2nd usb controller on sun4i/sun7i has its base address 0x8000
bytes from the 1st one, rather then 0x1000. Also the ahb clk gates
are interleaved with the ohci clk-gates introducing a hole between
the clks for usb1 and usb2.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
utp
Hans de Goede 2016-03-21 14:44:35 +01:00
parent 9284f3b452
commit 948603d4d6
2 changed files with 23 additions and 5 deletions
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13
drivers/usb/host/ehci-sunxi.c
View File

@ -17,6 +17,14 @@
#include <dm.h>
#include "ehci.h"
#ifdef CONFIG_SUNXI_GEN_SUN4I
#define BASE_DIST 0x8000
#define AHB_CLK_DIST 2
#else
#define BASE_DIST 0x1000
#define AHB_CLK_DIST 1
#endif
struct ehci_sunxi_priv {
struct ehci_ctrl ehci;
int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */
@ -39,8 +47,9 @@ static int ehci_usb_probe(struct udevice *dev)
#ifdef CONFIG_MACH_SUN8I_H3
priv->ahb_gate_mask |= 1 << AHB_GATE_OFFSET_USB_OHCI0;
#endif
priv->phy_index = ((u32)hccr - SUNXI_USB1_BASE) / 0x1000 + 1;
priv->ahb_gate_mask <<= priv->phy_index - 1;
priv->phy_index = ((u32)hccr - SUNXI_USB1_BASE) / BASE_DIST;
priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
priv->phy_index++; /* Non otg phys start at 1 */
setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask);
#ifdef CONFIG_SUNXI_GEN_SUN6I

15
drivers/usb/host/ohci-sunxi.c
View File

@ -17,6 +17,14 @@
#include <usb.h>
#include "ohci.h"
#ifdef CONFIG_SUNXI_GEN_SUN4I
#define BASE_DIST 0x8000
#define AHB_CLK_DIST 2
#else
#define BASE_DIST 0x1000
#define AHB_CLK_DIST 1
#endif
struct ohci_sunxi_priv {
ohci_t ohci;
int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */
@ -42,9 +50,10 @@ static int ohci_usb_probe(struct udevice *dev)
priv->ahb_gate_mask |= 1 << AHB_GATE_OFFSET_USB_EHCI0;
#endif
priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
priv->phy_index = ((u32)regs - (SUNXI_USB1_BASE + 0x400)) / 0x1000 + 1;
priv->ahb_gate_mask <<= priv->phy_index - 1;
priv->usb_gate_mask <<= priv->phy_index - 1;
priv->phy_index = ((u32)regs - (SUNXI_USB1_BASE + 0x400)) / BASE_DIST;
priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
priv->usb_gate_mask <<= priv->phy_index;
priv->phy_index++; /* Non otg phys start at 1 */
setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask);
setbits_le32(&ccm->usb_clk_cfg, priv->usb_gate_mask);